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spi-topcliff-pch: Fix issue for transmitting over 4KByte
[zen-stable.git] / arch / arm / mach-msm / devices-msm7x00.c
blob993780f490ada952cf54f80aa184c7ed53c68985
1 /* linux/arch/arm/mach-msm/devices.c
2 *
3 * Copyright (C) 2008 Google, Inc.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/platform_device.h>
18 #include <linux/clkdev.h>
19
20 #include <mach/irqs.h>
21 #include <mach/msm_iomap.h>
22 #include "devices.h"
23
24 #include <asm/mach/flash.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27
28 #include "clock.h"
29 #include "clock-pcom.h"
30 #include <mach/mmc.h>
31
32 static struct resource resources_uart1[] = {
33 {
34 .start = INT_UART1,
35 .end = INT_UART1,
36 .flags = IORESOURCE_IRQ,
37 },
38 {
39 .start = MSM_UART1_PHYS,
40 .end = MSM_UART1_PHYS + MSM_UART1_SIZE - 1,
41 .flags = IORESOURCE_MEM,
42 .name = "uart_resource"
43 },
44 };
45
46 static struct resource resources_uart2[] = {
47 {
48 .start = INT_UART2,
49 .end = INT_UART2,
50 .flags = IORESOURCE_IRQ,
51 },
52 {
53 .start = MSM_UART2_PHYS,
54 .end = MSM_UART2_PHYS + MSM_UART2_SIZE - 1,
55 .flags = IORESOURCE_MEM,
56 .name = "uart_resource"
57 },
58 };
59
60 static struct resource resources_uart3[] = {
61 {
62 .start = INT_UART3,
63 .end = INT_UART3,
64 .flags = IORESOURCE_IRQ,
65 },
66 {
67 .start = MSM_UART3_PHYS,
68 .end = MSM_UART3_PHYS + MSM_UART3_SIZE - 1,
69 .flags = IORESOURCE_MEM,
70 .name = "uart_resource"
71 },
72 };
73
74 struct platform_device msm_device_uart1 = {
75 .name = "msm_serial",
76 .id = 0,
77 .num_resources = ARRAY_SIZE(resources_uart1),
78 .resource = resources_uart1,
79 };
80
81 struct platform_device msm_device_uart2 = {
82 .name = "msm_serial",
83 .id = 1,
84 .num_resources = ARRAY_SIZE(resources_uart2),
85 .resource = resources_uart2,
86 };
87
88 struct platform_device msm_device_uart3 = {
89 .name = "msm_serial",
90 .id = 2,
91 .num_resources = ARRAY_SIZE(resources_uart3),
92 .resource = resources_uart3,
93 };
94
95 static struct resource resources_i2c[] = {
96 {
97 .start = MSM_I2C_PHYS,
98 .end = MSM_I2C_PHYS + MSM_I2C_SIZE - 1,
99 .flags = IORESOURCE_MEM,
100 },
101 {
102 .start = INT_PWB_I2C,
103 .end = INT_PWB_I2C,
104 .flags = IORESOURCE_IRQ,
105 },
106 };
107
108 struct platform_device msm_device_i2c = {
109 .name = "msm_i2c",
110 .id = 0,
111 .num_resources = ARRAY_SIZE(resources_i2c),
112 .resource = resources_i2c,
113 };
114
115 static struct resource resources_hsusb[] = {
116 {
117 .start = MSM_HSUSB_PHYS,
118 .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
119 .flags = IORESOURCE_MEM,
120 },
121 {
122 .start = INT_USB_HS,
123 .end = INT_USB_HS,
124 .flags = IORESOURCE_IRQ,
125 },
126 };
127
128 struct platform_device msm_device_hsusb = {
129 .name = "msm_hsusb",
130 .id = -1,
131 .num_resources = ARRAY_SIZE(resources_hsusb),
132 .resource = resources_hsusb,
133 .dev = {
134 .coherent_dma_mask = 0xffffffff,
135 },
136 };
137
138 struct flash_platform_data msm_nand_data = {
139 .parts = NULL,
140 .nr_parts = 0,
141 };
142
143 static struct resource resources_nand[] = {
144 [0] = {
145 .start = 7,
146 .end = 7,
147 .flags = IORESOURCE_DMA,
148 },
149 };
150
151 struct platform_device msm_device_nand = {
152 .name = "msm_nand",
153 .id = -1,
154 .num_resources = ARRAY_SIZE(resources_nand),
155 .resource = resources_nand,
156 .dev = {
157 .platform_data = &msm_nand_data,
158 },
159 };
160
161 struct platform_device msm_device_smd = {
162 .name = "msm_smd",
163 .id = -1,
164 };
165
166 static struct resource resources_sdc1[] = {
167 {
168 .start = MSM_SDC1_PHYS,
169 .end = MSM_SDC1_PHYS + MSM_SDC1_SIZE - 1,
170 .flags = IORESOURCE_MEM,
171 },
172 {
173 .start = INT_SDC1_0,
174 .end = INT_SDC1_0,
175 .flags = IORESOURCE_IRQ,
176 .name = "cmd_irq",
177 },
178 {
179 .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
180 .name = "status_irq"
181 },
182 {
183 .start = 8,
184 .end = 8,
185 .flags = IORESOURCE_DMA,
186 },
187 };
188
189 static struct resource resources_sdc2[] = {
190 {
191 .start = MSM_SDC2_PHYS,
192 .end = MSM_SDC2_PHYS + MSM_SDC2_SIZE - 1,
193 .flags = IORESOURCE_MEM,
194 },
195 {
196 .start = INT_SDC2_0,
197 .end = INT_SDC2_0,
198 .flags = IORESOURCE_IRQ,
199 .name = "cmd_irq",
200 },
201 {
202 .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
203 .name = "status_irq"
204 },
205 {
206 .start = 8,
207 .end = 8,
208 .flags = IORESOURCE_DMA,
209 },
210 };
211
212 static struct resource resources_sdc3[] = {
213 {
214 .start = MSM_SDC3_PHYS,
215 .end = MSM_SDC3_PHYS + MSM_SDC3_SIZE - 1,
216 .flags = IORESOURCE_MEM,
217 },
218 {
219 .start = INT_SDC3_0,
220 .end = INT_SDC3_0,
221 .flags = IORESOURCE_IRQ,
222 .name = "cmd_irq",
223 },
224 {
225 .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
226 .name = "status_irq"
227 },
228 {
229 .start = 8,
230 .end = 8,
231 .flags = IORESOURCE_DMA,
232 },
233 };
234
235 static struct resource resources_sdc4[] = {
236 {
237 .start = MSM_SDC4_PHYS,
238 .end = MSM_SDC4_PHYS + MSM_SDC4_SIZE - 1,
239 .flags = IORESOURCE_MEM,
240 },
241 {
242 .start = INT_SDC4_0,
243 .end = INT_SDC4_0,
244 .flags = IORESOURCE_IRQ,
245 .name = "cmd_irq",
246 },
247 {
248 .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
249 .name = "status_irq"
250 },
251 {
252 .start = 8,
253 .end = 8,
254 .flags = IORESOURCE_DMA,
255 },
256 };
257
258 struct platform_device msm_device_sdc1 = {
259 .name = "msm_sdcc",
260 .id = 1,
261 .num_resources = ARRAY_SIZE(resources_sdc1),
262 .resource = resources_sdc1,
263 .dev = {
264 .coherent_dma_mask = 0xffffffff,
265 },
266 };
267
268 struct platform_device msm_device_sdc2 = {
269 .name = "msm_sdcc",
270 .id = 2,
271 .num_resources = ARRAY_SIZE(resources_sdc2),
272 .resource = resources_sdc2,
273 .dev = {
274 .coherent_dma_mask = 0xffffffff,
275 },
276 };
277
278 struct platform_device msm_device_sdc3 = {
279 .name = "msm_sdcc",
280 .id = 3,
281 .num_resources = ARRAY_SIZE(resources_sdc3),
282 .resource = resources_sdc3,
283 .dev = {
284 .coherent_dma_mask = 0xffffffff,
285 },
286 };
287
288 struct platform_device msm_device_sdc4 = {
289 .name = "msm_sdcc",
290 .id = 4,
291 .num_resources = ARRAY_SIZE(resources_sdc4),
292 .resource = resources_sdc4,
293 .dev = {
294 .coherent_dma_mask = 0xffffffff,
295 },
296 };
297
298 static struct platform_device *msm_sdcc_devices[] __initdata = {
299 &msm_device_sdc1,
300 &msm_device_sdc2,
301 &msm_device_sdc3,
302 &msm_device_sdc4,
303 };
304
305 int __init msm_add_sdcc(unsigned int controller,
306 struct msm_mmc_platform_data *plat,
307 unsigned int stat_irq, unsigned long stat_irq_flags)
308 {
309 struct platform_device *pdev;
310 struct resource *res;
311
312 if (controller < 1 || controller > 4)
313 return -EINVAL;
314
315 pdev = msm_sdcc_devices[controller-1];
316 pdev->dev.platform_data = plat;
317
318 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "status_irq");
319 if (!res)
320 return -EINVAL;
321 else if (stat_irq) {
322 res->start = res->end = stat_irq;
323 res->flags &= ~IORESOURCE_DISABLED;
324 res->flags |= stat_irq_flags;
325 }
326
327 return platform_device_register(pdev);
328 }
329
330 static struct resource resources_mddi0[] = {
331 {
332 .start = MSM_PMDH_PHYS,
333 .end = MSM_PMDH_PHYS + MSM_PMDH_SIZE - 1,
334 .flags = IORESOURCE_MEM,
335 },
336 {
337 .start = INT_MDDI_PRI,
338 .end = INT_MDDI_PRI,
339 .flags = IORESOURCE_IRQ,
340 },
341 };
342
343 static struct resource resources_mddi1[] = {
344 {
345 .start = MSM_EMDH_PHYS,
346 .end = MSM_EMDH_PHYS + MSM_EMDH_SIZE - 1,
347 .flags = IORESOURCE_MEM,
348 },
349 {
350 .start = INT_MDDI_EXT,
351 .end = INT_MDDI_EXT,
352 .flags = IORESOURCE_IRQ,
353 },
354 };
355
356 struct platform_device msm_device_mddi0 = {
357 .name = "msm_mddi",
358 .id = 0,
359 .num_resources = ARRAY_SIZE(resources_mddi0),
360 .resource = resources_mddi0,
361 .dev = {
362 .coherent_dma_mask = 0xffffffff,
363 },
364 };
365
366 struct platform_device msm_device_mddi1 = {
367 .name = "msm_mddi",
368 .id = 1,
369 .num_resources = ARRAY_SIZE(resources_mddi1),
370 .resource = resources_mddi1,
371 .dev = {
372 .coherent_dma_mask = 0xffffffff,
373 },
374 };
375
376 static struct resource resources_mdp[] = {
377 {
378 .start = MSM_MDP_PHYS,
379 .end = MSM_MDP_PHYS + MSM_MDP_SIZE - 1,
380 .name = "mdp",
381 .flags = IORESOURCE_MEM
382 },
383 {
384 .start = INT_MDP,
385 .end = INT_MDP,
386 .flags = IORESOURCE_IRQ,
387 },
388 };
389
390 struct platform_device msm_device_mdp = {
391 .name = "msm_mdp",
392 .id = 0,
393 .num_resources = ARRAY_SIZE(resources_mdp),
394 .resource = resources_mdp,
395 };
396
397 struct clk_lookup msm_clocks_7x01a[] = {
398 CLK_PCOM("adm_clk", ADM_CLK, NULL, 0),
399 CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0),
400 CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, 0),
401 CLK_PCOM("ebi2_clk", EBI2_CLK, NULL, 0),
402 CLK_PCOM("ecodec_clk", ECODEC_CLK, NULL, 0),
403 CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF),
404 CLK_PCOM("gp_clk", GP_CLK, NULL, 0),
405 CLK_PCOM("grp_clk", GRP_3D_CLK, NULL, OFF),
406 CLK_PCOM("i2c_clk", I2C_CLK, "msm_i2c.0", 0),
407 CLK_PCOM("icodec_rx_clk", ICODEC_RX_CLK, NULL, 0),
408 CLK_PCOM("icodec_tx_clk", ICODEC_TX_CLK, NULL, 0),
409 CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF),
410 CLK_PCOM("mdc_clk", MDC_CLK, NULL, 0),
411 CLK_PCOM("mdp_clk", MDP_CLK, NULL, OFF),
412 CLK_PCOM("pbus_clk", PBUS_CLK, NULL, 0),
413 CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0),
414 CLK_PCOM("mddi_clk", PMDH_CLK, NULL, OFF | CLK_MINMAX),
415 CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF),
416 CLK_PCOM("sdc_clk", SDC1_CLK, "msm_sdcc.1", OFF),
417 CLK_PCOM("sdc_pclk", SDC1_P_CLK, "msm_sdcc.1", OFF),
418 CLK_PCOM("sdc_clk", SDC2_CLK, "msm_sdcc.2", OFF),
419 CLK_PCOM("sdc_pclk", SDC2_P_CLK, "msm_sdcc.2", OFF),
420 CLK_PCOM("sdc_clk", SDC3_CLK, "msm_sdcc.3", OFF),
421 CLK_PCOM("sdc_pclk", SDC3_P_CLK, "msm_sdcc.3", OFF),
422 CLK_PCOM("sdc_clk", SDC4_CLK, "msm_sdcc.4", OFF),
423 CLK_PCOM("sdc_pclk", SDC4_P_CLK, "msm_sdcc.4", OFF),
424 CLK_PCOM("tsif_clk", TSIF_CLK, NULL, 0),
425 CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0),
426 CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0),
427 CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0),
428 CLK_PCOM("uart_clk", UART1_CLK, "msm_serial.0", OFF),
429 CLK_PCOM("uart_clk", UART2_CLK, "msm_serial.1", 0),
430 CLK_PCOM("uart_clk", UART3_CLK, "msm_serial.2", OFF),
431 CLK_PCOM("uart1dm_clk", UART1DM_CLK, NULL, OFF),
432 CLK_PCOM("uart2dm_clk", UART2DM_CLK, NULL, 0),
433 CLK_PCOM("usb_hs_clk", USB_HS_CLK, "msm_hsusb", OFF),
434 CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, "msm_hsusb", OFF),
435 CLK_PCOM("usb_otg_clk", USB_OTG_CLK, NULL, 0),
436 CLK_PCOM("vdc_clk", VDC_CLK, NULL, OFF ),
437 CLK_PCOM("vfe_clk", VFE_CLK, NULL, OFF),
438 CLK_PCOM("vfe_mdc_clk", VFE_MDC_CLK, NULL, OFF),
439 };
440
441 unsigned msm_num_clocks_7x01a = ARRAY_SIZE(msm_clocks_7x01a);