arch/arm/mach-mv78xx0/addr-map.c

   1 /*
   2  * arch/arm/mach-mv78xx0/addr-map.c
   3  *
   4  * Address map functions for Marvell MV78xx0 SoCs
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2.  This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/mbus.h>
  14 #include <linux/io.h>
  15 #include <plat/addr-map.h>
  16 #include "common.h"
  17
  18 /*
  19  * Generic Address Decode Windows bit settings
  20  */
  21 #define TARGET_DEV_BUS          1
  22 #define TARGET_PCIE0            4
  23 #define TARGET_PCIE1            8
  24 #define TARGET_PCIE(i)          ((i) ? TARGET_PCIE1 : TARGET_PCIE0)
  25 #define ATTR_DEV_SPI_ROM        0x1f
  26 #define ATTR_DEV_BOOT           0x2f
  27 #define ATTR_DEV_CS3            0x37
  28 #define ATTR_DEV_CS2            0x3b
  29 #define ATTR_DEV_CS1            0x3d
  30 #define ATTR_DEV_CS0            0x3e
  31 #define ATTR_PCIE_IO(l)         (0xf0 & ~(0x10 << (l)))
  32 #define ATTR_PCIE_MEM(l)        (0xf8 & ~(0x10 << (l)))
  33
  34 /*
  35  * CPU Address Decode Windows registers
  36  */
  37 #define WIN0_OFF(n)             (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
  38 #define WIN8_OFF(n)             (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4))
  39
  40 static void __init __iomem *win_cfg_base(int win)
  41 {
  42         /*
  43          * Find the control register base address for this window.
  44          *
  45          * BRIDGE_VIRT_BASE points to the right (CPU0's or CPU1's)
  46          * MBUS bridge depending on which CPU core we're running on,
  47          * so we don't need to take that into account here.
  48          */
  49
  50         return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win));
  51 }
  52
  53 /*
  54  * Description of the windows needed by the platform code
  55  */
  56 static struct __initdata orion_addr_map_cfg addr_map_cfg = {
  57         .num_wins = 14,
  58         .remappable_wins = 8,
  59         .win_cfg_base = win_cfg_base,
  60 };
  61
  62 void __init mv78xx0_setup_cpu_mbus(void)
  63 {
  64         /*
  65          * Disable, clear and configure windows.
  66          */
  67         orion_config_wins(&addr_map_cfg, NULL);
  68
  69         /*
  70          * Setup MBUS dram target info.
  71          */
  72         if (mv78xx0_core_index() == 0)
  73                 orion_setup_cpu_mbus_target(&addr_map_cfg,
  74                                             DDR_WINDOW_CPU0_BASE);
  75         else
  76                 orion_setup_cpu_mbus_target(&addr_map_cfg,
  77                                             DDR_WINDOW_CPU1_BASE);
  78 }
  79
  80 void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
  81                                       int maj, int min)
  82 {
  83         orion_setup_cpu_win(&addr_map_cfg, window, base, size,
  84                             TARGET_PCIE(maj), ATTR_PCIE_IO(min), -1);
  85 }
  86
  87 void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
  88                                        int maj, int min)
  89 {
  90         orion_setup_cpu_win(&addr_map_cfg, window, base, size,
  91                             TARGET_PCIE(maj), ATTR_PCIE_MEM(min), -1);
  92 }