arch/arm/mach-mv78xx0/common.c

   1 /*
   2  * arch/arm/mach-mv78xx0/common.c
   3  *
   4  * Core functions for Marvell MV78xx0 SoCs
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2.  This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/serial_8250.h>
  15 #include <linux/ata_platform.h>
  16 #include <linux/ethtool.h>
  17 #include <asm/mach/map.h>
  18 #include <asm/mach/time.h>
  19 #include <mach/mv78xx0.h>
  20 #include <mach/bridge-regs.h>
  21 #include <plat/cache-feroceon-l2.h>
  22 #include <plat/ehci-orion.h>
  23 #include <plat/orion_nand.h>
  24 #include <plat/time.h>
  25 #include <plat/common.h>
  26 #include <plat/addr-map.h>
  27 #include "common.h"
  28
  29 static int get_tclk(void);
  30
  31 /*****************************************************************************
  32  * Common bits
  33  ****************************************************************************/
  34 int mv78xx0_core_index(void)
  35 {
  36         u32 extra;
  37
  38         /*
  39          * Read Extra Features register.
  40          */
  41         __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra));
  42
  43         return !!(extra & 0x00004000);
  44 }
  45
  46 static int get_hclk(void)
  47 {
  48         int hclk;
  49
  50         /*
  51          * HCLK tick rate is configured by DEV_D[7:5] pins.
  52          */
  53         switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) {
  54         case 0:
  55                 hclk = 166666667;
  56                 break;
  57         case 1:
  58                 hclk = 200000000;
  59                 break;
  60         case 2:
  61                 hclk = 266666667;
  62                 break;
  63         case 3:
  64                 hclk = 333333333;
  65                 break;
  66         case 4:
  67                 hclk = 400000000;
  68                 break;
  69         default:
  70                 panic("unknown HCLK PLL setting: %.8x\n",
  71                         readl(SAMPLE_AT_RESET_LOW));
  72         }
  73
  74         return hclk;
  75 }
  76
  77 static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk)
  78 {
  79         u32 cfg;
  80
  81         /*
  82          * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1
  83          * PCLK/L2CLK by bits [19:14].
  84          */
  85         if (core_index == 0) {
  86                 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f;
  87         } else {
  88                 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f;
  89         }
  90
  91         /*
  92          * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK
  93          * ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6).
  94          */
  95         *pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1;
  96
  97         /*
  98          * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK
  99          * ratio (1, 2, 3).
 100          */
 101         *l2clk = *pclk / (((cfg >> 4) & 3) + 1);
 102 }
 103
 104 static int get_tclk(void)
 105 {
 106         int tclk;
 107
 108         /*
 109          * TCLK tick rate is configured by DEV_A[2:0] strap pins.
 110          */
 111         switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) {
 112         case 1:
 113                 tclk = 166666667;
 114                 break;
 115         case 3:
 116                 tclk = 200000000;
 117                 break;
 118         default:
 119                 panic("unknown TCLK PLL setting: %.8x\n",
 120                         readl(SAMPLE_AT_RESET_HIGH));
 121         }
 122
 123         return tclk;
 124 }
 125
 126
 127 /*****************************************************************************
 128  * I/O Address Mapping
 129  ****************************************************************************/
 130 static struct map_desc mv78xx0_io_desc[] __initdata = {
 131         {
 132                 .virtual        = MV78XX0_CORE_REGS_VIRT_BASE,
 133                 .pfn            = 0,
 134                 .length         = MV78XX0_CORE_REGS_SIZE,
 135                 .type           = MT_DEVICE,
 136         }, {
 137                 .virtual        = MV78XX0_PCIE_IO_VIRT_BASE(0),
 138                 .pfn            = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)),
 139                 .length         = MV78XX0_PCIE_IO_SIZE * 8,
 140                 .type           = MT_DEVICE,
 141         }, {
 142                 .virtual        = MV78XX0_REGS_VIRT_BASE,
 143                 .pfn            = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
 144                 .length         = MV78XX0_REGS_SIZE,
 145                 .type           = MT_DEVICE,
 146         },
 147 };
 148
 149 void __init mv78xx0_map_io(void)
 150 {
 151         unsigned long phys;
 152
 153         /*
 154          * Map the right set of per-core registers depending on
 155          * which core we are running on.
 156          */
 157         if (mv78xx0_core_index() == 0) {
 158                 phys = MV78XX0_CORE0_REGS_PHYS_BASE;
 159         } else {
 160                 phys = MV78XX0_CORE1_REGS_PHYS_BASE;
 161         }
 162         mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys);
 163
 164         iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc));
 165 }
 166
 167
 168 /*****************************************************************************
 169  * EHCI
 170  ****************************************************************************/
 171 void __init mv78xx0_ehci0_init(void)
 172 {
 173         orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA);
 174 }
 175
 176
 177 /*****************************************************************************
 178  * EHCI1
 179  ****************************************************************************/
 180 void __init mv78xx0_ehci1_init(void)
 181 {
 182         orion_ehci_1_init(USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
 183 }
 184
 185
 186 /*****************************************************************************
 187  * EHCI2
 188  ****************************************************************************/
 189 void __init mv78xx0_ehci2_init(void)
 190 {
 191         orion_ehci_2_init(USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
 192 }
 193
 194
 195 /*****************************************************************************
 196  * GE00
 197  ****************************************************************************/
 198 void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
 199 {
 200         orion_ge00_init(eth_data,
 201                         GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
 202                         IRQ_MV78XX0_GE_ERR, get_tclk());
 203 }
 204
 205
 206 /*****************************************************************************
 207  * GE01
 208  ****************************************************************************/
 209 void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
 210 {
 211         orion_ge01_init(eth_data,
 212                         GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
 213                         NO_IRQ, get_tclk());
 214 }
 215
 216
 217 /*****************************************************************************
 218  * GE10
 219  ****************************************************************************/
 220 void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
 221 {
 222         u32 dev, rev;
 223
 224         /*
 225          * On the Z0, ge10 and ge11 are internally connected back
 226          * to back, and not brought out.
 227          */
 228         mv78xx0_pcie_id(&dev, &rev);
 229         if (dev == MV78X00_Z0_DEV_ID) {
 230                 eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
 231                 eth_data->speed = SPEED_1000;
 232                 eth_data->duplex = DUPLEX_FULL;
 233         }
 234
 235         orion_ge10_init(eth_data,
 236                         GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM,
 237                         NO_IRQ, get_tclk());
 238 }
 239
 240
 241 /*****************************************************************************
 242  * GE11
 243  ****************************************************************************/
 244 void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
 245 {
 246         u32 dev, rev;
 247
 248         /*
 249          * On the Z0, ge10 and ge11 are internally connected back
 250          * to back, and not brought out.
 251          */
 252         mv78xx0_pcie_id(&dev, &rev);
 253         if (dev == MV78X00_Z0_DEV_ID) {
 254                 eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
 255                 eth_data->speed = SPEED_1000;
 256                 eth_data->duplex = DUPLEX_FULL;
 257         }
 258
 259         orion_ge11_init(eth_data,
 260                         GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM,
 261                         NO_IRQ, get_tclk());
 262 }
 263
 264 /*****************************************************************************
 265  * I2C
 266  ****************************************************************************/
 267 void __init mv78xx0_i2c_init(void)
 268 {
 269         orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8);
 270         orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8);
 271 }
 272
 273 /*****************************************************************************
 274  * SATA
 275  ****************************************************************************/
 276 void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
 277 {
 278         orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
 279 }
 280
 281
 282 /*****************************************************************************
 283  * UART0
 284  ****************************************************************************/
 285 void __init mv78xx0_uart0_init(void)
 286 {
 287         orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
 288                          IRQ_MV78XX0_UART_0, get_tclk());
 289 }
 290
 291
 292 /*****************************************************************************
 293  * UART1
 294  ****************************************************************************/
 295 void __init mv78xx0_uart1_init(void)
 296 {
 297         orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
 298                          IRQ_MV78XX0_UART_1, get_tclk());
 299 }
 300
 301
 302 /*****************************************************************************
 303  * UART2
 304  ****************************************************************************/
 305 void __init mv78xx0_uart2_init(void)
 306 {
 307         orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE,
 308                          IRQ_MV78XX0_UART_2, get_tclk());
 309 }
 310
 311 /*****************************************************************************
 312  * UART3
 313  ****************************************************************************/
 314 void __init mv78xx0_uart3_init(void)
 315 {
 316         orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE,
 317                          IRQ_MV78XX0_UART_3, get_tclk());
 318 }
 319
 320 /*****************************************************************************
 321  * Time handling
 322  ****************************************************************************/
 323 void __init mv78xx0_init_early(void)
 324 {
 325         orion_time_set_base(TIMER_VIRT_BASE);
 326 }
 327
 328 static void mv78xx0_timer_init(void)
 329 {
 330         orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
 331                         IRQ_MV78XX0_TIMER_1, get_tclk());
 332 }
 333
 334 struct sys_timer mv78xx0_timer = {
 335         .init = mv78xx0_timer_init,
 336 };
 337
 338
 339 /*****************************************************************************
 340  * General
 341  ****************************************************************************/
 342 static char * __init mv78xx0_id(void)
 343 {
 344         u32 dev, rev;
 345
 346         mv78xx0_pcie_id(&dev, &rev);
 347
 348         if (dev == MV78X00_Z0_DEV_ID) {
 349                 if (rev == MV78X00_REV_Z0)
 350                         return "MV78X00-Z0";
 351                 else
 352                         return "MV78X00-Rev-Unsupported";
 353         } else if (dev == MV78100_DEV_ID) {
 354                 if (rev == MV78100_REV_A0)
 355                         return "MV78100-A0";
 356                 else if (rev == MV78100_REV_A1)
 357                         return "MV78100-A1";
 358                 else
 359                         return "MV78100-Rev-Unsupported";
 360         } else if (dev == MV78200_DEV_ID) {
 361                 if (rev == MV78100_REV_A0)
 362                         return "MV78200-A0";
 363                 else
 364                         return "MV78200-Rev-Unsupported";
 365         } else {
 366                 return "Device-Unknown";
 367         }
 368 }
 369
 370 static int __init is_l2_writethrough(void)
 371 {
 372         return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH);
 373 }
 374
 375 void __init mv78xx0_init(void)
 376 {
 377         int core_index;
 378         int hclk;
 379         int pclk;
 380         int l2clk;
 381         int tclk;
 382
 383         core_index = mv78xx0_core_index();
 384         hclk = get_hclk();
 385         get_pclk_l2clk(hclk, core_index, &pclk, &l2clk);
 386         tclk = get_tclk();
 387
 388         printk(KERN_INFO "%s ", mv78xx0_id());
 389         printk("core #%d, ", core_index);
 390         printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000);
 391         printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000);
 392         printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
 393         printk("TCLK = %dMHz\n", (tclk + 499999) / 1000000);
 394
 395         mv78xx0_setup_cpu_mbus();
 396
 397 #ifdef CONFIG_CACHE_FEROCEON_L2
 398         feroceon_l2_init(is_l2_writethrough());
 399 #endif
 400 }
 401
 402 void mv78xx0_restart(char mode, const char *cmd)
 403 {
 404         /*
 405          * Enable soft reset to assert RSTOUTn.
 406          */
 407         writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
 408
 409         /*
 410          * Assert soft reset.
 411          */
 412         writel(SOFT_RESET, SYSTEM_SOFT_RESET);
 413
 414         while (1)
 415                 ;
 416 }