arch/arm/mach-orion5x/common.c

   1 /*
   2  * arch/arm/mach-orion5x/common.c
   3  *
   4  * Core functions for Marvell Orion 5x SoCs
   5  *
   6  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/serial_8250.h>
  18 #include <linux/mv643xx_i2c.h>
  19 #include <linux/ata_platform.h>
  20 #include <linux/delay.h>
  21 #include <net/dsa.h>
  22 #include <asm/page.h>
  23 #include <asm/setup.h>
  24 #include <asm/timex.h>
  25 #include <asm/mach/arch.h>
  26 #include <asm/mach/map.h>
  27 #include <asm/mach/time.h>
  28 #include <mach/bridge-regs.h>
  29 #include <mach/hardware.h>
  30 #include <mach/orion5x.h>
  31 #include <plat/orion_nand.h>
  32 #include <plat/ehci-orion.h>
  33 #include <plat/time.h>
  34 #include <plat/common.h>
  35 #include <plat/addr-map.h>
  36 #include "common.h"
  37
  38 /*****************************************************************************
  39  * I/O Address Mapping
  40  ****************************************************************************/
  41 static struct map_desc orion5x_io_desc[] __initdata = {
  42         {
  43                 .virtual        = ORION5X_REGS_VIRT_BASE,
  44                 .pfn            = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
  45                 .length         = ORION5X_REGS_SIZE,
  46                 .type           = MT_DEVICE,
  47         }, {
  48                 .virtual        = ORION5X_PCIE_IO_VIRT_BASE,
  49                 .pfn            = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
  50                 .length         = ORION5X_PCIE_IO_SIZE,
  51                 .type           = MT_DEVICE,
  52         }, {
  53                 .virtual        = ORION5X_PCI_IO_VIRT_BASE,
  54                 .pfn            = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
  55                 .length         = ORION5X_PCI_IO_SIZE,
  56                 .type           = MT_DEVICE,
  57         }, {
  58                 .virtual        = ORION5X_PCIE_WA_VIRT_BASE,
  59                 .pfn            = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
  60                 .length         = ORION5X_PCIE_WA_SIZE,
  61                 .type           = MT_DEVICE,
  62         },
  63 };
  64
  65 void __init orion5x_map_io(void)
  66 {
  67         iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
  68 }
  69
  70
  71 /*****************************************************************************
  72  * EHCI0
  73  ****************************************************************************/
  74 void __init orion5x_ehci0_init(void)
  75 {
  76         orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL,
  77                         EHCI_PHY_ORION);
  78 }
  79
  80
  81 /*****************************************************************************
  82  * EHCI1
  83  ****************************************************************************/
  84 void __init orion5x_ehci1_init(void)
  85 {
  86         orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
  87 }
  88
  89
  90 /*****************************************************************************
  91  * GE00
  92  ****************************************************************************/
  93 void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
  94 {
  95         orion_ge00_init(eth_data,
  96                         ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
  97                         IRQ_ORION5X_ETH_ERR, orion5x_tclk);
  98 }
  99
 100
 101 /*****************************************************************************
 102  * Ethernet switch
 103  ****************************************************************************/
 104 void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq)
 105 {
 106         orion_ge00_switch_init(d, irq);
 107 }
 108
 109
 110 /*****************************************************************************
 111  * I2C
 112  ****************************************************************************/
 113 void __init orion5x_i2c_init(void)
 114 {
 115         orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8);
 116
 117 }
 118
 119
 120 /*****************************************************************************
 121  * SATA
 122  ****************************************************************************/
 123 void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
 124 {
 125         orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
 126 }
 127
 128
 129 /*****************************************************************************
 130  * SPI
 131  ****************************************************************************/
 132 void __init orion5x_spi_init()
 133 {
 134         orion_spi_init(SPI_PHYS_BASE, orion5x_tclk);
 135 }
 136
 137
 138 /*****************************************************************************
 139  * UART0
 140  ****************************************************************************/
 141 void __init orion5x_uart0_init(void)
 142 {
 143         orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
 144                          IRQ_ORION5X_UART0, orion5x_tclk);
 145 }
 146
 147 /*****************************************************************************
 148  * UART1
 149  ****************************************************************************/
 150 void __init orion5x_uart1_init(void)
 151 {
 152         orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
 153                          IRQ_ORION5X_UART1, orion5x_tclk);
 154 }
 155
 156 /*****************************************************************************
 157  * XOR engine
 158  ****************************************************************************/
 159 void __init orion5x_xor_init(void)
 160 {
 161         orion_xor0_init(ORION5X_XOR_PHYS_BASE,
 162                         ORION5X_XOR_PHYS_BASE + 0x200,
 163                         IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
 164 }
 165
 166 /*****************************************************************************
 167  * Cryptographic Engines and Security Accelerator (CESA)
 168  ****************************************************************************/
 169 static void __init orion5x_crypto_init(void)
 170 {
 171         orion5x_setup_sram_win();
 172         orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
 173                           SZ_8K, IRQ_ORION5X_CESA);
 174 }
 175
 176 /*****************************************************************************
 177  * Watchdog
 178  ****************************************************************************/
 179 void __init orion5x_wdt_init(void)
 180 {
 181         orion_wdt_init(orion5x_tclk);
 182 }
 183
 184
 185 /*****************************************************************************
 186  * Time handling
 187  ****************************************************************************/
 188 void __init orion5x_init_early(void)
 189 {
 190         orion_time_set_base(TIMER_VIRT_BASE);
 191 }
 192
 193 int orion5x_tclk;
 194
 195 int __init orion5x_find_tclk(void)
 196 {
 197         u32 dev, rev;
 198
 199         orion5x_pcie_id(&dev, &rev);
 200         if (dev == MV88F6183_DEV_ID &&
 201             (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0)
 202                 return 133333333;
 203
 204         return 166666667;
 205 }
 206
 207 static void orion5x_timer_init(void)
 208 {
 209         orion5x_tclk = orion5x_find_tclk();
 210
 211         orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
 212                         IRQ_ORION5X_BRIDGE, orion5x_tclk);
 213 }
 214
 215 struct sys_timer orion5x_timer = {
 216         .init = orion5x_timer_init,
 217 };
 218
 219
 220 /*****************************************************************************
 221  * General
 222  ****************************************************************************/
 223 /*
 224  * Identify device ID and rev from PCIe configuration header space '0'.
 225  */
 226 static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
 227 {
 228         orion5x_pcie_id(dev, rev);
 229
 230         if (*dev == MV88F5281_DEV_ID) {
 231                 if (*rev == MV88F5281_REV_D2) {
 232                         *dev_name = "MV88F5281-D2";
 233                 } else if (*rev == MV88F5281_REV_D1) {
 234                         *dev_name = "MV88F5281-D1";
 235                 } else if (*rev == MV88F5281_REV_D0) {
 236                         *dev_name = "MV88F5281-D0";
 237                 } else {
 238                         *dev_name = "MV88F5281-Rev-Unsupported";
 239                 }
 240         } else if (*dev == MV88F5182_DEV_ID) {
 241                 if (*rev == MV88F5182_REV_A2) {
 242                         *dev_name = "MV88F5182-A2";
 243                 } else {
 244                         *dev_name = "MV88F5182-Rev-Unsupported";
 245                 }
 246         } else if (*dev == MV88F5181_DEV_ID) {
 247                 if (*rev == MV88F5181_REV_B1) {
 248                         *dev_name = "MV88F5181-Rev-B1";
 249                 } else if (*rev == MV88F5181L_REV_A1) {
 250                         *dev_name = "MV88F5181L-Rev-A1";
 251                 } else {
 252                         *dev_name = "MV88F5181(L)-Rev-Unsupported";
 253                 }
 254         } else if (*dev == MV88F6183_DEV_ID) {
 255                 if (*rev == MV88F6183_REV_B0) {
 256                         *dev_name = "MV88F6183-Rev-B0";
 257                 } else {
 258                         *dev_name = "MV88F6183-Rev-Unsupported";
 259                 }
 260         } else {
 261                 *dev_name = "Device-Unknown";
 262         }
 263 }
 264
 265 void __init orion5x_init(void)
 266 {
 267         char *dev_name;
 268         u32 dev, rev;
 269
 270         orion5x_id(&dev, &rev, &dev_name);
 271         printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
 272
 273         /*
 274          * Setup Orion address map
 275          */
 276         orion5x_setup_cpu_mbus_bridge();
 277
 278         /*
 279          * Don't issue "Wait for Interrupt" instruction if we are
 280          * running on D0 5281 silicon.
 281          */
 282         if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
 283                 printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
 284                 disable_hlt();
 285         }
 286
 287         /*
 288          * The 5082/5181l/5182/6082/6082l/6183 have crypto
 289          * while 5180n/5181/5281 don't have crypto.
 290          */
 291         if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) ||
 292             dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID)
 293                 orion5x_crypto_init();
 294
 295         /*
 296          * Register watchdog driver
 297          */
 298         orion5x_wdt_init();
 299 }
 300
 301 void orion5x_restart(char mode, const char *cmd)
 302 {
 303         /*
 304          * Enable and issue soft reset
 305          */
 306         orion5x_setbits(RSTOUTn_MASK, (1 << 2));
 307         orion5x_setbits(CPU_SOFT_RESET, 1);
 308         mdelay(200);
 309         orion5x_clrbits(CPU_SOFT_RESET, 1);
 310 }
 311
 312 /*
 313  * Many orion-based systems have buggy bootloader implementations.
 314  * This is a common fixup for bogus memory tags.
 315  */
 316 void __init tag_fixup_mem32(struct tag *t, char **from,
 317                             struct meminfo *meminfo)
 318 {
 319         for (; t->hdr.size; t = tag_next(t))
 320                 if (t->hdr.tag == ATAG_MEM &&
 321                     (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK ||
 322                      t->u.mem.start & ~PAGE_MASK)) {
 323                         printk(KERN_WARNING
 324                                "Clearing invalid memory bank %dKB@0x%08x\n",
 325                                t->u.mem.size / 1024, t->u.mem.start);
 326                         t->hdr.tag = 0;
 327                 }
 328 }