arch/arm/mach-s3c2443/clock.c

   1 /* linux/arch/arm/mach-s3c2443/clock.c
   2  *
   3  * Copyright (c) 2007, 2010 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2443 Clock control support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21 */
  22
  23 #include <linux/init.h>
  24
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/list.h>
  28 #include <linux/errno.h>
  29 #include <linux/err.h>
  30 #include <linux/device.h>
  31 #include <linux/clk.h>
  32 #include <linux/mutex.h>
  33 #include <linux/serial_core.h>
  34 #include <linux/io.h>
  35
  36 #include <asm/mach/map.h>
  37
  38 #include <mach/hardware.h>
  39
  40 #include <mach/regs-s3c2443-clock.h>
  41
  42 #include <plat/cpu-freq.h>
  43
  44 #include <plat/s3c2443.h>
  45 #include <plat/clock.h>
  46 #include <plat/clock-clksrc.h>
  47 #include <plat/cpu.h>
  48
  49 /* We currently have to assume that the system is running
  50  * from the XTPll input, and that all ***REFCLKs are being
  51  * fed from it, as we cannot read the state of OM[4] from
  52  * software.
  53  *
  54  * It would be possible for each board initialisation to
  55  * set the correct muxing at initialisation
  56 */
  57
  58 /* clock selections */
  59
  60 /* armdiv
  61  *
  62  * this clock is sourced from msysclk and can have a number of
  63  * divider values applied to it to then be fed into armclk.
  64  * The real clock definition is done in s3c2443-clock.c,
  65  * only the armdiv divisor table must be defined here.
  66 */
  67
  68 static unsigned int armdiv[16] = {
  69         [S3C2443_CLKDIV0_ARMDIV_1 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]      = 1,
  70         [S3C2443_CLKDIV0_ARMDIV_2 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]      = 2,
  71         [S3C2443_CLKDIV0_ARMDIV_3 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]      = 3,
  72         [S3C2443_CLKDIV0_ARMDIV_4 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]      = 4,
  73         [S3C2443_CLKDIV0_ARMDIV_6 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]      = 6,
  74         [S3C2443_CLKDIV0_ARMDIV_8 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]      = 8,
  75         [S3C2443_CLKDIV0_ARMDIV_12 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]     = 12,
  76         [S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]     = 16,
  77 };
  78
  79 /* hsspi
  80  *
  81  * high-speed spi clock, sourced from esysclk
  82 */
  83
  84 static struct clksrc_clk clk_hsspi = {
  85         .clk    = {
  86                 .name           = "hsspi-if",
  87                 .parent         = &clk_esysclk.clk,
  88                 .ctrlbit        = S3C2443_SCLKCON_HSSPICLK,
  89                 .enable         = s3c2443_clkcon_enable_s,
  90         },
  91         .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
  92 };
  93
  94
  95 /* clk_hsmcc_div
  96  *
  97  * this clock is sourced from epll, and is fed through a divider,
  98  * to a mux controlled by sclkcon where either it or a extclk can
  99  * be fed to the hsmmc block
 100 */
 101
 102 static struct clksrc_clk clk_hsmmc_div = {
 103         .clk    = {
 104                 .name           = "hsmmc-div",
 105                 .devname        = "s3c-sdhci.1",
 106                 .parent         = &clk_esysclk.clk,
 107         },
 108         .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
 109 };
 110
 111 static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent)
 112 {
 113         unsigned long clksrc = __raw_readl(S3C2443_SCLKCON);
 114
 115         clksrc &= ~(S3C2443_SCLKCON_HSMMCCLK_EXT |
 116                     S3C2443_SCLKCON_HSMMCCLK_EPLL);
 117
 118         if (parent == &clk_epll)
 119                 clksrc |= S3C2443_SCLKCON_HSMMCCLK_EPLL;
 120         else if (parent == &clk_ext)
 121                 clksrc |= S3C2443_SCLKCON_HSMMCCLK_EXT;
 122         else
 123                 return -EINVAL;
 124
 125         if (clk->usage > 0) {
 126                 __raw_writel(clksrc, S3C2443_SCLKCON);
 127         }
 128
 129         clk->parent = parent;
 130         return 0;
 131 }
 132
 133 static int s3c2443_enable_hsmmc(struct clk *clk, int enable)
 134 {
 135         return s3c2443_setparent_hsmmc(clk, clk->parent);
 136 }
 137
 138 static struct clk clk_hsmmc = {
 139         .name           = "hsmmc-if",
 140         .devname        = "s3c-sdhci.1",
 141         .parent         = &clk_hsmmc_div.clk,
 142         .enable         = s3c2443_enable_hsmmc,
 143         .ops            = &(struct clk_ops) {
 144                 .set_parent     = s3c2443_setparent_hsmmc,
 145         },
 146 };
 147
 148 /* standard clock definitions */
 149
 150 static struct clk init_clocks_off[] = {
 151         {
 152                 .name           = "sdi",
 153                 .parent         = &clk_p,
 154                 .enable         = s3c2443_clkcon_enable_p,
 155                 .ctrlbit        = S3C2443_PCLKCON_SDI,
 156         }, {
 157                 .name           = "spi",
 158                 .devname        = "s3c2410-spi.0",
 159                 .parent         = &clk_p,
 160                 .enable         = s3c2443_clkcon_enable_p,
 161                 .ctrlbit        = S3C2443_PCLKCON_SPI0,
 162         }, {
 163                 .name           = "spi",
 164                 .devname        = "s3c2410-spi.1",
 165                 .parent         = &clk_p,
 166                 .enable         = s3c2443_clkcon_enable_p,
 167                 .ctrlbit        = S3C2443_PCLKCON_SPI1,
 168         }
 169 };
 170
 171 /* clocks to add straight away */
 172
 173 static struct clksrc_clk *clksrcs[] __initdata = {
 174         &clk_hsspi,
 175         &clk_hsmmc_div,
 176 };
 177
 178 static struct clk *clks[] __initdata = {
 179         &clk_hsmmc,
 180 };
 181
 182 void __init_or_cpufreq s3c2443_setup_clocks(void)
 183 {
 184         s3c2443_common_setup_clocks(s3c2443_get_mpll);
 185 }
 186
 187 void __init s3c2443_init_clocks(int xtal)
 188 {
 189         unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
 190         int ptr;
 191
 192         clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
 193         clk_epll.parent = &clk_epllref.clk;
 194
 195         s3c2443_common_init_clocks(xtal, s3c2443_get_mpll,
 196                                    armdiv, ARRAY_SIZE(armdiv),
 197                                    S3C2443_CLKDIV0_ARMDIV_MASK);
 198
 199         s3c2443_setup_clocks();
 200
 201         s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
 202
 203         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
 204                 s3c_register_clksrc(clksrcs[ptr], 1);
 205
 206         /* We must be careful disabling the clocks we are not intending to
 207          * be using at boot time, as subsystems such as the LCD which do
 208          * their own DMA requests to the bus can cause the system to lockup
 209          * if they where in the middle of requesting bus access.
 210          *
 211          * Disabling the LCD clock if the LCD is active is very dangerous,
 212          * and therefore the bootloader should be careful to not enable
 213          * the LCD clock if it is not needed.
 214         */
 215
 216         /* install (and disable) the clocks we do not need immediately */
 217
 218         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 219         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 220
 221         s3c_pwmclk_init();
 222 }