arch/arm/mach-sa1100/cpu-sa1100.c

   1 /*
   2  * cpu-sa1100.c: clock scaling for the SA1100
   3  *
   4  * Copyright (C) 2000 2001, The Delft University of Technology
   5  *
   6  * Authors:
   7  * - Johan Pouwelse (J.A.Pouwelse@its.tudelft.nl): initial version
   8  * - Erik Mouw (J.A.K.Mouw@its.tudelft.nl):
   9  *   - major rewrite for linux-2.3.99
  10  *   - rewritten for the more generic power management scheme in
  11  *     linux-2.4.5-rmk1
  12  *
  13  * This software has been developed while working on the LART
  14  * computing board (http://www.lartmaker.nl/), which is
  15  * sponsored by the Mobile Multi-media Communications
  16  * (http://www.mobimedia.org/) and Ubiquitous Communications
  17  * (http://www.ubicom.tudelft.nl/) projects.
  18  *
  19  * The authors can be reached at:
  20  *
  21  *  Erik Mouw
  22  *  Information and Communication Theory Group
  23  *  Faculty of Information Technology and Systems
  24  *  Delft University of Technology
  25  *  P.O. Box 5031
  26  *  2600 GA Delft
  27  *  The Netherlands
  28  *
  29  *
  30  * This program is free software; you can redistribute it and/or modify
  31  * it under the terms of the GNU General Public License as published by
  32  * the Free Software Foundation; either version 2 of the License, or
  33  * (at your option) any later version.
  34  *
  35  * This program is distributed in the hope that it will be useful,
  36  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  37  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  38  * GNU General Public License for more details.
  39  *
  40  * You should have received a copy of the GNU General Public License
  41  * along with this program; if not, write to the Free Software
  42  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  43  *
  44  *
  45  * Theory of operations
  46  * ====================
  47  *
  48  * Clock scaling can be used to lower the power consumption of the CPU
  49  * core. This will give you a somewhat longer running time.
  50  *
  51  * The SA-1100 has a single register to change the core clock speed:
  52  *
  53  *   PPCR      0x90020014    PLL config
  54  *
  55  * However, the DRAM timings are closely related to the core clock
  56  * speed, so we need to change these, too. The used registers are:
  57  *
  58  *   MDCNFG    0xA0000000    DRAM config
  59  *   MDCAS0    0xA0000004    Access waveform
  60  *   MDCAS1    0xA0000008    Access waveform
  61  *   MDCAS2    0xA000000C    Access waveform
  62  *
  63  * Care must be taken to change the DRAM parameters the correct way,
  64  * because otherwise the DRAM becomes unusable and the kernel will
  65  * crash.
  66  *
  67  * The simple solution to avoid a kernel crash is to put the actual
  68  * clock change in ROM and jump to that code from the kernel. The main
  69  * disadvantage is that the ROM has to be modified, which is not
  70  * possible on all SA-1100 platforms. Another disadvantage is that
  71  * jumping to ROM makes clock switching unnecessary complicated.
  72  *
  73  * The idea behind this driver is that the memory configuration can be
  74  * changed while running from DRAM (even with interrupts turned on!)
  75  * as long as all re-configuration steps yield a valid DRAM
  76  * configuration. The advantages are clear: it will run on all SA-1100
  77  * platforms, and the code is very simple.
  78  *
  79  * If you really want to understand what is going on in
  80  * sa1100_update_dram_timings(), you'll have to read sections 8.2,
  81  * 9.5.7.3, and 10.2 from the "Intel StrongARM SA-1100 Microprocessor
  82  * Developers Manual" (available for free from Intel).
  83  *
  84  */
  85
  86 #include <linux/kernel.h>
  87 #include <linux/types.h>
  88 #include <linux/init.h>
  89 #include <linux/cpufreq.h>
  90
  91 #include <asm/cputype.h>
  92
  93 #include <mach/hardware.h>
  94
  95 #include "generic.h"
  96
  97 struct sa1100_dram_regs {
  98         int speed;
  99         u32 mdcnfg;
 100         u32 mdcas0;
 101         u32 mdcas1;
 102         u32 mdcas2;
 103 };
 104
 105
 106 static struct cpufreq_driver sa1100_driver;
 107
 108 static struct sa1100_dram_regs sa1100_dram_settings[] = {
 109         /*speed,     mdcnfg,     mdcas0,     mdcas1,     mdcas2,   clock freq */
 110         { 59000, 0x00dc88a3, 0xcccccccf, 0xfffffffc, 0xffffffff},/*  59.0 MHz */
 111         { 73700, 0x011490a3, 0xcccccccf, 0xfffffffc, 0xffffffff},/*  73.7 MHz */
 112         { 88500, 0x014e90a3, 0xcccccccf, 0xfffffffc, 0xffffffff},/*  88.5 MHz */
 113         {103200, 0x01889923, 0xcccccccf, 0xfffffffc, 0xffffffff},/* 103.2 MHz */
 114         {118000, 0x01c29923, 0x9999998f, 0xfffffff9, 0xffffffff},/* 118.0 MHz */
 115         {132700, 0x01fb2123, 0x9999998f, 0xfffffff9, 0xffffffff},/* 132.7 MHz */
 116         {147500, 0x02352123, 0x3333330f, 0xfffffff3, 0xffffffff},/* 147.5 MHz */
 117         {162200, 0x026b29a3, 0x38e38e1f, 0xfff8e38e, 0xffffffff},/* 162.2 MHz */
 118         {176900, 0x02a329a3, 0x71c71c1f, 0xfff1c71c, 0xffffffff},/* 176.9 MHz */
 119         {191700, 0x02dd31a3, 0xe38e383f, 0xffe38e38, 0xffffffff},/* 191.7 MHz */
 120         {206400, 0x03153223, 0xc71c703f, 0xffc71c71, 0xffffffff},/* 206.4 MHz */
 121         {221200, 0x034fba23, 0xc71c703f, 0xffc71c71, 0xffffffff},/* 221.2 MHz */
 122         {235900, 0x03853a23, 0xe1e1e07f, 0xe1e1e1e1, 0xffffffe1},/* 235.9 MHz */
 123         {250700, 0x03bf3aa3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3},/* 250.7 MHz */
 124         {265400, 0x03f7c2a3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3},/* 265.4 MHz */
 125         {280200, 0x0431c2a3, 0x878780ff, 0x87878787, 0xffffff87},/* 280.2 MHz */
 126         { 0, 0, 0, 0, 0 } /* last entry */
 127 };
 128
 129 static void sa1100_update_dram_timings(int current_speed, int new_speed)
 130 {
 131         struct sa1100_dram_regs *settings = sa1100_dram_settings;
 132
 133         /* find speed */
 134         while (settings->speed != 0) {
 135                 if (new_speed == settings->speed)
 136                         break;
 137
 138                 settings++;
 139         }
 140
 141         if (settings->speed == 0) {
 142                 panic("%s: couldn't find dram setting for speed %d\n",
 143                       __func__, new_speed);
 144         }
 145
 146         /* No risk, no fun: run with interrupts on! */
 147         if (new_speed > current_speed) {
 148                 /* We're going FASTER, so first relax the memory
 149                  * timings before changing the core frequency
 150                  */
 151
 152                 /* Half the memory access clock */
 153                 MDCNFG |= MDCNFG_CDB2;
 154
 155                 /* The order of these statements IS important, keep 8
 156                  * pulses!!
 157                  */
 158                 MDCAS2 = settings->mdcas2;
 159                 MDCAS1 = settings->mdcas1;
 160                 MDCAS0 = settings->mdcas0;
 161                 MDCNFG = settings->mdcnfg;
 162         } else {
 163                 /* We're going SLOWER: first decrease the core
 164                  * frequency and then tighten the memory settings.
 165                  */
 166
 167                 /* Half the memory access clock */
 168                 MDCNFG |= MDCNFG_CDB2;
 169
 170                 /* The order of these statements IS important, keep 8
 171                  * pulses!!
 172                  */
 173                 MDCAS0 = settings->mdcas0;
 174                 MDCAS1 = settings->mdcas1;
 175                 MDCAS2 = settings->mdcas2;
 176                 MDCNFG = settings->mdcnfg;
 177         }
 178 }
 179
 180 static int sa1100_target(struct cpufreq_policy *policy,
 181                          unsigned int target_freq,
 182                          unsigned int relation)
 183 {
 184         unsigned int cur = sa11x0_getspeed(0);
 185         unsigned int new_ppcr;
 186         struct cpufreq_freqs freqs;
 187
 188         new_ppcr = sa11x0_freq_to_ppcr(target_freq);
 189         switch (relation) {
 190         case CPUFREQ_RELATION_L:
 191                 if (sa11x0_ppcr_to_freq(new_ppcr) > policy->max)
 192                         new_ppcr--;
 193                 break;
 194         case CPUFREQ_RELATION_H:
 195                 if ((sa11x0_ppcr_to_freq(new_ppcr) > target_freq) &&
 196                     (sa11x0_ppcr_to_freq(new_ppcr - 1) >= policy->min))
 197                         new_ppcr--;
 198                 break;
 199         }
 200
 201         freqs.old = cur;
 202         freqs.new = sa11x0_ppcr_to_freq(new_ppcr);
 203         freqs.cpu = 0;
 204
 205         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 206
 207         if (freqs.new > cur)
 208                 sa1100_update_dram_timings(cur, freqs.new);
 209
 210         PPCR = new_ppcr;
 211
 212         if (freqs.new < cur)
 213                 sa1100_update_dram_timings(cur, freqs.new);
 214
 215         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 216
 217         return 0;
 218 }
 219
 220 static int __init sa1100_cpu_init(struct cpufreq_policy *policy)
 221 {
 222         if (policy->cpu != 0)
 223                 return -EINVAL;
 224         policy->cur = policy->min = policy->max = sa11x0_getspeed(0);
 225         policy->cpuinfo.min_freq = 59000;
 226         policy->cpuinfo.max_freq = 287000;
 227         policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
 228         return 0;
 229 }
 230
 231 static struct cpufreq_driver sa1100_driver __refdata = {
 232         .flags          = CPUFREQ_STICKY,
 233         .verify         = sa11x0_verify_speed,
 234         .target         = sa1100_target,
 235         .get            = sa11x0_getspeed,
 236         .init           = sa1100_cpu_init,
 237         .name           = "sa1100",
 238 };
 239
 240 static int __init sa1100_dram_init(void)
 241 {
 242         if (cpu_is_sa1100())
 243                 return cpufreq_register_driver(&sa1100_driver);
 244         else
 245                 return -ENODEV;
 246 }
 247
 248 arch_initcall(sa1100_dram_init);