arch/arm/mach-tegra/include/mach/pinmux.h

   1 /*
   2  * linux/arch/arm/mach-tegra/include/mach/pinmux.h
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Copyright (C) 2010,2011 Nvidia, Inc.
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #ifndef __MACH_TEGRA_PINMUX_H
  19 #define __MACH_TEGRA_PINMUX_H
  20
  21 enum tegra_mux_func {
  22         TEGRA_MUX_RSVD = 0x8000,
  23         TEGRA_MUX_RSVD1 = 0x8000,
  24         TEGRA_MUX_RSVD2 = 0x8001,
  25         TEGRA_MUX_RSVD3 = 0x8002,
  26         TEGRA_MUX_RSVD4 = 0x8003,
  27         TEGRA_MUX_INVALID = 0x4000,
  28         TEGRA_MUX_NONE = -1,
  29         TEGRA_MUX_AHB_CLK,
  30         TEGRA_MUX_APB_CLK,
  31         TEGRA_MUX_AUDIO_SYNC,
  32         TEGRA_MUX_CRT,
  33         TEGRA_MUX_DAP1,
  34         TEGRA_MUX_DAP2,
  35         TEGRA_MUX_DAP3,
  36         TEGRA_MUX_DAP4,
  37         TEGRA_MUX_DAP5,
  38         TEGRA_MUX_DISPLAYA,
  39         TEGRA_MUX_DISPLAYB,
  40         TEGRA_MUX_EMC_TEST0_DLL,
  41         TEGRA_MUX_EMC_TEST1_DLL,
  42         TEGRA_MUX_GMI,
  43         TEGRA_MUX_GMI_INT,
  44         TEGRA_MUX_HDMI,
  45         TEGRA_MUX_I2C,
  46         TEGRA_MUX_I2C2,
  47         TEGRA_MUX_I2C3,
  48         TEGRA_MUX_IDE,
  49         TEGRA_MUX_IRDA,
  50         TEGRA_MUX_KBC,
  51         TEGRA_MUX_MIO,
  52         TEGRA_MUX_MIPI_HS,
  53         TEGRA_MUX_NAND,
  54         TEGRA_MUX_OSC,
  55         TEGRA_MUX_OWR,
  56         TEGRA_MUX_PCIE,
  57         TEGRA_MUX_PLLA_OUT,
  58         TEGRA_MUX_PLLC_OUT1,
  59         TEGRA_MUX_PLLM_OUT1,
  60         TEGRA_MUX_PLLP_OUT2,
  61         TEGRA_MUX_PLLP_OUT3,
  62         TEGRA_MUX_PLLP_OUT4,
  63         TEGRA_MUX_PWM,
  64         TEGRA_MUX_PWR_INTR,
  65         TEGRA_MUX_PWR_ON,
  66         TEGRA_MUX_RTCK,
  67         TEGRA_MUX_SDIO1,
  68         TEGRA_MUX_SDIO2,
  69         TEGRA_MUX_SDIO3,
  70         TEGRA_MUX_SDIO4,
  71         TEGRA_MUX_SFLASH,
  72         TEGRA_MUX_SPDIF,
  73         TEGRA_MUX_SPI1,
  74         TEGRA_MUX_SPI2,
  75         TEGRA_MUX_SPI2_ALT,
  76         TEGRA_MUX_SPI3,
  77         TEGRA_MUX_SPI4,
  78         TEGRA_MUX_TRACE,
  79         TEGRA_MUX_TWC,
  80         TEGRA_MUX_UARTA,
  81         TEGRA_MUX_UARTB,
  82         TEGRA_MUX_UARTC,
  83         TEGRA_MUX_UARTD,
  84         TEGRA_MUX_UARTE,
  85         TEGRA_MUX_ULPI,
  86         TEGRA_MUX_VI,
  87         TEGRA_MUX_VI_SENSOR_CLK,
  88         TEGRA_MUX_XIO,
  89         TEGRA_MUX_BLINK,
  90         TEGRA_MUX_CEC,
  91         TEGRA_MUX_CLK12,
  92         TEGRA_MUX_DAP,
  93         TEGRA_MUX_DAPSDMMC2,
  94         TEGRA_MUX_DDR,
  95         TEGRA_MUX_DEV3,
  96         TEGRA_MUX_DTV,
  97         TEGRA_MUX_VI_ALT1,
  98         TEGRA_MUX_VI_ALT2,
  99         TEGRA_MUX_VI_ALT3,
 100         TEGRA_MUX_EMC_DLL,
 101         TEGRA_MUX_EXTPERIPH1,
 102         TEGRA_MUX_EXTPERIPH2,
 103         TEGRA_MUX_EXTPERIPH3,
 104         TEGRA_MUX_GMI_ALT,
 105         TEGRA_MUX_HDA,
 106         TEGRA_MUX_HSI,
 107         TEGRA_MUX_I2C4,
 108         TEGRA_MUX_I2C5,
 109         TEGRA_MUX_I2CPWR,
 110         TEGRA_MUX_I2S0,
 111         TEGRA_MUX_I2S1,
 112         TEGRA_MUX_I2S2,
 113         TEGRA_MUX_I2S3,
 114         TEGRA_MUX_I2S4,
 115         TEGRA_MUX_NAND_ALT,
 116         TEGRA_MUX_POPSDIO4,
 117         TEGRA_MUX_POPSDMMC4,
 118         TEGRA_MUX_PWM0,
 119         TEGRA_MUX_PWM1,
 120         TEGRA_MUX_PWM2,
 121         TEGRA_MUX_PWM3,
 122         TEGRA_MUX_SATA,
 123         TEGRA_MUX_SPI5,
 124         TEGRA_MUX_SPI6,
 125         TEGRA_MUX_SYSCLK,
 126         TEGRA_MUX_VGP1,
 127         TEGRA_MUX_VGP2,
 128         TEGRA_MUX_VGP3,
 129         TEGRA_MUX_VGP4,
 130         TEGRA_MUX_VGP5,
 131         TEGRA_MUX_VGP6,
 132         TEGRA_MUX_SAFE,
 133         TEGRA_MAX_MUX,
 134 };
 135
 136 enum tegra_pullupdown {
 137         TEGRA_PUPD_NORMAL = 0,
 138         TEGRA_PUPD_PULL_DOWN,
 139         TEGRA_PUPD_PULL_UP,
 140 };
 141
 142 enum tegra_tristate {
 143         TEGRA_TRI_NORMAL = 0,
 144         TEGRA_TRI_TRISTATE = 1,
 145 };
 146
 147 enum tegra_pin_io {
 148         TEGRA_PIN_OUTPUT = 0,
 149         TEGRA_PIN_INPUT = 1,
 150 };
 151
 152 enum tegra_vddio {
 153         TEGRA_VDDIO_BB = 0,
 154         TEGRA_VDDIO_LCD,
 155         TEGRA_VDDIO_VI,
 156         TEGRA_VDDIO_UART,
 157         TEGRA_VDDIO_DDR,
 158         TEGRA_VDDIO_NAND,
 159         TEGRA_VDDIO_SYS,
 160         TEGRA_VDDIO_AUDIO,
 161         TEGRA_VDDIO_SD,
 162         TEGRA_VDDIO_CAM,
 163         TEGRA_VDDIO_GMI,
 164         TEGRA_VDDIO_PEXCTL,
 165         TEGRA_VDDIO_SDMMC1,
 166         TEGRA_VDDIO_SDMMC3,
 167         TEGRA_VDDIO_SDMMC4,
 168 };
 169
 170 struct tegra_pingroup_config {
 171         int pingroup;
 172         enum tegra_mux_func     func;
 173         enum tegra_pullupdown   pupd;
 174         enum tegra_tristate     tristate;
 175 };
 176
 177 enum tegra_slew {
 178         TEGRA_SLEW_FASTEST = 0,
 179         TEGRA_SLEW_FAST,
 180         TEGRA_SLEW_SLOW,
 181         TEGRA_SLEW_SLOWEST,
 182         TEGRA_MAX_SLEW,
 183 };
 184
 185 enum tegra_pull_strength {
 186         TEGRA_PULL_0 = 0,
 187         TEGRA_PULL_1,
 188         TEGRA_PULL_2,
 189         TEGRA_PULL_3,
 190         TEGRA_PULL_4,
 191         TEGRA_PULL_5,
 192         TEGRA_PULL_6,
 193         TEGRA_PULL_7,
 194         TEGRA_PULL_8,
 195         TEGRA_PULL_9,
 196         TEGRA_PULL_10,
 197         TEGRA_PULL_11,
 198         TEGRA_PULL_12,
 199         TEGRA_PULL_13,
 200         TEGRA_PULL_14,
 201         TEGRA_PULL_15,
 202         TEGRA_PULL_16,
 203         TEGRA_PULL_17,
 204         TEGRA_PULL_18,
 205         TEGRA_PULL_19,
 206         TEGRA_PULL_20,
 207         TEGRA_PULL_21,
 208         TEGRA_PULL_22,
 209         TEGRA_PULL_23,
 210         TEGRA_PULL_24,
 211         TEGRA_PULL_25,
 212         TEGRA_PULL_26,
 213         TEGRA_PULL_27,
 214         TEGRA_PULL_28,
 215         TEGRA_PULL_29,
 216         TEGRA_PULL_30,
 217         TEGRA_PULL_31,
 218         TEGRA_MAX_PULL,
 219 };
 220
 221 enum tegra_drive {
 222         TEGRA_DRIVE_DIV_8 = 0,
 223         TEGRA_DRIVE_DIV_4,
 224         TEGRA_DRIVE_DIV_2,
 225         TEGRA_DRIVE_DIV_1,
 226         TEGRA_MAX_DRIVE,
 227 };
 228
 229 enum tegra_hsm {
 230         TEGRA_HSM_DISABLE = 0,
 231         TEGRA_HSM_ENABLE,
 232 };
 233
 234 enum tegra_schmitt {
 235         TEGRA_SCHMITT_DISABLE = 0,
 236         TEGRA_SCHMITT_ENABLE,
 237 };
 238
 239 struct tegra_drive_pingroup_config {
 240         int pingroup;
 241         enum tegra_hsm hsm;
 242         enum tegra_schmitt schmitt;
 243         enum tegra_drive drive;
 244         enum tegra_pull_strength pull_down;
 245         enum tegra_pull_strength pull_up;
 246         enum tegra_slew slew_rising;
 247         enum tegra_slew slew_falling;
 248 };
 249
 250 struct tegra_drive_pingroup_desc {
 251         const char *name;
 252         s16 reg_bank;
 253         s16 reg;
 254 };
 255
 256 struct tegra_pingroup_desc {
 257         const char *name;
 258         int funcs[4];
 259         int func_safe;
 260         int vddio;
 261         enum tegra_pin_io io_default;
 262         s16 tri_bank;   /* Register bank the tri_reg exists within */
 263         s16 mux_bank;   /* Register bank the mux_reg exists within */
 264         s16 pupd_bank;  /* Register bank the pupd_reg exists within */
 265         s16 tri_reg;    /* offset into the TRISTATE_REG_* register bank */
 266         s16 mux_reg;    /* offset into the PIN_MUX_CTL_* register bank */
 267         s16 pupd_reg;   /* offset into the PULL_UPDOWN_REG_* register bank */
 268         s8 tri_bit;     /* offset into the TRISTATE_REG_* register bit */
 269         s8 mux_bit;     /* offset into the PIN_MUX_CTL_* register bit */
 270         s8 pupd_bit;    /* offset into the PULL_UPDOWN_REG_* register bit */
 271         s8 lock_bit;    /* offset of the LOCK bit into mux register bit */
 272         s8 od_bit;      /* offset of the OD bit into mux register bit */
 273         s8 ioreset_bit; /* offset of the IO_RESET bit into mux register bit */
 274 };
 275
 276 typedef void (*pinmux_init) (const struct tegra_pingroup_desc **pg,
 277         int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
 278         int *pgdrive_max);
 279
 280 void tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
 281         const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
 282
 283 void tegra30_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
 284         const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
 285
 286 int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate);
 287 int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd);
 288
 289 void tegra_pinmux_config_table(const struct tegra_pingroup_config *config,
 290         int len);
 291
 292 void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
 293         int len);
 294 void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
 295         int len);
 296 void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
 297         int len);
 298 void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
 299         int len, enum tegra_tristate tristate);
 300 void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
 301         int len, enum tegra_pullupdown pupd);
 302 #endif