arch/arm/mach-w90x900/cpu.c

   1 /*
   2  * linux/arch/arm/mach-w90x900/cpu.c
   3  *
   4  * Copyright (c) 2009 Nuvoton corporation.
   5  *
   6  * Wan ZongShun <mcuos.com@gmail.com>
   7  *
   8  * NUC900 series cpu common support
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation;version 2 of the License.
  13  *
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/types.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/list.h>
  20 #include <linux/timer.h>
  21 #include <linux/init.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/io.h>
  24 #include <linux/serial_8250.h>
  25 #include <linux/delay.h>
  26
  27 #include <asm/mach/arch.h>
  28 #include <asm/mach/map.h>
  29 #include <asm/mach/irq.h>
  30 #include <asm/irq.h>
  31
  32 #include <mach/hardware.h>
  33 #include <mach/regs-serial.h>
  34 #include <mach/regs-clock.h>
  35 #include <mach/regs-ebi.h>
  36 #include <mach/regs-timer.h>
  37
  38 #include "cpu.h"
  39 #include "clock.h"
  40 #include "nuc9xx.h"
  41
  42 /* Initial IO mappings */
  43
  44 static struct map_desc nuc900_iodesc[] __initdata = {
  45         IODESC_ENT(IRQ),
  46         IODESC_ENT(GCR),
  47         IODESC_ENT(UART),
  48         IODESC_ENT(TIMER),
  49         IODESC_ENT(EBI),
  50         IODESC_ENT(GPIO),
  51 };
  52
  53 /* Initial clock declarations. */
  54 static DEFINE_CLK(lcd, 0);
  55 static DEFINE_CLK(audio, 1);
  56 static DEFINE_CLK(fmi, 4);
  57 static DEFINE_SUBCLK(ms, 0);
  58 static DEFINE_SUBCLK(sd, 1);
  59 static DEFINE_CLK(dmac, 5);
  60 static DEFINE_CLK(atapi, 6);
  61 static DEFINE_CLK(emc, 7);
  62 static DEFINE_SUBCLK(rmii, 2);
  63 static DEFINE_CLK(usbd, 8);
  64 static DEFINE_CLK(usbh, 9);
  65 static DEFINE_CLK(g2d, 10);
  66 static DEFINE_CLK(pwm, 18);
  67 static DEFINE_CLK(ps2, 24);
  68 static DEFINE_CLK(kpi, 25);
  69 static DEFINE_CLK(wdt, 26);
  70 static DEFINE_CLK(gdma, 27);
  71 static DEFINE_CLK(adc, 28);
  72 static DEFINE_CLK(usi, 29);
  73 static DEFINE_CLK(ext, 0);
  74 static DEFINE_CLK(timer0, 19);
  75 static DEFINE_CLK(timer1, 20);
  76 static DEFINE_CLK(timer2, 21);
  77 static DEFINE_CLK(timer3, 22);
  78 static DEFINE_CLK(timer4, 23);
  79
  80 static struct clk_lookup nuc900_clkregs[] = {
  81         DEF_CLKLOOK(&clk_lcd, "nuc900-lcd", NULL),
  82         DEF_CLKLOOK(&clk_audio, "nuc900-ac97", NULL),
  83         DEF_CLKLOOK(&clk_fmi, "nuc900-fmi", NULL),
  84         DEF_CLKLOOK(&clk_ms, "nuc900-fmi", "MS"),
  85         DEF_CLKLOOK(&clk_sd, "nuc900-fmi", "SD"),
  86         DEF_CLKLOOK(&clk_dmac, "nuc900-dmac", NULL),
  87         DEF_CLKLOOK(&clk_atapi, "nuc900-atapi", NULL),
  88         DEF_CLKLOOK(&clk_emc, "nuc900-emc", NULL),
  89         DEF_CLKLOOK(&clk_rmii, "nuc900-emc", "RMII"),
  90         DEF_CLKLOOK(&clk_usbd, "nuc900-usbd", NULL),
  91         DEF_CLKLOOK(&clk_usbh, "nuc900-usbh", NULL),
  92         DEF_CLKLOOK(&clk_g2d, "nuc900-g2d", NULL),
  93         DEF_CLKLOOK(&clk_pwm, "nuc900-pwm", NULL),
  94         DEF_CLKLOOK(&clk_ps2, "nuc900-ps2", NULL),
  95         DEF_CLKLOOK(&clk_kpi, "nuc900-kpi", NULL),
  96         DEF_CLKLOOK(&clk_wdt, "nuc900-wdt", NULL),
  97         DEF_CLKLOOK(&clk_gdma, "nuc900-gdma", NULL),
  98         DEF_CLKLOOK(&clk_adc, "nuc900-ts", NULL),
  99         DEF_CLKLOOK(&clk_usi, "nuc900-spi", NULL),
 100         DEF_CLKLOOK(&clk_ext, NULL, "ext"),
 101         DEF_CLKLOOK(&clk_timer0, NULL, "timer0"),
 102         DEF_CLKLOOK(&clk_timer1, NULL, "timer1"),
 103         DEF_CLKLOOK(&clk_timer2, NULL, "timer2"),
 104         DEF_CLKLOOK(&clk_timer3, NULL, "timer3"),
 105         DEF_CLKLOOK(&clk_timer4, NULL, "timer4"),
 106 };
 107
 108 /* Initial serial platform data */
 109
 110 struct plat_serial8250_port nuc900_uart_data[] = {
 111         NUC900_8250PORT(UART0),
 112         {},
 113 };
 114
 115 struct platform_device nuc900_serial_device = {
 116         .name                   = "serial8250",
 117         .id                     = PLAT8250_DEV_PLATFORM,
 118         .dev                    = {
 119                 .platform_data  = nuc900_uart_data,
 120         },
 121 };
 122
 123 /*Set NUC900 series cpu frequence*/
 124 static int __init nuc900_set_clkval(unsigned int cpufreq)
 125 {
 126         unsigned int pllclk, ahbclk, apbclk, val;
 127
 128         pllclk = 0;
 129         ahbclk = 0;
 130         apbclk = 0;
 131
 132         switch (cpufreq) {
 133         case 66:
 134                 pllclk = PLL_66MHZ;
 135                 ahbclk = AHB_CPUCLK_1_1;
 136                 apbclk = APB_AHB_1_2;
 137                 break;
 138
 139         case 100:
 140                 pllclk = PLL_100MHZ;
 141                 ahbclk = AHB_CPUCLK_1_1;
 142                 apbclk = APB_AHB_1_2;
 143                 break;
 144
 145         case 120:
 146                 pllclk = PLL_120MHZ;
 147                 ahbclk = AHB_CPUCLK_1_2;
 148                 apbclk = APB_AHB_1_2;
 149                 break;
 150
 151         case 166:
 152                 pllclk = PLL_166MHZ;
 153                 ahbclk = AHB_CPUCLK_1_2;
 154                 apbclk = APB_AHB_1_2;
 155                 break;
 156
 157         case 200:
 158                 pllclk = PLL_200MHZ;
 159                 ahbclk = AHB_CPUCLK_1_2;
 160                 apbclk = APB_AHB_1_2;
 161                 break;
 162         }
 163
 164         __raw_writel(pllclk, REG_PLLCON0);
 165
 166         val = __raw_readl(REG_CLKDIV);
 167         val &= ~(0x03 << 24 | 0x03 << 26);
 168         val |= (ahbclk << 24 | apbclk << 26);
 169         __raw_writel(val, REG_CLKDIV);
 170
 171         return  0;
 172 }
 173 static int __init nuc900_set_cpufreq(char *str)
 174 {
 175         unsigned long cpufreq, val;
 176
 177         if (!*str)
 178                 return 0;
 179
 180         strict_strtoul(str, 0, &cpufreq);
 181
 182         nuc900_clock_source(NULL, "ext");
 183
 184         nuc900_set_clkval(cpufreq);
 185
 186         mdelay(1);
 187
 188         val = __raw_readl(REG_CKSKEW);
 189         val &= ~0xff;
 190         val |= DEFAULTSKEW;
 191         __raw_writel(val, REG_CKSKEW);
 192
 193         nuc900_clock_source(NULL, "pll0");
 194
 195         return 1;
 196 }
 197
 198 __setup("cpufreq=", nuc900_set_cpufreq);
 199
 200 /*Init NUC900 evb io*/
 201
 202 void __init nuc900_map_io(struct map_desc *mach_desc, int mach_size)
 203 {
 204         unsigned long idcode = 0x0;
 205
 206         iotable_init(mach_desc, mach_size);
 207         iotable_init(nuc900_iodesc, ARRAY_SIZE(nuc900_iodesc));
 208
 209         idcode = __raw_readl(NUC900PDID);
 210         if (idcode == NUC910_CPUID)
 211                 printk(KERN_INFO "CPU type 0x%08lx is NUC910\n", idcode);
 212         else if (idcode == NUC920_CPUID)
 213                 printk(KERN_INFO "CPU type 0x%08lx is NUC920\n", idcode);
 214         else if (idcode == NUC950_CPUID)
 215                 printk(KERN_INFO "CPU type 0x%08lx is NUC950\n", idcode);
 216         else if (idcode == NUC960_CPUID)
 217                 printk(KERN_INFO "CPU type 0x%08lx is NUC960\n", idcode);
 218 }
 219
 220 /*Init NUC900 clock*/
 221
 222 void __init nuc900_init_clocks(void)
 223 {
 224         clkdev_add_table(nuc900_clkregs, ARRAY_SIZE(nuc900_clkregs));
 225 }
 226
 227 #define WTCR    (TMR_BA + 0x1C)
 228 #define WTCLK   (1 << 10)
 229 #define WTE     (1 << 7)
 230 #define WTRE    (1 << 1)
 231
 232 void nuc9xx_restart(char mode, const char *cmd)
 233 {
 234         if (mode == 's') {
 235                 /* Jump into ROM at address 0 */
 236                 soft_restart(0);
 237         } else {
 238                 __raw_writel(WTE | WTRE | WTCLK, WTCR);
 239         }
 240 }