arch/arm/mach-zynq/include/mach/zynq_soc.h

   1 /* arch/arm/mach-zynq/include/mach/zynq_soc.h
   2  *
   3  *  Copyright (C) 2011 Xilinx
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #ifndef __MACH_XILINX_SOC_H__
  16 #define __MACH_XILINX_SOC_H__
  17
  18 #define PERIPHERAL_CLOCK_RATE           2500000
  19
  20 /* For now, all mappings are flat (physical = virtual)
  21  */
  22 #define UART0_PHYS                      0xE0000000
  23 #define UART0_VIRT                      UART0_PHYS
  24
  25 #define TTC0_PHYS                       0xF8001000
  26 #define TTC0_VIRT                       TTC0_PHYS
  27
  28 #define PL310_L2CC_PHYS                 0xF8F02000
  29 #define PL310_L2CC_VIRT                 PL310_L2CC_PHYS
  30
  31 #define SCU_PERIPH_PHYS                 0xF8F00000
  32 #define SCU_PERIPH_VIRT                 SCU_PERIPH_PHYS
  33
  34 /* The following are intended for the devices that are mapped early */
  35
  36 #define TTC0_BASE                       IOMEM(TTC0_VIRT)
  37 #define SCU_PERIPH_BASE                 IOMEM(SCU_PERIPH_VIRT)
  38 #define SCU_GIC_CPU_BASE                (SCU_PERIPH_BASE + 0x100)
  39 #define SCU_GIC_DIST_BASE               (SCU_PERIPH_BASE + 0x1000)
  40 #define PL310_L2CC_BASE                 IOMEM(PL310_L2CC_VIRT)
  41
  42 /*
  43  * Mandatory for CONFIG_LL_DEBUG, UART is mapped virtual = physical
  44  */
  45 #define LL_UART_PADDR   UART0_PHYS
  46 #define LL_UART_VADDR   UART0_VIRT
  47
  48 #endif