spi-topcliff-pch: Fix issue for transmitting over 4KByte
[zen-stable.git] / arch / arm / plat-mxc / include / mach / mx53.h
bloba37e8c3539941040f754b9288cee57b562d6d808
1 #ifndef __MACH_MX53_H__
2 #define __MACH_MX53_H__
4 /*
5 * IROM
6 */
7 #define MX53_IROM_BASE_ADDR 0x0
8 #define MX53_IROM_SIZE SZ_64K
10 /* TZIC */
11 #define MX53_TZIC_BASE_ADDR 0x0FFFC000
12 #define MX53_TZIC_SIZE SZ_16K
15 * AHCI SATA
17 #define MX53_SATA_BASE_ADDR 0x10000000
20 * NFC
22 #define MX53_NFC_AXI_BASE_ADDR 0xF7FF0000 /* NAND flash AXI */
23 #define MX53_NFC_AXI_SIZE SZ_64K
26 * IRAM
28 #define MX53_IRAM_BASE_ADDR 0xF8000000 /* internal ram */
29 #define MX53_IRAM_PARTITIONS 16
30 #define MX53_IRAM_SIZE (MX53_IRAM_PARTITIONS * SZ_8K) /* 128KB */
33 * Graphics Memory of GPU
35 #define MX53_IPU_CTRL_BASE_ADDR 0x18000000
36 #define MX53_GPU2D_BASE_ADDR 0x20000000
37 #define MX53_GPU_BASE_ADDR 0x30000000
38 #define MX53_GPU_GMEM_BASE_ADDR 0xF8020000
40 #define MX53_DEBUG_BASE_ADDR 0x40000000
41 #define MX53_DEBUG_SIZE SZ_1M
42 #define MX53_ETB_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00001000)
43 #define MX53_ETM_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00002000)
44 #define MX53_TPIU_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00003000)
45 #define MX53_CTI0_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00004000)
46 #define MX53_CTI1_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00005000)
47 #define MX53_CTI2_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00006000)
48 #define MX53_CTI3_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00007000)
49 #define MX53_CORTEX_DBG_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00008000)
52 * SPBA global module enabled #0
54 #define MX53_SPBA0_BASE_ADDR 0x50000000
55 #define MX53_SPBA0_SIZE SZ_1M
57 #define MX53_ESDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000)
58 #define MX53_ESDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000)
59 #define MX53_UART3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0000C000)
60 #define MX53_ECSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000)
61 #define MX53_SSI2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00014000)
62 #define MX53_ESDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000)
63 #define MX53_ESDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000)
64 #define MX53_SPDIF_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00028000)
65 #define MX53_ASRC_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0002C000)
66 #define MX53_ATA_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00030000)
67 #define MX53_SLIM_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00034000)
68 #define MX53_HSI2C_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00038000)
69 #define MX53_SPBA_CTRL_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0003C000)
72 * AIPS 1
74 #define MX53_AIPS1_BASE_ADDR 0x53F00000
75 #define MX53_AIPS1_SIZE SZ_1M
77 #define MX53_OTG_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00080000)
78 #define MX53_GPIO1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00084000)
79 #define MX53_GPIO2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00088000)
80 #define MX53_GPIO3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0008C000)
81 #define MX53_GPIO4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00090000)
82 #define MX53_KPP_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00094000)
83 #define MX53_WDOG1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00098000)
84 #define MX53_WDOG2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0009C000)
85 #define MX53_GPT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A0000)
86 #define MX53_SRTC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A4000)
87 #define MX53_IOMUXC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A8000)
88 #define MX53_EPIT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000AC000)
89 #define MX53_EPIT2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B0000)
90 #define MX53_PWM1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B4000)
91 #define MX53_PWM2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B8000)
92 #define MX53_UART1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000BC000)
93 #define MX53_UART2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000C0000)
94 #define MX53_SRC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D0000)
95 #define MX53_CCM_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D4000)
96 #define MX53_GPC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D8000)
97 #define MX53_GPIO5_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000DC000)
98 #define MX53_GPIO6_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E0000)
99 #define MX53_GPIO7_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E4000)
100 #define MX53_ATA_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E8000)
101 #define MX53_I2C3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000EC000)
102 #define MX53_UART4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000F0000)
105 * AIPS 2
107 #define MX53_AIPS2_BASE_ADDR 0x63F00000
108 #define MX53_AIPS2_SIZE SZ_1M
110 #define MX53_PLL1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00080000)
111 #define MX53_PLL2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00084000)
112 #define MX53_PLL3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00088000)
113 #define MX53_PLL4_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0008C000)
114 #define MX53_UART5_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00090000)
115 #define MX53_AHBMAX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00094000)
116 #define MX53_IIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00098000)
117 #define MX53_CSU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0009C000)
118 #define MX53_ARM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A0000)
119 #define MX53_OWIRE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A4000)
120 #define MX53_FIRI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A8000)
121 #define MX53_ECSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000)
122 #define MX53_SDMA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B0000)
123 #define MX53_SCC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B4000)
124 #define MX53_ROMCP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B8000)
125 #define MX53_RTIC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000BC000)
126 #define MX53_CSPI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000)
127 #define MX53_I2C2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C4000)
128 #define MX53_I2C1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C8000)
129 #define MX53_SSI1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000CC000)
130 #define MX53_AUDMUX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D0000)
131 #define MX53_RTC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D4000)
132 #define MX53_M4IF_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D8000)
133 #define MX53_ESDCTL_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D9000)
134 #define MX53_WEIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DA000)
135 #define MX53_NFC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DB000)
136 #define MX53_EMI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DBF00)
137 #define MX53_MIPI_HSC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DC000)
138 #define MX53_MLB_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E4000)
139 #define MX53_SSI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E8000)
140 #define MX53_FEC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000EC000)
141 #define MX53_TVE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F0000)
142 #define MX53_VPU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F4000)
143 #define MX53_SAHARA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F8000)
144 #define MX53_PTP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000FC000)
147 * Memory regions and CS
149 #define MX53_CSD0_BASE_ADDR 0x70000000
150 #define MX53_CSD1_BASE_ADDR 0xB0000000
151 #define MX53_CS0_BASE_ADDR 0xF0000000
152 #define MX53_CS1_32MB_BASE_ADDR 0xF2000000
153 #define MX53_CS1_64MB_BASE_ADDR 0xF4000000
154 #define MX53_CS2_64MB_BASE_ADDR 0xF4000000
155 #define MX53_CS2_96MB_BASE_ADDR 0xF6000000
156 #define MX53_CS3_BASE_ADDR 0xF6000000
158 #define MX53_IO_P2V(x) IMX_IO_P2V(x)
159 #define MX53_IO_ADDRESS(x) IOMEM(MX53_IO_P2V(x))
162 * defines for SPBA modules
164 #define MX53_SPBA_SDHC1 0x04
165 #define MX53_SPBA_SDHC2 0x08
166 #define MX53_SPBA_UART3 0x0C
167 #define MX53_SPBA_CSPI1 0x10
168 #define MX53_SPBA_SSI2 0x14
169 #define MX53_SPBA_SDHC3 0x20
170 #define MX53_SPBA_SDHC4 0x24
171 #define MX53_SPBA_SPDIF 0x28
172 #define MX53_SPBA_ATA 0x30
173 #define MX53_SPBA_SLIM 0x34
174 #define MX53_SPBA_HSI2C 0x38
175 #define MX53_SPBA_CTRL 0x3C
178 * DMA request assignments
180 #define MX53_DMA_REQ_SSI3_TX0 47
181 #define MX53_DMA_REQ_SSI3_RX0 46
182 #define MX53_DMA_REQ_SSI3_TX1 45
183 #define MX53_DMA_REQ_SSI3_RX1 44
184 #define MX53_DMA_REQ_UART3_TX 43
185 #define MX53_DMA_REQ_UART3_RX 42
186 #define MX53_DMA_REQ_ESAI_TX 41
187 #define MX53_DMA_REQ_ESAI_RX 40
188 #define MX53_DMA_REQ_CSPI_TX 39
189 #define MX53_DMA_REQ_CSPI_RX 38
190 #define MX53_DMA_REQ_ASRC_DMA6 37
191 #define MX53_DMA_REQ_ASRC_DMA5 36
192 #define MX53_DMA_REQ_ASRC_DMA4 35
193 #define MX53_DMA_REQ_ASRC_DMA3 34
194 #define MX53_DMA_REQ_ASRC_DMA2 33
195 #define MX53_DMA_REQ_ASRC_DMA1 32
196 #define MX53_DMA_REQ_EMI_WR 31
197 #define MX53_DMA_REQ_EMI_RD 30
198 #define MX53_DMA_REQ_SSI1_TX0 29
199 #define MX53_DMA_REQ_SSI1_RX0 28
200 #define MX53_DMA_REQ_SSI1_TX1 27
201 #define MX53_DMA_REQ_SSI1_RX1 26
202 #define MX53_DMA_REQ_SSI2_TX0 25
203 #define MX53_DMA_REQ_SSI2_RX0 24
204 #define MX53_DMA_REQ_SSI2_TX1 23
205 #define MX53_DMA_REQ_SSI2_RX1 22
206 #define MX53_DMA_REQ_I2C2_SDHC2 21
207 #define MX53_DMA_REQ_I2C1_SDHC1 20
208 #define MX53_DMA_REQ_UART1_TX 19
209 #define MX53_DMA_REQ_UART1_RX 18
210 #define MX53_DMA_REQ_UART5_TX 17
211 #define MX53_DMA_REQ_UART5_RX 16
212 #define MX53_DMA_REQ_SPDIF_TX 15
213 #define MX53_DMA_REQ_SPDIF_RX 14
214 #define MX53_DMA_REQ_UART2_FIRI_TX 13
215 #define MX53_DMA_REQ_UART2_FIRI_RX 12
216 #define MX53_DMA_REQ_SDHC4 11
217 #define MX53_DMA_REQ_I2C3_SDHC3 10
218 #define MX53_DMA_REQ_CSPI2_TX 9
219 #define MX53_DMA_REQ_CSPI2_RX 8
220 #define MX53_DMA_REQ_CSPI1_TX 7
221 #define MX53_DMA_REQ_CSPI1_RX 6
222 #define MX53_DMA_REQ_IPU 5
223 #define MX53_DMA_REQ_ATA_TX_END 4
224 #define MX53_DMA_REQ_ATA_UART4_TX 3
225 #define MX53_DMA_REQ_ATA_UART4_RX 2
226 #define MX53_DMA_REQ_GPC 1
227 #define MX53_DMA_REQ_VPU 0
230 * Interrupt numbers
232 #define MX53_INT_RESV0 0
233 #define MX53_INT_ESDHC1 1
234 #define MX53_INT_ESDHC2 2
235 #define MX53_INT_ESDHC3 3
236 #define MX53_INT_ESDHC4 4
237 #define MX53_INT_DAP 5
238 #define MX53_INT_SDMA 6
239 #define MX53_INT_IOMUX 7
240 #define MX53_INT_NFC 8
241 #define MX53_INT_VPU 9
242 #define MX53_INT_IPU_ERR 10
243 #define MX53_INT_IPU_SYN 11
244 #define MX53_INT_GPU 12
245 #define MX53_INT_UART4 13
246 #define MX53_INT_USB_H1 14
247 #define MX53_INT_EMI 15
248 #define MX53_INT_USB_H2 16
249 #define MX53_INT_USB_H3 17
250 #define MX53_INT_USB_OTG 18
251 #define MX53_INT_SAHARA_H0 19
252 #define MX53_INT_SAHARA_H1 20
253 #define MX53_INT_SCC_SMN 21
254 #define MX53_INT_SCC_STZ 22
255 #define MX53_INT_SCC_SCM 23
256 #define MX53_INT_SRTC_NTZ 24
257 #define MX53_INT_SRTC_TZ 25
258 #define MX53_INT_RTIC 26
259 #define MX53_INT_CSU 27
260 #define MX53_INT_SATA 28
261 #define MX53_INT_SSI1 29
262 #define MX53_INT_SSI2 30
263 #define MX53_INT_UART1 31
264 #define MX53_INT_UART2 32
265 #define MX53_INT_UART3 33
266 #define MX53_INT_RTC 34
267 #define MX53_INT_PTP 35
268 #define MX53_INT_ECSPI1 36
269 #define MX53_INT_ECSPI2 37
270 #define MX53_INT_CSPI 38
271 #define MX53_INT_GPT 39
272 #define MX53_INT_EPIT1 40
273 #define MX53_INT_EPIT2 41
274 #define MX53_INT_GPIO1_INT7 42
275 #define MX53_INT_GPIO1_INT6 43
276 #define MX53_INT_GPIO1_INT5 44
277 #define MX53_INT_GPIO1_INT4 45
278 #define MX53_INT_GPIO1_INT3 46
279 #define MX53_INT_GPIO1_INT2 47
280 #define MX53_INT_GPIO1_INT1 48
281 #define MX53_INT_GPIO1_INT0 49
282 #define MX53_INT_GPIO1_LOW 50
283 #define MX53_INT_GPIO1_HIGH 51
284 #define MX53_INT_GPIO2_LOW 52
285 #define MX53_INT_GPIO2_HIGH 53
286 #define MX53_INT_GPIO3_LOW 54
287 #define MX53_INT_GPIO3_HIGH 55
288 #define MX53_INT_GPIO4_LOW 56
289 #define MX53_INT_GPIO4_HIGH 57
290 #define MX53_INT_WDOG1 58
291 #define MX53_INT_WDOG2 59
292 #define MX53_INT_KPP 60
293 #define MX53_INT_PWM1 61
294 #define MX53_INT_I2C1 62
295 #define MX53_INT_I2C2 63
296 #define MX53_INT_I2C3 64
297 #define MX53_INT_MLB 65
298 #define MX53_INT_ASRC 66
299 #define MX53_INT_SPDIF 67
300 #define MX53_INT_SIM_DAT 68
301 #define MX53_INT_IIM 69
302 #define MX53_INT_ATA 70
303 #define MX53_INT_CCM1 71
304 #define MX53_INT_CCM2 72
305 #define MX53_INT_GPC1 73
306 #define MX53_INT_GPC2 74
307 #define MX53_INT_SRC 75
308 #define MX53_INT_NM 76
309 #define MX53_INT_PMU 77
310 #define MX53_INT_CTI_IRQ 78
311 #define MX53_INT_CTI1_TG0 79
312 #define MX53_INT_CTI1_TG1 80
313 #define MX53_INT_ESAI 81
314 #define MX53_INT_CAN1 82
315 #define MX53_INT_CAN2 83
316 #define MX53_INT_GPU2_IRQ 84
317 #define MX53_INT_GPU2_BUSY 85
318 #define MX53_INT_UART5 86
319 #define MX53_INT_FEC 87
320 #define MX53_INT_OWIRE 88
321 #define MX53_INT_CTI1_TG2 89
322 #define MX53_INT_SJC 90
323 #define MX53_INT_TVE 92
324 #define MX53_INT_FIRI 93
325 #define MX53_INT_PWM2 94
326 #define MX53_INT_SLIM_EXP 95
327 #define MX53_INT_SSI3 96
328 #define MX53_INT_EMI_BOOT 97
329 #define MX53_INT_CTI1_TG3 98
330 #define MX53_INT_SMC_RX 99
331 #define MX53_INT_VPU_IDLE 100
332 #define MX53_INT_EMI_NFC 101
333 #define MX53_INT_GPU_IDLE 102
334 #define MX53_INT_GPIO5_LOW 103
335 #define MX53_INT_GPIO5_HIGH 104
336 #define MX53_INT_GPIO6_LOW 105
337 #define MX53_INT_GPIO6_HIGH 106
338 #define MX53_INT_GPIO7_LOW 107
339 #define MX53_INT_GPIO7_HIGH 108
341 #endif /* ifndef __MACH_MX53_H__ */