spi-topcliff-pch: Fix issue for transmitting over 4KByte
[zen-stable.git] / arch / arm / plat-spear / clock.c
blob67dd00381ea69bfb7a742c599df4c0c6236c8402
1 /*
2 * arch/arm/plat-spear/clock.c
4 * Clock framework for SPEAr platform
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/bug.h>
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/err.h>
18 #include <linux/io.h>
19 #include <linux/list.h>
20 #include <linux/module.h>
21 #include <linux/spinlock.h>
22 #include <plat/clock.h>
24 static DEFINE_SPINLOCK(clocks_lock);
25 static LIST_HEAD(root_clks);
26 #ifdef CONFIG_DEBUG_FS
27 static LIST_HEAD(clocks);
28 #endif
30 static void propagate_rate(struct clk *, int on_init);
31 #ifdef CONFIG_DEBUG_FS
32 static int clk_debugfs_reparent(struct clk *);
33 #endif
35 static int generic_clk_enable(struct clk *clk)
37 unsigned int val;
39 if (!clk->en_reg)
40 return -EFAULT;
42 val = readl(clk->en_reg);
43 if (unlikely(clk->flags & RESET_TO_ENABLE))
44 val &= ~(1 << clk->en_reg_bit);
45 else
46 val |= 1 << clk->en_reg_bit;
48 writel(val, clk->en_reg);
50 return 0;
53 static void generic_clk_disable(struct clk *clk)
55 unsigned int val;
57 if (!clk->en_reg)
58 return;
60 val = readl(clk->en_reg);
61 if (unlikely(clk->flags & RESET_TO_ENABLE))
62 val |= 1 << clk->en_reg_bit;
63 else
64 val &= ~(1 << clk->en_reg_bit);
66 writel(val, clk->en_reg);
69 /* generic clk ops */
70 static struct clkops generic_clkops = {
71 .enable = generic_clk_enable,
72 .disable = generic_clk_disable,
75 /* returns current programmed clocks clock info structure */
76 static struct pclk_info *pclk_info_get(struct clk *clk)
78 unsigned int val, i;
79 struct pclk_info *info = NULL;
81 val = (readl(clk->pclk_sel->pclk_sel_reg) >> clk->pclk_sel_shift)
82 & clk->pclk_sel->pclk_sel_mask;
84 for (i = 0; i < clk->pclk_sel->pclk_count; i++) {
85 if (clk->pclk_sel->pclk_info[i].pclk_val == val)
86 info = &clk->pclk_sel->pclk_info[i];
89 return info;
93 * Set Update pclk, and pclk_info of clk and add clock sibling node to current
94 * parents children list
96 static void clk_reparent(struct clk *clk, struct pclk_info *pclk_info)
98 unsigned long flags;
100 spin_lock_irqsave(&clocks_lock, flags);
101 list_del(&clk->sibling);
102 list_add(&clk->sibling, &pclk_info->pclk->children);
104 clk->pclk = pclk_info->pclk;
105 spin_unlock_irqrestore(&clocks_lock, flags);
107 #ifdef CONFIG_DEBUG_FS
108 clk_debugfs_reparent(clk);
109 #endif
112 static void do_clk_disable(struct clk *clk)
114 if (!clk)
115 return;
117 if (!clk->usage_count) {
118 WARN_ON(1);
119 return;
122 clk->usage_count--;
124 if (clk->usage_count == 0) {
126 * Surely, there are no active childrens or direct users
127 * of this clock
129 if (clk->pclk)
130 do_clk_disable(clk->pclk);
132 if (clk->ops && clk->ops->disable)
133 clk->ops->disable(clk);
137 static int do_clk_enable(struct clk *clk)
139 int ret = 0;
141 if (!clk)
142 return -EFAULT;
144 if (clk->usage_count == 0) {
145 if (clk->pclk) {
146 ret = do_clk_enable(clk->pclk);
147 if (ret)
148 goto err;
150 if (clk->ops && clk->ops->enable) {
151 ret = clk->ops->enable(clk);
152 if (ret) {
153 if (clk->pclk)
154 do_clk_disable(clk->pclk);
155 goto err;
159 * Since the clock is going to be used for the first
160 * time please reclac
162 if (clk->recalc) {
163 ret = clk->recalc(clk);
164 if (ret)
165 goto err;
168 clk->usage_count++;
169 err:
170 return ret;
174 * clk_enable - inform the system when the clock source should be running.
175 * @clk: clock source
177 * If the clock can not be enabled/disabled, this should return success.
179 * Returns success (0) or negative errno.
181 int clk_enable(struct clk *clk)
183 unsigned long flags;
184 int ret = 0;
186 spin_lock_irqsave(&clocks_lock, flags);
187 ret = do_clk_enable(clk);
188 spin_unlock_irqrestore(&clocks_lock, flags);
189 return ret;
191 EXPORT_SYMBOL(clk_enable);
194 * clk_disable - inform the system when the clock source is no longer required.
195 * @clk: clock source
197 * Inform the system that a clock source is no longer required by
198 * a driver and may be shut down.
200 * Implementation detail: if the clock source is shared between
201 * multiple drivers, clk_enable() calls must be balanced by the
202 * same number of clk_disable() calls for the clock source to be
203 * disabled.
205 void clk_disable(struct clk *clk)
207 unsigned long flags;
209 spin_lock_irqsave(&clocks_lock, flags);
210 do_clk_disable(clk);
211 spin_unlock_irqrestore(&clocks_lock, flags);
213 EXPORT_SYMBOL(clk_disable);
216 * clk_get_rate - obtain the current clock rate (in Hz) for a clock source.
217 * This is only valid once the clock source has been enabled.
218 * @clk: clock source
220 unsigned long clk_get_rate(struct clk *clk)
222 unsigned long flags, rate;
224 spin_lock_irqsave(&clocks_lock, flags);
225 rate = clk->rate;
226 spin_unlock_irqrestore(&clocks_lock, flags);
228 return rate;
230 EXPORT_SYMBOL(clk_get_rate);
233 * clk_set_parent - set the parent clock source for this clock
234 * @clk: clock source
235 * @parent: parent clock source
237 * Returns success (0) or negative errno.
239 int clk_set_parent(struct clk *clk, struct clk *parent)
241 int i, found = 0, val = 0;
242 unsigned long flags;
244 if (!clk || !parent)
245 return -EFAULT;
246 if (clk->pclk == parent)
247 return 0;
248 if (!clk->pclk_sel)
249 return -EPERM;
251 /* check if requested parent is in clk parent list */
252 for (i = 0; i < clk->pclk_sel->pclk_count; i++) {
253 if (clk->pclk_sel->pclk_info[i].pclk == parent) {
254 found = 1;
255 break;
259 if (!found)
260 return -EINVAL;
262 spin_lock_irqsave(&clocks_lock, flags);
263 /* reflect parent change in hardware */
264 val = readl(clk->pclk_sel->pclk_sel_reg);
265 val &= ~(clk->pclk_sel->pclk_sel_mask << clk->pclk_sel_shift);
266 val |= clk->pclk_sel->pclk_info[i].pclk_val << clk->pclk_sel_shift;
267 writel(val, clk->pclk_sel->pclk_sel_reg);
268 spin_unlock_irqrestore(&clocks_lock, flags);
270 /* reflect parent change in software */
271 clk_reparent(clk, &clk->pclk_sel->pclk_info[i]);
273 propagate_rate(clk, 0);
274 return 0;
276 EXPORT_SYMBOL(clk_set_parent);
279 * clk_set_rate - set the clock rate for a clock source
280 * @clk: clock source
281 * @rate: desired clock rate in Hz
283 * Returns success (0) or negative errno.
285 int clk_set_rate(struct clk *clk, unsigned long rate)
287 unsigned long flags;
288 int ret = -EINVAL;
290 if (!clk || !rate)
291 return -EFAULT;
293 if (clk->set_rate) {
294 spin_lock_irqsave(&clocks_lock, flags);
295 ret = clk->set_rate(clk, rate);
296 if (!ret)
297 /* if successful -> propagate */
298 propagate_rate(clk, 0);
299 spin_unlock_irqrestore(&clocks_lock, flags);
300 } else if (clk->pclk) {
301 u32 mult = clk->div_factor ? clk->div_factor : 1;
302 ret = clk_set_rate(clk->pclk, mult * rate);
305 return ret;
307 EXPORT_SYMBOL(clk_set_rate);
309 /* registers clock in platform clock framework */
310 void clk_register(struct clk_lookup *cl)
312 struct clk *clk;
313 unsigned long flags;
315 if (!cl || !cl->clk)
316 return;
317 clk = cl->clk;
319 spin_lock_irqsave(&clocks_lock, flags);
321 INIT_LIST_HEAD(&clk->children);
322 if (clk->flags & ALWAYS_ENABLED)
323 clk->ops = NULL;
324 else if (!clk->ops)
325 clk->ops = &generic_clkops;
327 /* root clock don't have any parents */
328 if (!clk->pclk && !clk->pclk_sel) {
329 list_add(&clk->sibling, &root_clks);
330 } else if (clk->pclk && !clk->pclk_sel) {
331 /* add clocks with only one parent to parent's children list */
332 list_add(&clk->sibling, &clk->pclk->children);
333 } else {
334 /* clocks with more than one parent */
335 struct pclk_info *pclk_info;
337 pclk_info = pclk_info_get(clk);
338 if (!pclk_info) {
339 pr_err("CLKDEV: invalid pclk info of clk with"
340 " %s dev_id and %s con_id\n",
341 cl->dev_id, cl->con_id);
342 } else {
343 clk->pclk = pclk_info->pclk;
344 list_add(&clk->sibling, &pclk_info->pclk->children);
348 spin_unlock_irqrestore(&clocks_lock, flags);
350 /* debugfs specific */
351 #ifdef CONFIG_DEBUG_FS
352 list_add(&clk->node, &clocks);
353 clk->cl = cl;
354 #endif
356 /* add clock to arm clockdev framework */
357 clkdev_add(cl);
361 * propagate_rate - recalculate and propagate all clocks to children
362 * @pclk: parent clock required to be propogated
363 * @on_init: flag for enabling clocks which are ENABLED_ON_INIT.
365 * Recalculates all children clocks
367 void propagate_rate(struct clk *pclk, int on_init)
369 struct clk *clk, *_temp;
370 int ret = 0;
372 list_for_each_entry_safe(clk, _temp, &pclk->children, sibling) {
373 if (clk->recalc) {
374 ret = clk->recalc(clk);
376 * recalc will return error if clk out is not programmed
377 * In this case configure default rate.
379 if (ret && clk->set_rate)
380 clk->set_rate(clk, 0);
382 propagate_rate(clk, on_init);
384 if (!on_init)
385 continue;
387 /* Enable clks enabled on init, in software view */
388 if (clk->flags & ENABLED_ON_INIT)
389 do_clk_enable(clk);
394 * round_rate_index - return closest programmable rate index in rate_config tbl
395 * @clk: ptr to clock structure
396 * @drate: desired rate
397 * @rate: final rate will be returned in this variable only.
399 * Finds index in rate_config for highest clk rate which is less than
400 * requested rate. If there is no clk rate lesser than requested rate then
401 * -EINVAL is returned. This routine assumes that rate_config is written
402 * in incrementing order of clk rates.
403 * If drate passed is zero then default rate is programmed.
405 static int
406 round_rate_index(struct clk *clk, unsigned long drate, unsigned long *rate)
408 unsigned long tmp = 0, prev_rate = 0;
409 int index;
411 if (!clk->calc_rate)
412 return -EFAULT;
414 if (!drate)
415 return -EINVAL;
418 * This loops ends on two conditions:
419 * - as soon as clk is found with rate greater than requested rate.
420 * - if all clks in rate_config are smaller than requested rate.
422 for (index = 0; index < clk->rate_config.count; index++) {
423 prev_rate = tmp;
424 tmp = clk->calc_rate(clk, index);
425 if (drate < tmp) {
426 index--;
427 break;
430 /* return if can't find suitable clock */
431 if (index < 0) {
432 index = -EINVAL;
433 *rate = 0;
434 } else if (index == clk->rate_config.count) {
435 /* program with highest clk rate possible */
436 index = clk->rate_config.count - 1;
437 *rate = tmp;
438 } else
439 *rate = prev_rate;
441 return index;
445 * clk_round_rate - adjust a rate to the exact rate a clock can provide
446 * @clk: clock source
447 * @rate: desired clock rate in Hz
449 * Returns rounded clock rate in Hz, or negative errno.
451 long clk_round_rate(struct clk *clk, unsigned long drate)
453 long rate = 0;
454 int index;
457 * propagate call to parent who supports calc_rate. Similar approach is
458 * used in clk_set_rate.
460 if (!clk->calc_rate) {
461 u32 mult;
462 if (!clk->pclk)
463 return clk->rate;
465 mult = clk->div_factor ? clk->div_factor : 1;
466 return clk_round_rate(clk->pclk, mult * drate) / mult;
469 index = round_rate_index(clk, drate, &rate);
470 if (index >= 0)
471 return rate;
472 else
473 return index;
475 EXPORT_SYMBOL(clk_round_rate);
477 /*All below functions are called with lock held */
480 * Calculates pll clk rate for specific value of mode, m, n and p
482 * In normal mode
483 * rate = (2 * M[15:8] * Fin)/(N * 2^P)
485 * In Dithered mode
486 * rate = (2 * M[15:0] * Fin)/(256 * N * 2^P)
488 unsigned long pll_calc_rate(struct clk *clk, int index)
490 unsigned long rate = clk->pclk->rate;
491 struct pll_rate_tbl *tbls = clk->rate_config.tbls;
492 unsigned int mode;
494 mode = tbls[index].mode ? 256 : 1;
495 return (((2 * rate / 10000) * tbls[index].m) /
496 (mode * tbls[index].n * (1 << tbls[index].p))) * 10000;
500 * calculates current programmed rate of pll1
502 * In normal mode
503 * rate = (2 * M[15:8] * Fin)/(N * 2^P)
505 * In Dithered mode
506 * rate = (2 * M[15:0] * Fin)/(256 * N * 2^P)
508 int pll_clk_recalc(struct clk *clk)
510 struct pll_clk_config *config = clk->private_data;
511 unsigned int num = 2, den = 0, val, mode = 0;
513 mode = (readl(config->mode_reg) >> config->masks->mode_shift) &
514 config->masks->mode_mask;
516 val = readl(config->cfg_reg);
517 /* calculate denominator */
518 den = (val >> config->masks->div_p_shift) & config->masks->div_p_mask;
519 den = 1 << den;
520 den *= (val >> config->masks->div_n_shift) & config->masks->div_n_mask;
522 /* calculate numerator & denominator */
523 if (!mode) {
524 /* Normal mode */
525 num *= (val >> config->masks->norm_fdbk_m_shift) &
526 config->masks->norm_fdbk_m_mask;
527 } else {
528 /* Dithered mode */
529 num *= (val >> config->masks->dith_fdbk_m_shift) &
530 config->masks->dith_fdbk_m_mask;
531 den *= 256;
534 if (!den)
535 return -EINVAL;
537 clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000;
538 return 0;
542 * Configures new clock rate of pll
544 int pll_clk_set_rate(struct clk *clk, unsigned long desired_rate)
546 struct pll_rate_tbl *tbls = clk->rate_config.tbls;
547 struct pll_clk_config *config = clk->private_data;
548 unsigned long val, rate;
549 int i;
551 i = round_rate_index(clk, desired_rate, &rate);
552 if (i < 0)
553 return i;
555 val = readl(config->mode_reg) &
556 ~(config->masks->mode_mask << config->masks->mode_shift);
557 val |= (tbls[i].mode & config->masks->mode_mask) <<
558 config->masks->mode_shift;
559 writel(val, config->mode_reg);
561 val = readl(config->cfg_reg) &
562 ~(config->masks->div_p_mask << config->masks->div_p_shift);
563 val |= (tbls[i].p & config->masks->div_p_mask) <<
564 config->masks->div_p_shift;
565 val &= ~(config->masks->div_n_mask << config->masks->div_n_shift);
566 val |= (tbls[i].n & config->masks->div_n_mask) <<
567 config->masks->div_n_shift;
568 val &= ~(config->masks->dith_fdbk_m_mask <<
569 config->masks->dith_fdbk_m_shift);
570 if (tbls[i].mode)
571 val |= (tbls[i].m & config->masks->dith_fdbk_m_mask) <<
572 config->masks->dith_fdbk_m_shift;
573 else
574 val |= (tbls[i].m & config->masks->norm_fdbk_m_mask) <<
575 config->masks->norm_fdbk_m_shift;
577 writel(val, config->cfg_reg);
579 clk->rate = rate;
581 return 0;
585 * Calculates ahb, apb clk rate for specific value of div
587 unsigned long bus_calc_rate(struct clk *clk, int index)
589 unsigned long rate = clk->pclk->rate;
590 struct bus_rate_tbl *tbls = clk->rate_config.tbls;
592 return rate / (tbls[index].div + 1);
595 /* calculates current programmed rate of ahb or apb bus */
596 int bus_clk_recalc(struct clk *clk)
598 struct bus_clk_config *config = clk->private_data;
599 unsigned int div;
601 div = ((readl(config->reg) >> config->masks->shift) &
602 config->masks->mask) + 1;
604 if (!div)
605 return -EINVAL;
607 clk->rate = (unsigned long)clk->pclk->rate / div;
608 return 0;
611 /* Configures new clock rate of AHB OR APB bus */
612 int bus_clk_set_rate(struct clk *clk, unsigned long desired_rate)
614 struct bus_rate_tbl *tbls = clk->rate_config.tbls;
615 struct bus_clk_config *config = clk->private_data;
616 unsigned long val, rate;
617 int i;
619 i = round_rate_index(clk, desired_rate, &rate);
620 if (i < 0)
621 return i;
623 val = readl(config->reg) &
624 ~(config->masks->mask << config->masks->shift);
625 val |= (tbls[i].div & config->masks->mask) << config->masks->shift;
626 writel(val, config->reg);
628 clk->rate = rate;
630 return 0;
634 * gives rate for different values of eq, x and y
636 * Fout from synthesizer can be given from two equations:
637 * Fout1 = (Fin * X/Y)/2 EQ1
638 * Fout2 = Fin * X/Y EQ2
640 unsigned long aux_calc_rate(struct clk *clk, int index)
642 unsigned long rate = clk->pclk->rate;
643 struct aux_rate_tbl *tbls = clk->rate_config.tbls;
644 u8 eq = tbls[index].eq ? 1 : 2;
646 return (((rate/10000) * tbls[index].xscale) /
647 (tbls[index].yscale * eq)) * 10000;
651 * calculates current programmed rate of auxiliary synthesizers
652 * used by: UART, FIRDA
654 * Fout from synthesizer can be given from two equations:
655 * Fout1 = (Fin * X/Y)/2
656 * Fout2 = Fin * X/Y
658 * Selection of eqn 1 or 2 is programmed in register
660 int aux_clk_recalc(struct clk *clk)
662 struct aux_clk_config *config = clk->private_data;
663 unsigned int num = 1, den = 1, val, eqn;
665 val = readl(config->synth_reg);
667 eqn = (val >> config->masks->eq_sel_shift) &
668 config->masks->eq_sel_mask;
669 if (eqn == config->masks->eq1_mask)
670 den *= 2;
672 /* calculate numerator */
673 num = (val >> config->masks->xscale_sel_shift) &
674 config->masks->xscale_sel_mask;
676 /* calculate denominator */
677 den *= (val >> config->masks->yscale_sel_shift) &
678 config->masks->yscale_sel_mask;
680 if (!den)
681 return -EINVAL;
683 clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000;
684 return 0;
687 /* Configures new clock rate of auxiliary synthesizers used by: UART, FIRDA*/
688 int aux_clk_set_rate(struct clk *clk, unsigned long desired_rate)
690 struct aux_rate_tbl *tbls = clk->rate_config.tbls;
691 struct aux_clk_config *config = clk->private_data;
692 unsigned long val, rate;
693 int i;
695 i = round_rate_index(clk, desired_rate, &rate);
696 if (i < 0)
697 return i;
699 val = readl(config->synth_reg) &
700 ~(config->masks->eq_sel_mask << config->masks->eq_sel_shift);
701 val |= (tbls[i].eq & config->masks->eq_sel_mask) <<
702 config->masks->eq_sel_shift;
703 val &= ~(config->masks->xscale_sel_mask <<
704 config->masks->xscale_sel_shift);
705 val |= (tbls[i].xscale & config->masks->xscale_sel_mask) <<
706 config->masks->xscale_sel_shift;
707 val &= ~(config->masks->yscale_sel_mask <<
708 config->masks->yscale_sel_shift);
709 val |= (tbls[i].yscale & config->masks->yscale_sel_mask) <<
710 config->masks->yscale_sel_shift;
711 writel(val, config->synth_reg);
713 clk->rate = rate;
715 return 0;
719 * Calculates gpt clk rate for different values of mscale and nscale
721 * Fout= Fin/((2 ^ (N+1)) * (M+1))
723 unsigned long gpt_calc_rate(struct clk *clk, int index)
725 unsigned long rate = clk->pclk->rate;
726 struct gpt_rate_tbl *tbls = clk->rate_config.tbls;
728 return rate / ((1 << (tbls[index].nscale + 1)) *
729 (tbls[index].mscale + 1));
733 * calculates current programmed rate of gpt synthesizers
734 * Fout from synthesizer can be given from below equations:
735 * Fout= Fin/((2 ^ (N+1)) * (M+1))
737 int gpt_clk_recalc(struct clk *clk)
739 struct gpt_clk_config *config = clk->private_data;
740 unsigned int div = 1, val;
742 val = readl(config->synth_reg);
743 div += (val >> config->masks->mscale_sel_shift) &
744 config->masks->mscale_sel_mask;
745 div *= 1 << (((val >> config->masks->nscale_sel_shift) &
746 config->masks->nscale_sel_mask) + 1);
748 if (!div)
749 return -EINVAL;
751 clk->rate = (unsigned long)clk->pclk->rate / div;
752 return 0;
755 /* Configures new clock rate of gptiliary synthesizers used by: UART, FIRDA*/
756 int gpt_clk_set_rate(struct clk *clk, unsigned long desired_rate)
758 struct gpt_rate_tbl *tbls = clk->rate_config.tbls;
759 struct gpt_clk_config *config = clk->private_data;
760 unsigned long val, rate;
761 int i;
763 i = round_rate_index(clk, desired_rate, &rate);
764 if (i < 0)
765 return i;
767 val = readl(config->synth_reg) & ~(config->masks->mscale_sel_mask <<
768 config->masks->mscale_sel_shift);
769 val |= (tbls[i].mscale & config->masks->mscale_sel_mask) <<
770 config->masks->mscale_sel_shift;
771 val &= ~(config->masks->nscale_sel_mask <<
772 config->masks->nscale_sel_shift);
773 val |= (tbls[i].nscale & config->masks->nscale_sel_mask) <<
774 config->masks->nscale_sel_shift;
775 writel(val, config->synth_reg);
777 clk->rate = rate;
779 return 0;
783 * Calculates clcd clk rate for different values of div
785 * Fout from synthesizer can be given from below equation:
786 * Fout= Fin/2*div (division factor)
787 * div is 17 bits:-
788 * 0-13 (fractional part)
789 * 14-16 (integer part)
790 * To calculate Fout we left shift val by 14 bits and divide Fin by
791 * complete div (including fractional part) and then right shift the
792 * result by 14 places.
794 unsigned long clcd_calc_rate(struct clk *clk, int index)
796 unsigned long rate = clk->pclk->rate;
797 struct clcd_rate_tbl *tbls = clk->rate_config.tbls;
799 rate /= 1000;
800 rate <<= 12;
801 rate /= (2 * tbls[index].div);
802 rate >>= 12;
803 rate *= 1000;
805 return rate;
809 * calculates current programmed rate of clcd synthesizer
810 * Fout from synthesizer can be given from below equation:
811 * Fout= Fin/2*div (division factor)
812 * div is 17 bits:-
813 * 0-13 (fractional part)
814 * 14-16 (integer part)
815 * To calculate Fout we left shift val by 14 bits and divide Fin by
816 * complete div (including fractional part) and then right shift the
817 * result by 14 places.
819 int clcd_clk_recalc(struct clk *clk)
821 struct clcd_clk_config *config = clk->private_data;
822 unsigned int div = 1;
823 unsigned long prate;
824 unsigned int val;
826 val = readl(config->synth_reg);
827 div = (val >> config->masks->div_factor_shift) &
828 config->masks->div_factor_mask;
830 if (!div)
831 return -EINVAL;
833 prate = clk->pclk->rate / 1000; /* first level division, make it KHz */
835 clk->rate = (((unsigned long)prate << 12) / (2 * div)) >> 12;
836 clk->rate *= 1000;
837 return 0;
840 /* Configures new clock rate of auxiliary synthesizers used by: UART, FIRDA*/
841 int clcd_clk_set_rate(struct clk *clk, unsigned long desired_rate)
843 struct clcd_rate_tbl *tbls = clk->rate_config.tbls;
844 struct clcd_clk_config *config = clk->private_data;
845 unsigned long val, rate;
846 int i;
848 i = round_rate_index(clk, desired_rate, &rate);
849 if (i < 0)
850 return i;
852 val = readl(config->synth_reg) & ~(config->masks->div_factor_mask <<
853 config->masks->div_factor_shift);
854 val |= (tbls[i].div & config->masks->div_factor_mask) <<
855 config->masks->div_factor_shift;
856 writel(val, config->synth_reg);
858 clk->rate = rate;
860 return 0;
864 * Used for clocks that always have value as the parent clock divided by a
865 * fixed divisor
867 int follow_parent(struct clk *clk)
869 unsigned int div_factor = (clk->div_factor < 1) ? 1 : clk->div_factor;
871 clk->rate = clk->pclk->rate/div_factor;
872 return 0;
876 * recalc_root_clocks - recalculate and propagate all root clocks
878 * Recalculates all root clocks (clocks with no parent), which if the
879 * clock's .recalc is set correctly, should also propagate their rates.
881 void recalc_root_clocks(void)
883 struct clk *pclk;
884 unsigned long flags;
885 int ret = 0;
887 spin_lock_irqsave(&clocks_lock, flags);
888 list_for_each_entry(pclk, &root_clks, sibling) {
889 if (pclk->recalc) {
890 ret = pclk->recalc(pclk);
892 * recalc will return error if clk out is not programmed
893 * In this case configure default clock.
895 if (ret && pclk->set_rate)
896 pclk->set_rate(pclk, 0);
898 propagate_rate(pclk, 1);
899 /* Enable clks enabled on init, in software view */
900 if (pclk->flags & ENABLED_ON_INIT)
901 do_clk_enable(pclk);
903 spin_unlock_irqrestore(&clocks_lock, flags);
906 void __init clk_init(void)
908 recalc_root_clocks();
911 #ifdef CONFIG_DEBUG_FS
913 * debugfs support to trace clock tree hierarchy and attributes
915 static struct dentry *clk_debugfs_root;
916 static int clk_debugfs_register_one(struct clk *c)
918 int err;
919 struct dentry *d;
920 struct clk *pa = c->pclk;
921 char s[255];
922 char *p = s;
924 if (c) {
925 if (c->cl->con_id)
926 p += sprintf(p, "%s", c->cl->con_id);
927 if (c->cl->dev_id)
928 p += sprintf(p, "%s", c->cl->dev_id);
930 d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
931 if (!d)
932 return -ENOMEM;
933 c->dent = d;
935 d = debugfs_create_u32("usage_count", S_IRUGO, c->dent,
936 (u32 *)&c->usage_count);
937 if (!d) {
938 err = -ENOMEM;
939 goto err_out;
941 d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
942 if (!d) {
943 err = -ENOMEM;
944 goto err_out;
946 d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
947 if (!d) {
948 err = -ENOMEM;
949 goto err_out;
951 return 0;
953 err_out:
954 debugfs_remove_recursive(c->dent);
955 return err;
958 static int clk_debugfs_register(struct clk *c)
960 int err;
961 struct clk *pa = c->pclk;
963 if (pa && !pa->dent) {
964 err = clk_debugfs_register(pa);
965 if (err)
966 return err;
969 if (!c->dent) {
970 err = clk_debugfs_register_one(c);
971 if (err)
972 return err;
974 return 0;
977 static int __init clk_debugfs_init(void)
979 struct clk *c;
980 struct dentry *d;
981 int err;
983 d = debugfs_create_dir("clock", NULL);
984 if (!d)
985 return -ENOMEM;
986 clk_debugfs_root = d;
988 list_for_each_entry(c, &clocks, node) {
989 err = clk_debugfs_register(c);
990 if (err)
991 goto err_out;
993 return 0;
994 err_out:
995 debugfs_remove_recursive(clk_debugfs_root);
996 return err;
998 late_initcall(clk_debugfs_init);
1000 static int clk_debugfs_reparent(struct clk *c)
1002 debugfs_remove(c->dent);
1003 return clk_debugfs_register_one(c);
1005 #endif /* CONFIG_DEBUG_FS */