spi-topcliff-pch: Fix issue for transmitting over 4KByte
[zen-stable.git] / arch / avr32 / include / asm / cache.h
blobc3a58a189a914423bb5327ca0c6e487b564aad56
1 #ifndef __ASM_AVR32_CACHE_H
2 #define __ASM_AVR32_CACHE_H
4 #define L1_CACHE_SHIFT 5
5 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
7 /*
8 * Memory returned by kmalloc() may be used for DMA, so we must make
9 * sure that all such allocations are cache aligned. Otherwise,
10 * unrelated code may cause parts of the buffer to be read into the
11 * cache before the transfer is done, causing old data to be seen by
12 * the CPU.
14 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
16 #ifndef __ASSEMBLER__
17 struct cache_info {
18 unsigned int ways;
19 unsigned int sets;
20 unsigned int linesz;
22 #endif /* __ASSEMBLER */
24 /* Cache operation constants */
25 #define ICACHE_FLUSH 0x00
26 #define ICACHE_INVALIDATE 0x01
27 #define ICACHE_LOCK 0x02
28 #define ICACHE_UNLOCK 0x03
29 #define ICACHE_PREFETCH 0x04
31 #define DCACHE_FLUSH 0x08
32 #define DCACHE_LOCK 0x09
33 #define DCACHE_UNLOCK 0x0a
34 #define DCACHE_INVALIDATE 0x0b
35 #define DCACHE_CLEAN 0x0c
36 #define DCACHE_CLEAN_INVAL 0x0d
38 #endif /* __ASM_AVR32_CACHE_H */