arch/ia64/pci/pci.c

   1 /*
   2  * pci.c - Low-Level PCI Access in IA-64
   3  *
   4  * Derived from bios32.c of i386 tree.
   5  *
   6  * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P.
   7  *      David Mosberger-Tang <davidm@hpl.hp.com>
   8  *      Bjorn Helgaas <bjorn.helgaas@hp.com>
   9  * Copyright (C) 2004 Silicon Graphics, Inc.
  10  *
  11  * Note: Above list of copyright holders is incomplete...
  12  */
  13
  14 #include <linux/acpi.h>
  15 #include <linux/types.h>
  16 #include <linux/kernel.h>
  17 #include <linux/pci.h>
  18 #include <linux/init.h>
  19 #include <linux/ioport.h>
  20 #include <linux/slab.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/bootmem.h>
  23 #include <linux/export.h>
  24
  25 #include <asm/machvec.h>
  26 #include <asm/page.h>
  27 #include <asm/system.h>
  28 #include <asm/io.h>
  29 #include <asm/sal.h>
  30 #include <asm/smp.h>
  31 #include <asm/irq.h>
  32 #include <asm/hw_irq.h>
  33
  34 /*
  35  * Low-level SAL-based PCI configuration access functions. Note that SAL
  36  * calls are already serialized (via sal_lock), so we don't need another
  37  * synchronization mechanism here.
  38  */
  39
  40 #define PCI_SAL_ADDRESS(seg, bus, devfn, reg)           \
  41         (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg))
  42
  43 /* SAL 3.2 adds support for extended config space. */
  44
  45 #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg)       \
  46         (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg))
  47
  48 int raw_pci_read(unsigned int seg, unsigned int bus, unsigned int devfn,
  49               int reg, int len, u32 *value)
  50 {
  51         u64 addr, data = 0;
  52         int mode, result;
  53
  54         if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
  55                 return -EINVAL;
  56
  57         if ((seg | reg) <= 255) {
  58                 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
  59                 mode = 0;
  60         } else if (sal_revision >= SAL_VERSION_CODE(3,2)) {
  61                 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
  62                 mode = 1;
  63         } else {
  64                 return -EINVAL;
  65         }
  66
  67         result = ia64_sal_pci_config_read(addr, mode, len, &data);
  68         if (result != 0)
  69                 return -EINVAL;
  70
  71         *value = (u32) data;
  72         return 0;
  73 }
  74
  75 int raw_pci_write(unsigned int seg, unsigned int bus, unsigned int devfn,
  76                int reg, int len, u32 value)
  77 {
  78         u64 addr;
  79         int mode, result;
  80
  81         if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
  82                 return -EINVAL;
  83
  84         if ((seg | reg) <= 255) {
  85                 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
  86                 mode = 0;
  87         } else if (sal_revision >= SAL_VERSION_CODE(3,2)) {
  88                 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
  89                 mode = 1;
  90         } else {
  91                 return -EINVAL;
  92         }
  93         result = ia64_sal_pci_config_write(addr, mode, len, value);
  94         if (result != 0)
  95                 return -EINVAL;
  96         return 0;
  97 }
  98
  99 static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
 100                                                         int size, u32 *value)
 101 {
 102         return raw_pci_read(pci_domain_nr(bus), bus->number,
 103                                  devfn, where, size, value);
 104 }
 105
 106 static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
 107                                                         int size, u32 value)
 108 {
 109         return raw_pci_write(pci_domain_nr(bus), bus->number,
 110                                   devfn, where, size, value);
 111 }
 112
 113 struct pci_ops pci_root_ops = {
 114         .read = pci_read,
 115         .write = pci_write,
 116 };
 117
 118 /* Called by ACPI when it finds a new root bus.  */
 119
 120 static struct pci_controller * __devinit
 121 alloc_pci_controller (int seg)
 122 {
 123         struct pci_controller *controller;
 124
 125         controller = kzalloc(sizeof(*controller), GFP_KERNEL);
 126         if (!controller)
 127                 return NULL;
 128
 129         controller->segment = seg;
 130         controller->node = -1;
 131         return controller;
 132 }
 133
 134 struct pci_root_info {
 135         struct acpi_device *bridge;
 136         struct pci_controller *controller;
 137         struct list_head resources;
 138         char *name;
 139 };
 140
 141 static unsigned int
 142 new_space (u64 phys_base, int sparse)
 143 {
 144         u64 mmio_base;
 145         int i;
 146
 147         if (phys_base == 0)
 148                 return 0;       /* legacy I/O port space */
 149
 150         mmio_base = (u64) ioremap(phys_base, 0);
 151         for (i = 0; i < num_io_spaces; i++)
 152                 if (io_space[i].mmio_base == mmio_base &&
 153                     io_space[i].sparse == sparse)
 154                         return i;
 155
 156         if (num_io_spaces == MAX_IO_SPACES) {
 157                 printk(KERN_ERR "PCI: Too many IO port spaces "
 158                         "(MAX_IO_SPACES=%lu)\n", MAX_IO_SPACES);
 159                 return ~0;
 160         }
 161
 162         i = num_io_spaces++;
 163         io_space[i].mmio_base = mmio_base;
 164         io_space[i].sparse = sparse;
 165
 166         return i;
 167 }
 168
 169 static u64 __devinit
 170 add_io_space (struct pci_root_info *info, struct acpi_resource_address64 *addr)
 171 {
 172         struct resource *resource;
 173         char *name;
 174         unsigned long base, min, max, base_port;
 175         unsigned int sparse = 0, space_nr, len;
 176
 177         resource = kzalloc(sizeof(*resource), GFP_KERNEL);
 178         if (!resource) {
 179                 printk(KERN_ERR "PCI: No memory for %s I/O port space\n",
 180                         info->name);
 181                 goto out;
 182         }
 183
 184         len = strlen(info->name) + 32;
 185         name = kzalloc(len, GFP_KERNEL);
 186         if (!name) {
 187                 printk(KERN_ERR "PCI: No memory for %s I/O port space name\n",
 188                         info->name);
 189                 goto free_resource;
 190         }
 191
 192         min = addr->minimum;
 193         max = min + addr->address_length - 1;
 194         if (addr->info.io.translation_type == ACPI_SPARSE_TRANSLATION)
 195                 sparse = 1;
 196
 197         space_nr = new_space(addr->translation_offset, sparse);
 198         if (space_nr == ~0)
 199                 goto free_name;
 200
 201         base = __pa(io_space[space_nr].mmio_base);
 202         base_port = IO_SPACE_BASE(space_nr);
 203         snprintf(name, len, "%s I/O Ports %08lx-%08lx", info->name,
 204                 base_port + min, base_port + max);
 205
 206         /*
 207          * The SDM guarantees the legacy 0-64K space is sparse, but if the
 208          * mapping is done by the processor (not the bridge), ACPI may not
 209          * mark it as sparse.
 210          */
 211         if (space_nr == 0)
 212                 sparse = 1;
 213
 214         resource->name  = name;
 215         resource->flags = IORESOURCE_MEM;
 216         resource->start = base + (sparse ? IO_SPACE_SPARSE_ENCODING(min) : min);
 217         resource->end   = base + (sparse ? IO_SPACE_SPARSE_ENCODING(max) : max);
 218         insert_resource(&iomem_resource, resource);
 219
 220         return base_port;
 221
 222 free_name:
 223         kfree(name);
 224 free_resource:
 225         kfree(resource);
 226 out:
 227         return ~0;
 228 }
 229
 230 static acpi_status __devinit resource_to_window(struct acpi_resource *resource,
 231         struct acpi_resource_address64 *addr)
 232 {
 233         acpi_status status;
 234
 235         /*
 236          * We're only interested in _CRS descriptors that are
 237          *      - address space descriptors for memory or I/O space
 238          *      - non-zero size
 239          *      - producers, i.e., the address space is routed downstream,
 240          *        not consumed by the bridge itself
 241          */
 242         status = acpi_resource_to_address64(resource, addr);
 243         if (ACPI_SUCCESS(status) &&
 244             (addr->resource_type == ACPI_MEMORY_RANGE ||
 245              addr->resource_type == ACPI_IO_RANGE) &&
 246             addr->address_length &&
 247             addr->producer_consumer == ACPI_PRODUCER)
 248                 return AE_OK;
 249
 250         return AE_ERROR;
 251 }
 252
 253 static acpi_status __devinit
 254 count_window (struct acpi_resource *resource, void *data)
 255 {
 256         unsigned int *windows = (unsigned int *) data;
 257         struct acpi_resource_address64 addr;
 258         acpi_status status;
 259
 260         status = resource_to_window(resource, &addr);
 261         if (ACPI_SUCCESS(status))
 262                 (*windows)++;
 263
 264         return AE_OK;
 265 }
 266
 267 static __devinit acpi_status add_window(struct acpi_resource *res, void *data)
 268 {
 269         struct pci_root_info *info = data;
 270         struct pci_window *window;
 271         struct acpi_resource_address64 addr;
 272         acpi_status status;
 273         unsigned long flags, offset = 0;
 274         struct resource *root;
 275
 276         /* Return AE_OK for non-window resources to keep scanning for more */
 277         status = resource_to_window(res, &addr);
 278         if (!ACPI_SUCCESS(status))
 279                 return AE_OK;
 280
 281         if (addr.resource_type == ACPI_MEMORY_RANGE) {
 282                 flags = IORESOURCE_MEM;
 283                 root = &iomem_resource;
 284                 offset = addr.translation_offset;
 285         } else if (addr.resource_type == ACPI_IO_RANGE) {
 286                 flags = IORESOURCE_IO;
 287                 root = &ioport_resource;
 288                 offset = add_io_space(info, &addr);
 289                 if (offset == ~0)
 290                         return AE_OK;
 291         } else
 292                 return AE_OK;
 293
 294         window = &info->controller->window[info->controller->windows++];
 295         window->resource.name = info->name;
 296         window->resource.flags = flags;
 297         window->resource.start = addr.minimum + offset;
 298         window->resource.end = window->resource.start + addr.address_length - 1;
 299         window->resource.child = NULL;
 300         window->offset = offset;
 301
 302         if (insert_resource(root, &window->resource)) {
 303                 dev_err(&info->bridge->dev,
 304                         "can't allocate host bridge window %pR\n",
 305                         &window->resource);
 306         } else {
 307                 if (offset)
 308                         dev_info(&info->bridge->dev, "host bridge window %pR "
 309                                  "(PCI address [%#llx-%#llx])\n",
 310                                  &window->resource,
 311                                  window->resource.start - offset,
 312                                  window->resource.end - offset);
 313                 else
 314                         dev_info(&info->bridge->dev,
 315                                  "host bridge window %pR\n",
 316                                  &window->resource);
 317         }
 318
 319         /* HP's firmware has a hack to work around a Windows bug.
 320          * Ignore these tiny memory ranges */
 321         if (!((window->resource.flags & IORESOURCE_MEM) &&
 322               (window->resource.end - window->resource.start < 16)))
 323                 pci_add_resource(&info->resources, &window->resource);
 324
 325         return AE_OK;
 326 }
 327
 328 struct pci_bus * __devinit
 329 pci_acpi_scan_root(struct acpi_pci_root *root)
 330 {
 331         struct acpi_device *device = root->device;
 332         int domain = root->segment;
 333         int bus = root->secondary.start;
 334         struct pci_controller *controller;
 335         unsigned int windows = 0;
 336         struct pci_root_info info;
 337         struct pci_bus *pbus;
 338         char *name;
 339         int pxm;
 340
 341         controller = alloc_pci_controller(domain);
 342         if (!controller)
 343                 goto out1;
 344
 345         controller->acpi_handle = device->handle;
 346
 347         pxm = acpi_get_pxm(controller->acpi_handle);
 348 #ifdef CONFIG_NUMA
 349         if (pxm >= 0)
 350                 controller->node = pxm_to_node(pxm);
 351 #endif
 352
 353         INIT_LIST_HEAD(&info.resources);
 354         acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window,
 355                         &windows);
 356         if (windows) {
 357                 controller->window =
 358                         kmalloc_node(sizeof(*controller->window) * windows,
 359                                      GFP_KERNEL, controller->node);
 360                 if (!controller->window)
 361                         goto out2;
 362
 363                 name = kmalloc(16, GFP_KERNEL);
 364                 if (!name)
 365                         goto out3;
 366
 367                 sprintf(name, "PCI Bus %04x:%02x", domain, bus);
 368                 info.bridge = device;
 369                 info.controller = controller;
 370                 info.name = name;
 371                 acpi_walk_resources(device->handle, METHOD_NAME__CRS,
 372                         add_window, &info);
 373         }
 374         /*
 375          * See arch/x86/pci/acpi.c.
 376          * The desired pci bus might already be scanned in a quirk. We
 377          * should handle the case here, but it appears that IA64 hasn't
 378          * such quirk. So we just ignore the case now.
 379          */
 380         pbus = pci_create_root_bus(NULL, bus, &pci_root_ops, controller,
 381                                    &info.resources);
 382         if (!pbus) {
 383                 pci_free_resource_list(&info.resources);
 384                 return NULL;
 385         }
 386
 387         pbus->subordinate = pci_scan_child_bus(pbus);
 388         return pbus;
 389
 390 out3:
 391         kfree(controller->window);
 392 out2:
 393         kfree(controller);
 394 out1:
 395         return NULL;
 396 }
 397
 398 void pcibios_resource_to_bus(struct pci_dev *dev,
 399                 struct pci_bus_region *region, struct resource *res)
 400 {
 401         struct pci_controller *controller = PCI_CONTROLLER(dev);
 402         unsigned long offset = 0;
 403         int i;
 404
 405         for (i = 0; i < controller->windows; i++) {
 406                 struct pci_window *window = &controller->window[i];
 407                 if (!(window->resource.flags & res->flags))
 408                         continue;
 409                 if (window->resource.start > res->start)
 410                         continue;
 411                 if (window->resource.end < res->end)
 412                         continue;
 413                 offset = window->offset;
 414                 break;
 415         }
 416
 417         region->start = res->start - offset;
 418         region->end = res->end - offset;
 419 }
 420 EXPORT_SYMBOL(pcibios_resource_to_bus);
 421
 422 void pcibios_bus_to_resource(struct pci_dev *dev,
 423                 struct resource *res, struct pci_bus_region *region)
 424 {
 425         struct pci_controller *controller = PCI_CONTROLLER(dev);
 426         unsigned long offset = 0;
 427         int i;
 428
 429         for (i = 0; i < controller->windows; i++) {
 430                 struct pci_window *window = &controller->window[i];
 431                 if (!(window->resource.flags & res->flags))
 432                         continue;
 433                 if (window->resource.start - window->offset > region->start)
 434                         continue;
 435                 if (window->resource.end - window->offset < region->end)
 436                         continue;
 437                 offset = window->offset;
 438                 break;
 439         }
 440
 441         res->start = region->start + offset;
 442         res->end = region->end + offset;
 443 }
 444 EXPORT_SYMBOL(pcibios_bus_to_resource);
 445
 446 static int __devinit is_valid_resource(struct pci_dev *dev, int idx)
 447 {
 448         unsigned int i, type_mask = IORESOURCE_IO | IORESOURCE_MEM;
 449         struct resource *devr = &dev->resource[idx], *busr;
 450
 451         if (!dev->bus)
 452                 return 0;
 453
 454         pci_bus_for_each_resource(dev->bus, busr, i) {
 455                 if (!busr || ((busr->flags ^ devr->flags) & type_mask))
 456                         continue;
 457                 if ((devr->start) && (devr->start >= busr->start) &&
 458                                 (devr->end <= busr->end))
 459                         return 1;
 460         }
 461         return 0;
 462 }
 463
 464 static void __devinit
 465 pcibios_fixup_resources(struct pci_dev *dev, int start, int limit)
 466 {
 467         struct pci_bus_region region;
 468         int i;
 469
 470         for (i = start; i < limit; i++) {
 471                 if (!dev->resource[i].flags)
 472                         continue;
 473                 region.start = dev->resource[i].start;
 474                 region.end = dev->resource[i].end;
 475                 pcibios_bus_to_resource(dev, &dev->resource[i], &region);
 476                 if ((is_valid_resource(dev, i)))
 477                         pci_claim_resource(dev, i);
 478         }
 479 }
 480
 481 void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
 482 {
 483         pcibios_fixup_resources(dev, 0, PCI_BRIDGE_RESOURCES);
 484 }
 485 EXPORT_SYMBOL_GPL(pcibios_fixup_device_resources);
 486
 487 static void __devinit pcibios_fixup_bridge_resources(struct pci_dev *dev)
 488 {
 489         pcibios_fixup_resources(dev, PCI_BRIDGE_RESOURCES, PCI_NUM_RESOURCES);
 490 }
 491
 492 /*
 493  *  Called after each bus is probed, but before its children are examined.
 494  */
 495 void __devinit
 496 pcibios_fixup_bus (struct pci_bus *b)
 497 {
 498         struct pci_dev *dev;
 499
 500         if (b->self) {
 501                 pci_read_bridge_bases(b);
 502                 pcibios_fixup_bridge_resources(b->self);
 503         }
 504         list_for_each_entry(dev, &b->devices, bus_list)
 505                 pcibios_fixup_device_resources(dev);
 506         platform_pci_fixup_bus(b);
 507 }
 508
 509 void pcibios_set_master (struct pci_dev *dev)
 510 {
 511         /* No special bus mastering setup handling */
 512 }
 513
 514 void __devinit
 515 pcibios_update_irq (struct pci_dev *dev, int irq)
 516 {
 517         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 518
 519         /* ??? FIXME -- record old value for shutdown.  */
 520 }
 521
 522 int
 523 pcibios_enable_device (struct pci_dev *dev, int mask)
 524 {
 525         int ret;
 526
 527         ret = pci_enable_resources(dev, mask);
 528         if (ret < 0)
 529                 return ret;
 530
 531         if (!dev->msi_enabled)
 532                 return acpi_pci_irq_enable(dev);
 533         return 0;
 534 }
 535
 536 void
 537 pcibios_disable_device (struct pci_dev *dev)
 538 {
 539         BUG_ON(atomic_read(&dev->enable_cnt));
 540         if (!dev->msi_enabled)
 541                 acpi_pci_irq_disable(dev);
 542 }
 543
 544 resource_size_t
 545 pcibios_align_resource (void *data, const struct resource *res,
 546                         resource_size_t size, resource_size_t align)
 547 {
 548         return res->start;
 549 }
 550
 551 /*
 552  * PCI BIOS setup, always defaults to SAL interface
 553  */
 554 char * __init
 555 pcibios_setup (char *str)
 556 {
 557         return str;
 558 }
 559
 560 int
 561 pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
 562                      enum pci_mmap_state mmap_state, int write_combine)
 563 {
 564         unsigned long size = vma->vm_end - vma->vm_start;
 565         pgprot_t prot;
 566
 567         /*
 568          * I/O space cannot be accessed via normal processor loads and
 569          * stores on this platform.
 570          */
 571         if (mmap_state == pci_mmap_io)
 572                 /*
 573                  * XXX we could relax this for I/O spaces for which ACPI
 574                  * indicates that the space is 1-to-1 mapped.  But at the
 575                  * moment, we don't support multiple PCI address spaces and
 576                  * the legacy I/O space is not 1-to-1 mapped, so this is moot.
 577                  */
 578                 return -EINVAL;
 579
 580         if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size))
 581                 return -EINVAL;
 582
 583         prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size,
 584                                     vma->vm_page_prot);
 585
 586         /*
 587          * If the user requested WC, the kernel uses UC or WC for this region,
 588          * and the chipset supports WC, we can use WC. Otherwise, we have to
 589          * use the same attribute the kernel uses.
 590          */
 591         if (write_combine &&
 592             ((pgprot_val(prot) & _PAGE_MA_MASK) == _PAGE_MA_UC ||
 593              (pgprot_val(prot) & _PAGE_MA_MASK) == _PAGE_MA_WC) &&
 594             efi_range_is_wc(vma->vm_start, vma->vm_end - vma->vm_start))
 595                 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
 596         else
 597                 vma->vm_page_prot = prot;
 598
 599         if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 600                              vma->vm_end - vma->vm_start, vma->vm_page_prot))
 601                 return -EAGAIN;
 602
 603         return 0;
 604 }
 605
 606 /**
 607  * ia64_pci_get_legacy_mem - generic legacy mem routine
 608  * @bus: bus to get legacy memory base address for
 609  *
 610  * Find the base of legacy memory for @bus.  This is typically the first
 611  * megabyte of bus address space for @bus or is simply 0 on platforms whose
 612  * chipsets support legacy I/O and memory routing.  Returns the base address
 613  * or an error pointer if an error occurred.
 614  *
 615  * This is the ia64 generic version of this routine.  Other platforms
 616  * are free to override it with a machine vector.
 617  */
 618 char *ia64_pci_get_legacy_mem(struct pci_bus *bus)
 619 {
 620         return (char *)__IA64_UNCACHED_OFFSET;
 621 }
 622
 623 /**
 624  * pci_mmap_legacy_page_range - map legacy memory space to userland
 625  * @bus: bus whose legacy space we're mapping
 626  * @vma: vma passed in by mmap
 627  *
 628  * Map legacy memory space for this device back to userspace using a machine
 629  * vector to get the base address.
 630  */
 631 int
 632 pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma,
 633                            enum pci_mmap_state mmap_state)
 634 {
 635         unsigned long size = vma->vm_end - vma->vm_start;
 636         pgprot_t prot;
 637         char *addr;
 638
 639         /* We only support mmap'ing of legacy memory space */
 640         if (mmap_state != pci_mmap_mem)
 641                 return -ENOSYS;
 642
 643         /*
 644          * Avoid attribute aliasing.  See Documentation/ia64/aliasing.txt
 645          * for more details.
 646          */
 647         if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size))
 648                 return -EINVAL;
 649         prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size,
 650                                     vma->vm_page_prot);
 651
 652         addr = pci_get_legacy_mem(bus);
 653         if (IS_ERR(addr))
 654                 return PTR_ERR(addr);
 655
 656         vma->vm_pgoff += (unsigned long)addr >> PAGE_SHIFT;
 657         vma->vm_page_prot = prot;
 658
 659         if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 660                             size, vma->vm_page_prot))
 661                 return -EAGAIN;
 662
 663         return 0;
 664 }
 665
 666 /**
 667  * ia64_pci_legacy_read - read from legacy I/O space
 668  * @bus: bus to read
 669  * @port: legacy port value
 670  * @val: caller allocated storage for returned value
 671  * @size: number of bytes to read
 672  *
 673  * Simply reads @size bytes from @port and puts the result in @val.
 674  *
 675  * Again, this (and the write routine) are generic versions that can be
 676  * overridden by the platform.  This is necessary on platforms that don't
 677  * support legacy I/O routing or that hard fail on legacy I/O timeouts.
 678  */
 679 int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
 680 {
 681         int ret = size;
 682
 683         switch (size) {
 684         case 1:
 685                 *val = inb(port);
 686                 break;
 687         case 2:
 688                 *val = inw(port);
 689                 break;
 690         case 4:
 691                 *val = inl(port);
 692                 break;
 693         default:
 694                 ret = -EINVAL;
 695                 break;
 696         }
 697
 698         return ret;
 699 }
 700
 701 /**
 702  * ia64_pci_legacy_write - perform a legacy I/O write
 703  * @bus: bus pointer
 704  * @port: port to write
 705  * @val: value to write
 706  * @size: number of bytes to write from @val
 707  *
 708  * Simply writes @size bytes of @val to @port.
 709  */
 710 int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
 711 {
 712         int ret = size;
 713
 714         switch (size) {
 715         case 1:
 716                 outb(val, port);
 717                 break;
 718         case 2:
 719                 outw(val, port);
 720                 break;
 721         case 4:
 722                 outl(val, port);
 723                 break;
 724         default:
 725                 ret = -EINVAL;
 726                 break;
 727         }
 728
 729         return ret;
 730 }
 731
 732 /**
 733  * set_pci_cacheline_size - determine cacheline size for PCI devices
 734  *
 735  * We want to use the line-size of the outer-most cache.  We assume
 736  * that this line-size is the same for all CPUs.
 737  *
 738  * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
 739  */
 740 static void __init set_pci_dfl_cacheline_size(void)
 741 {
 742         unsigned long levels, unique_caches;
 743         long status;
 744         pal_cache_config_info_t cci;
 745
 746         status = ia64_pal_cache_summary(&levels, &unique_caches);
 747         if (status != 0) {
 748                 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed "
 749                         "(status=%ld)\n", __func__, status);
 750                 return;
 751         }
 752
 753         status = ia64_pal_cache_config_info(levels - 1,
 754                                 /* cache_type (data_or_unified)= */ 2, &cci);
 755         if (status != 0) {
 756                 printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed "
 757                         "(status=%ld)\n", __func__, status);
 758                 return;
 759         }
 760         pci_dfl_cache_line_size = (1 << cci.pcci_line_size) / 4;
 761 }
 762
 763 u64 ia64_dma_get_required_mask(struct device *dev)
 764 {
 765         u32 low_totalram = ((max_pfn - 1) << PAGE_SHIFT);
 766         u32 high_totalram = ((max_pfn - 1) >> (32 - PAGE_SHIFT));
 767         u64 mask;
 768
 769         if (!high_totalram) {
 770                 /* convert to mask just covering totalram */
 771                 low_totalram = (1 << (fls(low_totalram) - 1));
 772                 low_totalram += low_totalram - 1;
 773                 mask = low_totalram;
 774         } else {
 775                 high_totalram = (1 << (fls(high_totalram) - 1));
 776                 high_totalram += high_totalram - 1;
 777                 mask = (((u64)high_totalram) << 32) + 0xffffffff;
 778         }
 779         return mask;
 780 }
 781 EXPORT_SYMBOL_GPL(ia64_dma_get_required_mask);
 782
 783 u64 dma_get_required_mask(struct device *dev)
 784 {
 785         return platform_dma_get_required_mask(dev);
 786 }
 787 EXPORT_SYMBOL_GPL(dma_get_required_mask);
 788
 789 static int __init pcibios_init(void)
 790 {
 791         set_pci_dfl_cacheline_size();
 792         return 0;
 793 }
 794
 795 subsys_initcall(pcibios_init);