spi-topcliff-pch: Fix issue for transmitting over 4KByte
[zen-stable.git] / arch / ia64 / sn / kernel / sn2 / cache.c
blob2862cb33026d16dd8bbc46a2d54cb793314acf96
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2001-2003, 2006 Silicon Graphics, Inc. All rights reserved.
8 */
9 #include <linux/module.h>
10 #include <asm/pgalloc.h>
11 #include <asm/sn/arch.h>
13 /**
14 * sn_flush_all_caches - flush a range of address from all caches (incl. L4)
15 * @flush_addr: identity mapped region 7 address to start flushing
16 * @bytes: number of bytes to flush
18 * Flush a range of addresses from all caches including L4.
19 * All addresses fully or partially contained within
20 * @flush_addr to @flush_addr + @bytes are flushed
21 * from all caches.
23 void
24 sn_flush_all_caches(long flush_addr, long bytes)
26 unsigned long addr = flush_addr;
28 /* SHub1 requires a cached address */
29 if (is_shub1() && (addr & RGN_BITS) == RGN_BASE(RGN_UNCACHED))
30 addr = (addr - RGN_BASE(RGN_UNCACHED)) + RGN_BASE(RGN_KERNEL);
32 flush_icache_range(addr, addr + bytes);
34 * The last call may have returned before the caches
35 * were actually flushed, so we call it again to make
36 * sure.
38 flush_icache_range(addr, addr + bytes);
39 mb();
41 EXPORT_SYMBOL(sn_flush_all_caches);