arch/m68k/include/asm/pgtable_mm.h

   1 #ifndef _M68K_PGTABLE_H
   2 #define _M68K_PGTABLE_H
   3
   4 #include <asm-generic/4level-fixup.h>
   5
   6 #include <asm/setup.h>
   7
   8 #ifndef __ASSEMBLY__
   9 #include <asm/processor.h>
  10 #include <linux/sched.h>
  11 #include <linux/threads.h>
  12
  13 /*
  14  * This file contains the functions and defines necessary to modify and use
  15  * the m68k page table tree.
  16  */
  17
  18 #include <asm/virtconvert.h>
  19
  20 /* Certain architectures need to do special things when pte's
  21  * within a page table are directly modified.  Thus, the following
  22  * hook is made available.
  23  */
  24 #define set_pte(pteptr, pteval)                                 \
  25         do{                                                     \
  26                 *(pteptr) = (pteval);                           \
  27         } while(0)
  28 #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
  29
  30
  31 /* PMD_SHIFT determines the size of the area a second-level page table can map */
  32 #ifdef CONFIG_SUN3
  33 #define PMD_SHIFT       17
  34 #else
  35 #define PMD_SHIFT       22
  36 #endif
  37 #define PMD_SIZE        (1UL << PMD_SHIFT)
  38 #define PMD_MASK        (~(PMD_SIZE-1))
  39
  40 /* PGDIR_SHIFT determines what a third-level page table entry can map */
  41 #ifdef CONFIG_SUN3
  42 #define PGDIR_SHIFT     17
  43 #elif defined(CONFIG_COLDFIRE)
  44 #define PGDIR_SHIFT     22
  45 #else
  46 #define PGDIR_SHIFT     25
  47 #endif
  48 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
  49 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
  50
  51 /*
  52  * entries per page directory level: the m68k is configured as three-level,
  53  * so we do have PMD level physically.
  54  */
  55 #ifdef CONFIG_SUN3
  56 #define PTRS_PER_PTE   16
  57 #define PTRS_PER_PMD   1
  58 #define PTRS_PER_PGD   2048
  59 #elif defined(CONFIG_COLDFIRE)
  60 #define PTRS_PER_PTE    512
  61 #define PTRS_PER_PMD    1
  62 #define PTRS_PER_PGD    1024
  63 #else
  64 #define PTRS_PER_PTE    1024
  65 #define PTRS_PER_PMD    8
  66 #define PTRS_PER_PGD    128
  67 #endif
  68 #define USER_PTRS_PER_PGD       (TASK_SIZE/PGDIR_SIZE)
  69 #define FIRST_USER_ADDRESS      0
  70
  71 /* Virtual address region for use by kernel_map() */
  72 #ifdef CONFIG_SUN3
  73 #define KMAP_START     0x0DC00000
  74 #define KMAP_END       0x0E000000
  75 #elif defined(CONFIG_COLDFIRE)
  76 #define KMAP_START      0xe0000000
  77 #define KMAP_END        0xf0000000
  78 #else
  79 #define KMAP_START      0xd0000000
  80 #define KMAP_END        0xf0000000
  81 #endif
  82
  83 #ifdef CONFIG_SUN3
  84 extern unsigned long m68k_vmalloc_end;
  85 #define VMALLOC_START 0x0f800000
  86 #define VMALLOC_END m68k_vmalloc_end
  87 #elif defined(CONFIG_COLDFIRE)
  88 #define VMALLOC_START   0xd0000000
  89 #define VMALLOC_END     0xe0000000
  90 #else
  91 /* Just any arbitrary offset to the start of the vmalloc VM area: the
  92  * current 8MB value just means that there will be a 8MB "hole" after the
  93  * physical memory until the kernel virtual memory starts.  That means that
  94  * any out-of-bounds memory accesses will hopefully be caught.
  95  * The vmalloc() routines leaves a hole of 4kB between each vmalloced
  96  * area for the same reason. ;)
  97  */
  98 #define VMALLOC_OFFSET  (8*1024*1024)
  99 #define VMALLOC_START (((unsigned long) high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
 100 #define VMALLOC_END KMAP_START
 101 #endif
 102
 103 /* zero page used for uninitialized stuff */
 104 extern void *empty_zero_page;
 105
 106 /*
 107  * ZERO_PAGE is a global shared page that is always zero: used
 108  * for zero-mapped memory areas etc..
 109  */
 110 #define ZERO_PAGE(vaddr)        (virt_to_page(empty_zero_page))
 111
 112 /* number of bits that fit into a memory pointer */
 113 #define BITS_PER_PTR                    (8*sizeof(unsigned long))
 114
 115 /* to align the pointer to a pointer address */
 116 #define PTR_MASK                        (~(sizeof(void*)-1))
 117
 118 /* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */
 119 /* 64-bit machines, beware!  SRB. */
 120 #define SIZEOF_PTR_LOG2                        2
 121
 122 extern void kernel_set_cachemode(void *addr, unsigned long size, int cmode);
 123
 124 /*
 125  * The m68k doesn't have any external MMU info: the kernel page
 126  * tables contain all the necessary information.  The Sun3 does, but
 127  * they are updated on demand.
 128  */
 129 static inline void update_mmu_cache(struct vm_area_struct *vma,
 130                                     unsigned long address, pte_t *ptep)
 131 {
 132 }
 133
 134 #endif /* !__ASSEMBLY__ */
 135
 136 #define kern_addr_valid(addr)   (1)
 137
 138 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
 139                 remap_pfn_range(vma, vaddr, pfn, size, prot)
 140
 141 /* MMU-specific headers */
 142
 143 #ifdef CONFIG_SUN3
 144 #include <asm/sun3_pgtable.h>
 145 #elif defined(CONFIG_COLDFIRE)
 146 #include <asm/mcf_pgtable.h>
 147 #else
 148 #include <asm/motorola_pgtable.h>
 149 #endif
 150
 151 #ifndef __ASSEMBLY__
 152 /*
 153  * Macro to mark a page protection value as "uncacheable".
 154  */
 155 #ifdef CONFIG_COLDFIRE
 156 # define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | CF_PAGE_NOCACHE))
 157 #else
 158 #ifdef SUN3_PAGE_NOCACHE
 159 # define __SUN3_PAGE_NOCACHE    SUN3_PAGE_NOCACHE
 160 #else
 161 # define __SUN3_PAGE_NOCACHE    0
 162 #endif
 163 #define pgprot_noncached(prot)                                                  \
 164         (MMU_IS_SUN3                                                            \
 165          ? (__pgprot(pgprot_val(prot) | __SUN3_PAGE_NOCACHE))                   \
 166          : ((MMU_IS_851 || MMU_IS_030)                                          \
 167             ? (__pgprot(pgprot_val(prot) | _PAGE_NOCACHE030))                   \
 168             : (MMU_IS_040 || MMU_IS_060)                                        \
 169             ? (__pgprot((pgprot_val(prot) & _CACHEMASK040) | _PAGE_NOCACHE_S))  \
 170             : (prot)))
 171
 172 #endif /* CONFIG_COLDFIRE */
 173 #include <asm-generic/pgtable.h>
 174 #endif /* !__ASSEMBLY__ */
 175
 176 /*
 177  * No page table caches to initialise
 178  */
 179 #define pgtable_cache_init()    do { } while (0)
 180
 181 #define check_pgt_cache()       do { } while (0)
 182
 183 #endif /* _M68K_PGTABLE_H */