arch/mips/alchemy/common/time.c

   1 /*
   2  * Copyright (C) 2008-2009 Manuel Lauss <manuel.lauss@gmail.com>
   3  *
   4  * Previous incarnations were:
   5  * Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com>
   6  * Copied and modified Carsten Langgaard's time.c
   7  *
   8  * Carsten Langgaard, carstenl@mips.com
   9  * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
  10  *
  11  * ########################################################################
  12  *
  13  *  This program is free software; you can distribute it and/or modify it
  14  *  under the terms of the GNU General Public License (Version 2) as
  15  *  published by the Free Software Foundation.
  16  *
  17  *  This program is distributed in the hope it will be useful, but WITHOUT
  18  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  20  *  for more details.
  21  *
  22  *  You should have received a copy of the GNU General Public License along
  23  *  with this program; if not, write to the Free Software Foundation, Inc.,
  24  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  25  *
  26  * ########################################################################
  27  *
  28  * Clocksource/event using the 32.768kHz-clocked Counter1 ('RTC' in the
  29  * databooks).  Firmware/Board init code must enable the counters in the
  30  * counter control register, otherwise the CP0 counter clocksource/event
  31  * will be installed instead (and use of 'wait' instruction is prohibited).
  32  */
  33
  34 #include <linux/clockchips.h>
  35 #include <linux/clocksource.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/spinlock.h>
  38
  39 #include <asm/processor.h>
  40 #include <asm/time.h>
  41 #include <asm/mach-au1x00/au1000.h>
  42
  43 /* 32kHz clock enabled and detected */
  44 #define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S)
  45
  46 static cycle_t au1x_counter1_read(struct clocksource *cs)
  47 {
  48         return au_readl(SYS_RTCREAD);
  49 }
  50
  51 static struct clocksource au1x_counter1_clocksource = {
  52         .name           = "alchemy-counter1",
  53         .read           = au1x_counter1_read,
  54         .mask           = CLOCKSOURCE_MASK(32),
  55         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  56         .rating         = 100,
  57 };
  58
  59 static int au1x_rtcmatch2_set_next_event(unsigned long delta,
  60                                          struct clock_event_device *cd)
  61 {
  62         delta += au_readl(SYS_RTCREAD);
  63         /* wait for register access */
  64         while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M21)
  65                 ;
  66         au_writel(delta, SYS_RTCMATCH2);
  67         au_sync();
  68
  69         return 0;
  70 }
  71
  72 static void au1x_rtcmatch2_set_mode(enum clock_event_mode mode,
  73                                     struct clock_event_device *cd)
  74 {
  75 }
  76
  77 static irqreturn_t au1x_rtcmatch2_irq(int irq, void *dev_id)
  78 {
  79         struct clock_event_device *cd = dev_id;
  80         cd->event_handler(cd);
  81         return IRQ_HANDLED;
  82 }
  83
  84 static struct clock_event_device au1x_rtcmatch2_clockdev = {
  85         .name           = "rtcmatch2",
  86         .features       = CLOCK_EVT_FEAT_ONESHOT,
  87         .rating         = 100,
  88         .set_next_event = au1x_rtcmatch2_set_next_event,
  89         .set_mode       = au1x_rtcmatch2_set_mode,
  90         .cpumask        = cpu_all_mask,
  91 };
  92
  93 static struct irqaction au1x_rtcmatch2_irqaction = {
  94         .handler        = au1x_rtcmatch2_irq,
  95         .flags          = IRQF_TIMER,
  96         .name           = "timer",
  97         .dev_id         = &au1x_rtcmatch2_clockdev,
  98 };
  99
 100 static int __init alchemy_time_init(unsigned int m2int)
 101 {
 102         struct clock_event_device *cd = &au1x_rtcmatch2_clockdev;
 103         unsigned long t;
 104
 105         au1x_rtcmatch2_clockdev.irq = m2int;
 106
 107         /* Check if firmware (YAMON, ...) has enabled 32kHz and clock
 108          * has been detected.  If so install the rtcmatch2 clocksource,
 109          * otherwise don't bother.  Note that both bits being set is by
 110          * no means a definite guarantee that the counters actually work
 111          * (the 32S bit seems to be stuck set to 1 once a single clock-
 112          * edge is detected, hence the timeouts).
 113          */
 114         if (CNTR_OK != (au_readl(SYS_COUNTER_CNTRL) & CNTR_OK))
 115                 goto cntr_err;
 116
 117         /*
 118          * setup counter 1 (RTC) to tick at full speed
 119          */
 120         t = 0xffffff;
 121         while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S) && --t)
 122                 asm volatile ("nop");
 123         if (!t)
 124                 goto cntr_err;
 125
 126         au_writel(0, SYS_RTCTRIM);      /* 32.768 kHz */
 127         au_sync();
 128
 129         t = 0xffffff;
 130         while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && --t)
 131                 asm volatile ("nop");
 132         if (!t)
 133                 goto cntr_err;
 134         au_writel(0, SYS_RTCWRITE);
 135         au_sync();
 136
 137         t = 0xffffff;
 138         while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && --t)
 139                 asm volatile ("nop");
 140         if (!t)
 141                 goto cntr_err;
 142
 143         /* register counter1 clocksource and event device */
 144         clocksource_register_hz(&au1x_counter1_clocksource, 32768);
 145
 146         cd->shift = 32;
 147         cd->mult = div_sc(32768, NSEC_PER_SEC, cd->shift);
 148         cd->max_delta_ns = clockevent_delta2ns(0xffffffff, cd);
 149         cd->min_delta_ns = clockevent_delta2ns(9, cd);  /* ~0.28ms */
 150         clockevents_register_device(cd);
 151         setup_irq(m2int, &au1x_rtcmatch2_irqaction);
 152
 153         printk(KERN_INFO "Alchemy clocksource installed\n");
 154
 155         return 0;
 156
 157 cntr_err:
 158         return -1;
 159 }
 160
 161 static void __init alchemy_setup_c0timer(void)
 162 {
 163         /*
 164          * MIPS kernel assigns 'au1k_wait' to 'cpu_wait' before this
 165          * function is called.  Because the Alchemy counters are unusable
 166          * the C0 timekeeping code is installed and use of the 'wait'
 167          * instruction must be prohibited, which is done most easily by
 168          * assigning NULL to cpu_wait.
 169          */
 170         cpu_wait = NULL;
 171         r4k_clockevent_init();
 172         init_r4k_clocksource();
 173 }
 174
 175 static int alchemy_m2inttab[] __initdata = {
 176         AU1000_RTC_MATCH2_INT,
 177         AU1500_RTC_MATCH2_INT,
 178         AU1100_RTC_MATCH2_INT,
 179         AU1550_RTC_MATCH2_INT,
 180         AU1200_RTC_MATCH2_INT,
 181         AU1300_RTC_MATCH2_INT,
 182 };
 183
 184 void __init plat_time_init(void)
 185 {
 186         int t;
 187
 188         t = alchemy_get_cputype();
 189         if (t == ALCHEMY_CPU_UNKNOWN)
 190                 alchemy_setup_c0timer();
 191         else if (alchemy_time_init(alchemy_m2inttab[t]))
 192                 alchemy_setup_c0timer();
 193 }