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spi-topcliff-pch: Fix issue for transmitting over 4KByte
[zen-stable.git] / arch / sparc / kernel / traps_64.c
blob0cbdaa41cd1eb8fa19f4597b834da3c9a489b4ee
1 /* arch/sparc64/kernel/traps.c
2 *
3 * Copyright (C) 1995,1997,2008,2009 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1997,1999,2000 Jakub Jelinek (jakub@redhat.com)
5 */
6
7 /*
8 * I like traps on v9, :))))
9 */
10
11 #include <linux/module.h>
12 #include <linux/sched.h>
13 #include <linux/linkage.h>
14 #include <linux/kernel.h>
15 #include <linux/signal.h>
16 #include <linux/smp.h>
17 #include <linux/mm.h>
18 #include <linux/init.h>
19 #include <linux/kdebug.h>
20 #include <linux/ftrace.h>
21 #include <linux/gfp.h>
22
23 #include <asm/smp.h>
24 #include <asm/delay.h>
25 #include <asm/system.h>
26 #include <asm/ptrace.h>
27 #include <asm/oplib.h>
28 #include <asm/page.h>
29 #include <asm/pgtable.h>
30 #include <asm/unistd.h>
31 #include <asm/uaccess.h>
32 #include <asm/fpumacro.h>
33 #include <asm/lsu.h>
34 #include <asm/dcu.h>
35 #include <asm/estate.h>
36 #include <asm/chafsr.h>
37 #include <asm/sfafsr.h>
38 #include <asm/psrcompat.h>
39 #include <asm/processor.h>
40 #include <asm/timer.h>
41 #include <asm/head.h>
42 #include <asm/prom.h>
43 #include <asm/memctrl.h>
44
45 #include "entry.h"
46 #include "kstack.h"
47
48 /* When an irrecoverable trap occurs at tl > 0, the trap entry
49 * code logs the trap state registers at every level in the trap
50 * stack. It is found at (pt_regs + sizeof(pt_regs)) and the layout
51 * is as follows:
52 */
53 struct tl1_traplog {
54 struct {
55 unsigned long tstate;
56 unsigned long tpc;
57 unsigned long tnpc;
58 unsigned long tt;
59 } trapstack[4];
60 unsigned long tl;
61 };
62
63 static void dump_tl1_traplog(struct tl1_traplog *p)
64 {
65 int i, limit;
66
67 printk(KERN_EMERG "TRAPLOG: Error at trap level 0x%lx, "
68 "dumping track stack.\n", p->tl);
69
70 limit = (tlb_type == hypervisor) ? 2 : 4;
71 for (i = 0; i < limit; i++) {
72 printk(KERN_EMERG
73 "TRAPLOG: Trap level %d TSTATE[%016lx] TPC[%016lx] "
74 "TNPC[%016lx] TT[%lx]\n",
75 i + 1,
76 p->trapstack[i].tstate, p->trapstack[i].tpc,
77 p->trapstack[i].tnpc, p->trapstack[i].tt);
78 printk("TRAPLOG: TPC<%pS>\n", (void *) p->trapstack[i].tpc);
79 }
80 }
81
82 void bad_trap(struct pt_regs *regs, long lvl)
83 {
84 char buffer[32];
85 siginfo_t info;
86
87 if (notify_die(DIE_TRAP, "bad trap", regs,
88 0, lvl, SIGTRAP) == NOTIFY_STOP)
89 return;
90
91 if (lvl < 0x100) {
92 sprintf(buffer, "Bad hw trap %lx at tl0\n", lvl);
93 die_if_kernel(buffer, regs);
94 }
95
96 lvl -= 0x100;
97 if (regs->tstate & TSTATE_PRIV) {
98 sprintf(buffer, "Kernel bad sw trap %lx", lvl);
99 die_if_kernel(buffer, regs);
100 }
101 if (test_thread_flag(TIF_32BIT)) {
102 regs->tpc &= 0xffffffff;
103 regs->tnpc &= 0xffffffff;
104 }
105 info.si_signo = SIGILL;
106 info.si_errno = 0;
107 info.si_code = ILL_ILLTRP;
108 info.si_addr = (void __user *)regs->tpc;
109 info.si_trapno = lvl;
110 force_sig_info(SIGILL, &info, current);
111 }
112
113 void bad_trap_tl1(struct pt_regs *regs, long lvl)
114 {
115 char buffer[32];
116
117 if (notify_die(DIE_TRAP_TL1, "bad trap tl1", regs,
118 0, lvl, SIGTRAP) == NOTIFY_STOP)
119 return;
120
121 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
122
123 sprintf (buffer, "Bad trap %lx at tl>0", lvl);
124 die_if_kernel (buffer, regs);
125 }
126
127 #ifdef CONFIG_DEBUG_BUGVERBOSE
128 void do_BUG(const char *file, int line)
129 {
130 bust_spinlocks(1);
131 printk("kernel BUG at %s:%d!\n", file, line);
132 }
133 EXPORT_SYMBOL(do_BUG);
134 #endif
135
136 static DEFINE_SPINLOCK(dimm_handler_lock);
137 static dimm_printer_t dimm_handler;
138
139 static int sprintf_dimm(int synd_code, unsigned long paddr, char *buf, int buflen)
140 {
141 unsigned long flags;
142 int ret = -ENODEV;
143
144 spin_lock_irqsave(&dimm_handler_lock, flags);
145 if (dimm_handler) {
146 ret = dimm_handler(synd_code, paddr, buf, buflen);
147 } else if (tlb_type == spitfire) {
148 if (prom_getunumber(synd_code, paddr, buf, buflen) == -1)
149 ret = -EINVAL;
150 else
151 ret = 0;
152 } else
153 ret = -ENODEV;
154 spin_unlock_irqrestore(&dimm_handler_lock, flags);
155
156 return ret;
157 }
158
159 int register_dimm_printer(dimm_printer_t func)
160 {
161 unsigned long flags;
162 int ret = 0;
163
164 spin_lock_irqsave(&dimm_handler_lock, flags);
165 if (!dimm_handler)
166 dimm_handler = func;
167 else
168 ret = -EEXIST;
169 spin_unlock_irqrestore(&dimm_handler_lock, flags);
170
171 return ret;
172 }
173 EXPORT_SYMBOL_GPL(register_dimm_printer);
174
175 void unregister_dimm_printer(dimm_printer_t func)
176 {
177 unsigned long flags;
178
179 spin_lock_irqsave(&dimm_handler_lock, flags);
180 if (dimm_handler == func)
181 dimm_handler = NULL;
182 spin_unlock_irqrestore(&dimm_handler_lock, flags);
183 }
184 EXPORT_SYMBOL_GPL(unregister_dimm_printer);
185
186 void spitfire_insn_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
187 {
188 siginfo_t info;
189
190 if (notify_die(DIE_TRAP, "instruction access exception", regs,
191 0, 0x8, SIGTRAP) == NOTIFY_STOP)
192 return;
193
194 if (regs->tstate & TSTATE_PRIV) {
195 printk("spitfire_insn_access_exception: SFSR[%016lx] "
196 "SFAR[%016lx], going.\n", sfsr, sfar);
197 die_if_kernel("Iax", regs);
198 }
199 if (test_thread_flag(TIF_32BIT)) {
200 regs->tpc &= 0xffffffff;
201 regs->tnpc &= 0xffffffff;
202 }
203 info.si_signo = SIGSEGV;
204 info.si_errno = 0;
205 info.si_code = SEGV_MAPERR;
206 info.si_addr = (void __user *)regs->tpc;
207 info.si_trapno = 0;
208 force_sig_info(SIGSEGV, &info, current);
209 }
210
211 void spitfire_insn_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
212 {
213 if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
214 0, 0x8, SIGTRAP) == NOTIFY_STOP)
215 return;
216
217 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
218 spitfire_insn_access_exception(regs, sfsr, sfar);
219 }
220
221 void sun4v_insn_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
222 {
223 unsigned short type = (type_ctx >> 16);
224 unsigned short ctx = (type_ctx & 0xffff);
225 siginfo_t info;
226
227 if (notify_die(DIE_TRAP, "instruction access exception", regs,
228 0, 0x8, SIGTRAP) == NOTIFY_STOP)
229 return;
230
231 if (regs->tstate & TSTATE_PRIV) {
232 printk("sun4v_insn_access_exception: ADDR[%016lx] "
233 "CTX[%04x] TYPE[%04x], going.\n",
234 addr, ctx, type);
235 die_if_kernel("Iax", regs);
236 }
237
238 if (test_thread_flag(TIF_32BIT)) {
239 regs->tpc &= 0xffffffff;
240 regs->tnpc &= 0xffffffff;
241 }
242 info.si_signo = SIGSEGV;
243 info.si_errno = 0;
244 info.si_code = SEGV_MAPERR;
245 info.si_addr = (void __user *) addr;
246 info.si_trapno = 0;
247 force_sig_info(SIGSEGV, &info, current);
248 }
249
250 void sun4v_insn_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
251 {
252 if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
253 0, 0x8, SIGTRAP) == NOTIFY_STOP)
254 return;
255
256 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
257 sun4v_insn_access_exception(regs, addr, type_ctx);
258 }
259
260 void spitfire_data_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
261 {
262 siginfo_t info;
263
264 if (notify_die(DIE_TRAP, "data access exception", regs,
265 0, 0x30, SIGTRAP) == NOTIFY_STOP)
266 return;
267
268 if (regs->tstate & TSTATE_PRIV) {
269 /* Test if this comes from uaccess places. */
270 const struct exception_table_entry *entry;
271
272 entry = search_exception_tables(regs->tpc);
273 if (entry) {
274 /* Ouch, somebody is trying VM hole tricks on us... */
275 #ifdef DEBUG_EXCEPTIONS
276 printk("Exception: PC<%016lx> faddr<UNKNOWN>\n", regs->tpc);
277 printk("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
278 regs->tpc, entry->fixup);
279 #endif
280 regs->tpc = entry->fixup;
281 regs->tnpc = regs->tpc + 4;
282 return;
283 }
284 /* Shit... */
285 printk("spitfire_data_access_exception: SFSR[%016lx] "
286 "SFAR[%016lx], going.\n", sfsr, sfar);
287 die_if_kernel("Dax", regs);
288 }
289
290 info.si_signo = SIGSEGV;
291 info.si_errno = 0;
292 info.si_code = SEGV_MAPERR;
293 info.si_addr = (void __user *)sfar;
294 info.si_trapno = 0;
295 force_sig_info(SIGSEGV, &info, current);
296 }
297
298 void spitfire_data_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
299 {
300 if (notify_die(DIE_TRAP_TL1, "data access exception tl1", regs,
301 0, 0x30, SIGTRAP) == NOTIFY_STOP)
302 return;
303
304 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
305 spitfire_data_access_exception(regs, sfsr, sfar);
306 }
307
308 void sun4v_data_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
309 {
310 unsigned short type = (type_ctx >> 16);
311 unsigned short ctx = (type_ctx & 0xffff);
312 siginfo_t info;
313
314 if (notify_die(DIE_TRAP, "data access exception", regs,
315 0, 0x8, SIGTRAP) == NOTIFY_STOP)
316 return;
317
318 if (regs->tstate & TSTATE_PRIV) {
319 /* Test if this comes from uaccess places. */
320 const struct exception_table_entry *entry;
321
322 entry = search_exception_tables(regs->tpc);
323 if (entry) {
324 /* Ouch, somebody is trying VM hole tricks on us... */
325 #ifdef DEBUG_EXCEPTIONS
326 printk("Exception: PC<%016lx> faddr<UNKNOWN>\n", regs->tpc);
327 printk("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
328 regs->tpc, entry->fixup);
329 #endif
330 regs->tpc = entry->fixup;
331 regs->tnpc = regs->tpc + 4;
332 return;
333 }
334 printk("sun4v_data_access_exception: ADDR[%016lx] "
335 "CTX[%04x] TYPE[%04x], going.\n",
336 addr, ctx, type);
337 die_if_kernel("Dax", regs);
338 }
339
340 if (test_thread_flag(TIF_32BIT)) {
341 regs->tpc &= 0xffffffff;
342 regs->tnpc &= 0xffffffff;
343 }
344 info.si_signo = SIGSEGV;
345 info.si_errno = 0;
346 info.si_code = SEGV_MAPERR;
347 info.si_addr = (void __user *) addr;
348 info.si_trapno = 0;
349 force_sig_info(SIGSEGV, &info, current);
350 }
351
352 void sun4v_data_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
353 {
354 if (notify_die(DIE_TRAP_TL1, "data access exception tl1", regs,
355 0, 0x8, SIGTRAP) == NOTIFY_STOP)
356 return;
357
358 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
359 sun4v_data_access_exception(regs, addr, type_ctx);
360 }
361
362 #ifdef CONFIG_PCI
363 #include "pci_impl.h"
364 #endif
365
366 /* When access exceptions happen, we must do this. */
367 static void spitfire_clean_and_reenable_l1_caches(void)
368 {
369 unsigned long va;
370
371 if (tlb_type != spitfire)
372 BUG();
373
374 /* Clean 'em. */
375 for (va = 0; va < (PAGE_SIZE << 1); va += 32) {
376 spitfire_put_icache_tag(va, 0x0);
377 spitfire_put_dcache_tag(va, 0x0);
378 }
379
380 /* Re-enable in LSU. */
381 __asm__ __volatile__("flush %%g6\n\t"
382 "membar #Sync\n\t"
383 "stxa %0, [%%g0] %1\n\t"
384 "membar #Sync"
385 : /* no outputs */
386 : "r" (LSU_CONTROL_IC | LSU_CONTROL_DC |
387 LSU_CONTROL_IM | LSU_CONTROL_DM),
388 "i" (ASI_LSU_CONTROL)
389 : "memory");
390 }
391
392 static void spitfire_enable_estate_errors(void)
393 {
394 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
395 "membar #Sync"
396 : /* no outputs */
397 : "r" (ESTATE_ERR_ALL),
398 "i" (ASI_ESTATE_ERROR_EN));
399 }
400
401 static char ecc_syndrome_table[] = {
402 0x4c, 0x40, 0x41, 0x48, 0x42, 0x48, 0x48, 0x49,
403 0x43, 0x48, 0x48, 0x49, 0x48, 0x49, 0x49, 0x4a,
404 0x44, 0x48, 0x48, 0x20, 0x48, 0x39, 0x4b, 0x48,
405 0x48, 0x25, 0x31, 0x48, 0x28, 0x48, 0x48, 0x2c,
406 0x45, 0x48, 0x48, 0x21, 0x48, 0x3d, 0x04, 0x48,
407 0x48, 0x4b, 0x35, 0x48, 0x2d, 0x48, 0x48, 0x29,
408 0x48, 0x00, 0x01, 0x48, 0x0a, 0x48, 0x48, 0x4b,
409 0x0f, 0x48, 0x48, 0x4b, 0x48, 0x49, 0x49, 0x48,
410 0x46, 0x48, 0x48, 0x2a, 0x48, 0x3b, 0x27, 0x48,
411 0x48, 0x4b, 0x33, 0x48, 0x22, 0x48, 0x48, 0x2e,
412 0x48, 0x19, 0x1d, 0x48, 0x1b, 0x4a, 0x48, 0x4b,
413 0x1f, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
414 0x48, 0x4b, 0x24, 0x48, 0x07, 0x48, 0x48, 0x36,
415 0x4b, 0x48, 0x48, 0x3e, 0x48, 0x30, 0x38, 0x48,
416 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x16, 0x48,
417 0x48, 0x12, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
418 0x47, 0x48, 0x48, 0x2f, 0x48, 0x3f, 0x4b, 0x48,
419 0x48, 0x06, 0x37, 0x48, 0x23, 0x48, 0x48, 0x2b,
420 0x48, 0x05, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x32,
421 0x26, 0x48, 0x48, 0x3a, 0x48, 0x34, 0x3c, 0x48,
422 0x48, 0x11, 0x15, 0x48, 0x13, 0x4a, 0x48, 0x4b,
423 0x17, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
424 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x1e, 0x48,
425 0x48, 0x1a, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
426 0x48, 0x08, 0x0d, 0x48, 0x02, 0x48, 0x48, 0x49,
427 0x03, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x4b, 0x48,
428 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x10, 0x48,
429 0x48, 0x14, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
430 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x18, 0x48,
431 0x48, 0x1c, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
432 0x4a, 0x0c, 0x09, 0x48, 0x0e, 0x48, 0x48, 0x4b,
433 0x0b, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x4b, 0x4a
434 };
435
436 static char *syndrome_unknown = "<Unknown>";
437
438 static void spitfire_log_udb_syndrome(unsigned long afar, unsigned long udbh, unsigned long udbl, unsigned long bit)
439 {
440 unsigned short scode;
441 char memmod_str[64], *p;
442
443 if (udbl & bit) {
444 scode = ecc_syndrome_table[udbl & 0xff];
445 if (sprintf_dimm(scode, afar, memmod_str, sizeof(memmod_str)) < 0)
446 p = syndrome_unknown;
447 else
448 p = memmod_str;
449 printk(KERN_WARNING "CPU[%d]: UDBL Syndrome[%x] "
450 "Memory Module \"%s\"\n",
451 smp_processor_id(), scode, p);
452 }
453
454 if (udbh & bit) {
455 scode = ecc_syndrome_table[udbh & 0xff];
456 if (sprintf_dimm(scode, afar, memmod_str, sizeof(memmod_str)) < 0)
457 p = syndrome_unknown;
458 else
459 p = memmod_str;
460 printk(KERN_WARNING "CPU[%d]: UDBH Syndrome[%x] "
461 "Memory Module \"%s\"\n",
462 smp_processor_id(), scode, p);
463 }
464
465 }
466
467 static void spitfire_cee_log(unsigned long afsr, unsigned long afar, unsigned long udbh, unsigned long udbl, int tl1, struct pt_regs *regs)
468 {
469
470 printk(KERN_WARNING "CPU[%d]: Correctable ECC Error "
471 "AFSR[%lx] AFAR[%016lx] UDBL[%lx] UDBH[%lx] TL>1[%d]\n",
472 smp_processor_id(), afsr, afar, udbl, udbh, tl1);
473
474 spitfire_log_udb_syndrome(afar, udbh, udbl, UDBE_CE);
475
476 /* We always log it, even if someone is listening for this
477 * trap.
478 */
479 notify_die(DIE_TRAP, "Correctable ECC Error", regs,
480 0, TRAP_TYPE_CEE, SIGTRAP);
481
482 /* The Correctable ECC Error trap does not disable I/D caches. So
483 * we only have to restore the ESTATE Error Enable register.
484 */
485 spitfire_enable_estate_errors();
486 }
487
488 static void spitfire_ue_log(unsigned long afsr, unsigned long afar, unsigned long udbh, unsigned long udbl, unsigned long tt, int tl1, struct pt_regs *regs)
489 {
490 siginfo_t info;
491
492 printk(KERN_WARNING "CPU[%d]: Uncorrectable Error AFSR[%lx] "
493 "AFAR[%lx] UDBL[%lx] UDBH[%ld] TT[%lx] TL>1[%d]\n",
494 smp_processor_id(), afsr, afar, udbl, udbh, tt, tl1);
495
496 /* XXX add more human friendly logging of the error status
497 * XXX as is implemented for cheetah
498 */
499
500 spitfire_log_udb_syndrome(afar, udbh, udbl, UDBE_UE);
501
502 /* We always log it, even if someone is listening for this
503 * trap.
504 */
505 notify_die(DIE_TRAP, "Uncorrectable Error", regs,
506 0, tt, SIGTRAP);
507
508 if (regs->tstate & TSTATE_PRIV) {
509 if (tl1)
510 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
511 die_if_kernel("UE", regs);
512 }
513
514 /* XXX need more intelligent processing here, such as is implemented
515 * XXX for cheetah errors, in fact if the E-cache still holds the
516 * XXX line with bad parity this will loop
517 */
518
519 spitfire_clean_and_reenable_l1_caches();
520 spitfire_enable_estate_errors();
521
522 if (test_thread_flag(TIF_32BIT)) {
523 regs->tpc &= 0xffffffff;
524 regs->tnpc &= 0xffffffff;
525 }
526 info.si_signo = SIGBUS;
527 info.si_errno = 0;
528 info.si_code = BUS_OBJERR;
529 info.si_addr = (void *)0;
530 info.si_trapno = 0;
531 force_sig_info(SIGBUS, &info, current);
532 }
533
534 void spitfire_access_error(struct pt_regs *regs, unsigned long status_encoded, unsigned long afar)
535 {
536 unsigned long afsr, tt, udbh, udbl;
537 int tl1;
538
539 afsr = (status_encoded & SFSTAT_AFSR_MASK) >> SFSTAT_AFSR_SHIFT;
540 tt = (status_encoded & SFSTAT_TRAP_TYPE) >> SFSTAT_TRAP_TYPE_SHIFT;
541 tl1 = (status_encoded & SFSTAT_TL_GT_ONE) ? 1 : 0;
542 udbl = (status_encoded & SFSTAT_UDBL_MASK) >> SFSTAT_UDBL_SHIFT;
543 udbh = (status_encoded & SFSTAT_UDBH_MASK) >> SFSTAT_UDBH_SHIFT;
544
545 #ifdef CONFIG_PCI
546 if (tt == TRAP_TYPE_DAE &&
547 pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
548 spitfire_clean_and_reenable_l1_caches();
549 spitfire_enable_estate_errors();
550
551 pci_poke_faulted = 1;
552 regs->tnpc = regs->tpc + 4;
553 return;
554 }
555 #endif
556
557 if (afsr & SFAFSR_UE)
558 spitfire_ue_log(afsr, afar, udbh, udbl, tt, tl1, regs);
559
560 if (tt == TRAP_TYPE_CEE) {
561 /* Handle the case where we took a CEE trap, but ACK'd
562 * only the UE state in the UDB error registers.
563 */
564 if (afsr & SFAFSR_UE) {
565 if (udbh & UDBE_CE) {
566 __asm__ __volatile__(
567 "stxa %0, [%1] %2\n\t"
568 "membar #Sync"
569 : /* no outputs */
570 : "r" (udbh & UDBE_CE),
571 "r" (0x0), "i" (ASI_UDB_ERROR_W));
572 }
573 if (udbl & UDBE_CE) {
574 __asm__ __volatile__(
575 "stxa %0, [%1] %2\n\t"
576 "membar #Sync"
577 : /* no outputs */
578 : "r" (udbl & UDBE_CE),
579 "r" (0x18), "i" (ASI_UDB_ERROR_W));
580 }
581 }
582
583 spitfire_cee_log(afsr, afar, udbh, udbl, tl1, regs);
584 }
585 }
586
587 int cheetah_pcache_forced_on;
588
589 void cheetah_enable_pcache(void)
590 {
591 unsigned long dcr;
592
593 printk("CHEETAH: Enabling P-Cache on cpu %d.\n",
594 smp_processor_id());
595
596 __asm__ __volatile__("ldxa [%%g0] %1, %0"
597 : "=r" (dcr)
598 : "i" (ASI_DCU_CONTROL_REG));
599 dcr |= (DCU_PE | DCU_HPE | DCU_SPE | DCU_SL);
600 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
601 "membar #Sync"
602 : /* no outputs */
603 : "r" (dcr), "i" (ASI_DCU_CONTROL_REG));
604 }
605
606 /* Cheetah error trap handling. */
607 static unsigned long ecache_flush_physbase;
608 static unsigned long ecache_flush_linesize;
609 static unsigned long ecache_flush_size;
610
611 /* This table is ordered in priority of errors and matches the
612 * AFAR overwrite policy as well.
613 */
614
615 struct afsr_error_table {
616 unsigned long mask;
617 const char *name;
618 };
619
620 static const char CHAFSR_PERR_msg[] =
621 "System interface protocol error";
622 static const char CHAFSR_IERR_msg[] =
623 "Internal processor error";
624 static const char CHAFSR_ISAP_msg[] =
625 "System request parity error on incoming address";
626 static const char CHAFSR_UCU_msg[] =
627 "Uncorrectable E-cache ECC error for ifetch/data";
628 static const char CHAFSR_UCC_msg[] =
629 "SW Correctable E-cache ECC error for ifetch/data";
630 static const char CHAFSR_UE_msg[] =
631 "Uncorrectable system bus data ECC error for read";
632 static const char CHAFSR_EDU_msg[] =
633 "Uncorrectable E-cache ECC error for stmerge/blkld";
634 static const char CHAFSR_EMU_msg[] =
635 "Uncorrectable system bus MTAG error";
636 static const char CHAFSR_WDU_msg[] =
637 "Uncorrectable E-cache ECC error for writeback";
638 static const char CHAFSR_CPU_msg[] =
639 "Uncorrectable ECC error for copyout";
640 static const char CHAFSR_CE_msg[] =
641 "HW corrected system bus data ECC error for read";
642 static const char CHAFSR_EDC_msg[] =
643 "HW corrected E-cache ECC error for stmerge/blkld";
644 static const char CHAFSR_EMC_msg[] =
645 "HW corrected system bus MTAG ECC error";
646 static const char CHAFSR_WDC_msg[] =
647 "HW corrected E-cache ECC error for writeback";
648 static const char CHAFSR_CPC_msg[] =
649 "HW corrected ECC error for copyout";
650 static const char CHAFSR_TO_msg[] =
651 "Unmapped error from system bus";
652 static const char CHAFSR_BERR_msg[] =
653 "Bus error response from system bus";
654 static const char CHAFSR_IVC_msg[] =
655 "HW corrected system bus data ECC error for ivec read";
656 static const char CHAFSR_IVU_msg[] =
657 "Uncorrectable system bus data ECC error for ivec read";
658 static struct afsr_error_table __cheetah_error_table[] = {
659 { CHAFSR_PERR, CHAFSR_PERR_msg },
660 { CHAFSR_IERR, CHAFSR_IERR_msg },
661 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
662 { CHAFSR_UCU, CHAFSR_UCU_msg },
663 { CHAFSR_UCC, CHAFSR_UCC_msg },
664 { CHAFSR_UE, CHAFSR_UE_msg },
665 { CHAFSR_EDU, CHAFSR_EDU_msg },
666 { CHAFSR_EMU, CHAFSR_EMU_msg },
667 { CHAFSR_WDU, CHAFSR_WDU_msg },
668 { CHAFSR_CPU, CHAFSR_CPU_msg },
669 { CHAFSR_CE, CHAFSR_CE_msg },
670 { CHAFSR_EDC, CHAFSR_EDC_msg },
671 { CHAFSR_EMC, CHAFSR_EMC_msg },
672 { CHAFSR_WDC, CHAFSR_WDC_msg },
673 { CHAFSR_CPC, CHAFSR_CPC_msg },
674 { CHAFSR_TO, CHAFSR_TO_msg },
675 { CHAFSR_BERR, CHAFSR_BERR_msg },
676 /* These two do not update the AFAR. */
677 { CHAFSR_IVC, CHAFSR_IVC_msg },
678 { CHAFSR_IVU, CHAFSR_IVU_msg },
679 { 0, NULL },
680 };
681 static const char CHPAFSR_DTO_msg[] =
682 "System bus unmapped error for prefetch/storequeue-read";
683 static const char CHPAFSR_DBERR_msg[] =
684 "System bus error for prefetch/storequeue-read";
685 static const char CHPAFSR_THCE_msg[] =
686 "Hardware corrected E-cache Tag ECC error";
687 static const char CHPAFSR_TSCE_msg[] =
688 "SW handled correctable E-cache Tag ECC error";
689 static const char CHPAFSR_TUE_msg[] =
690 "Uncorrectable E-cache Tag ECC error";
691 static const char CHPAFSR_DUE_msg[] =
692 "System bus uncorrectable data ECC error due to prefetch/store-fill";
693 static struct afsr_error_table __cheetah_plus_error_table[] = {
694 { CHAFSR_PERR, CHAFSR_PERR_msg },
695 { CHAFSR_IERR, CHAFSR_IERR_msg },
696 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
697 { CHAFSR_UCU, CHAFSR_UCU_msg },
698 { CHAFSR_UCC, CHAFSR_UCC_msg },
699 { CHAFSR_UE, CHAFSR_UE_msg },
700 { CHAFSR_EDU, CHAFSR_EDU_msg },
701 { CHAFSR_EMU, CHAFSR_EMU_msg },
702 { CHAFSR_WDU, CHAFSR_WDU_msg },
703 { CHAFSR_CPU, CHAFSR_CPU_msg },
704 { CHAFSR_CE, CHAFSR_CE_msg },
705 { CHAFSR_EDC, CHAFSR_EDC_msg },
706 { CHAFSR_EMC, CHAFSR_EMC_msg },
707 { CHAFSR_WDC, CHAFSR_WDC_msg },
708 { CHAFSR_CPC, CHAFSR_CPC_msg },
709 { CHAFSR_TO, CHAFSR_TO_msg },
710 { CHAFSR_BERR, CHAFSR_BERR_msg },
711 { CHPAFSR_DTO, CHPAFSR_DTO_msg },
712 { CHPAFSR_DBERR, CHPAFSR_DBERR_msg },
713 { CHPAFSR_THCE, CHPAFSR_THCE_msg },
714 { CHPAFSR_TSCE, CHPAFSR_TSCE_msg },
715 { CHPAFSR_TUE, CHPAFSR_TUE_msg },
716 { CHPAFSR_DUE, CHPAFSR_DUE_msg },
717 /* These two do not update the AFAR. */
718 { CHAFSR_IVC, CHAFSR_IVC_msg },
719 { CHAFSR_IVU, CHAFSR_IVU_msg },
720 { 0, NULL },
721 };
722 static const char JPAFSR_JETO_msg[] =
723 "System interface protocol error, hw timeout caused";
724 static const char JPAFSR_SCE_msg[] =
725 "Parity error on system snoop results";
726 static const char JPAFSR_JEIC_msg[] =
727 "System interface protocol error, illegal command detected";
728 static const char JPAFSR_JEIT_msg[] =
729 "System interface protocol error, illegal ADTYPE detected";
730 static const char JPAFSR_OM_msg[] =
731 "Out of range memory error has occurred";
732 static const char JPAFSR_ETP_msg[] =
733 "Parity error on L2 cache tag SRAM";
734 static const char JPAFSR_UMS_msg[] =
735 "Error due to unsupported store";
736 static const char JPAFSR_RUE_msg[] =
737 "Uncorrectable ECC error from remote cache/memory";
738 static const char JPAFSR_RCE_msg[] =
739 "Correctable ECC error from remote cache/memory";
740 static const char JPAFSR_BP_msg[] =
741 "JBUS parity error on returned read data";
742 static const char JPAFSR_WBP_msg[] =
743 "JBUS parity error on data for writeback or block store";
744 static const char JPAFSR_FRC_msg[] =
745 "Foreign read to DRAM incurring correctable ECC error";
746 static const char JPAFSR_FRU_msg[] =
747 "Foreign read to DRAM incurring uncorrectable ECC error";
748 static struct afsr_error_table __jalapeno_error_table[] = {
749 { JPAFSR_JETO, JPAFSR_JETO_msg },
750 { JPAFSR_SCE, JPAFSR_SCE_msg },
751 { JPAFSR_JEIC, JPAFSR_JEIC_msg },
752 { JPAFSR_JEIT, JPAFSR_JEIT_msg },
753 { CHAFSR_PERR, CHAFSR_PERR_msg },
754 { CHAFSR_IERR, CHAFSR_IERR_msg },
755 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
756 { CHAFSR_UCU, CHAFSR_UCU_msg },
757 { CHAFSR_UCC, CHAFSR_UCC_msg },
758 { CHAFSR_UE, CHAFSR_UE_msg },
759 { CHAFSR_EDU, CHAFSR_EDU_msg },
760 { JPAFSR_OM, JPAFSR_OM_msg },
761 { CHAFSR_WDU, CHAFSR_WDU_msg },
762 { CHAFSR_CPU, CHAFSR_CPU_msg },
763 { CHAFSR_CE, CHAFSR_CE_msg },
764 { CHAFSR_EDC, CHAFSR_EDC_msg },
765 { JPAFSR_ETP, JPAFSR_ETP_msg },
766 { CHAFSR_WDC, CHAFSR_WDC_msg },
767 { CHAFSR_CPC, CHAFSR_CPC_msg },
768 { CHAFSR_TO, CHAFSR_TO_msg },
769 { CHAFSR_BERR, CHAFSR_BERR_msg },
770 { JPAFSR_UMS, JPAFSR_UMS_msg },
771 { JPAFSR_RUE, JPAFSR_RUE_msg },
772 { JPAFSR_RCE, JPAFSR_RCE_msg },
773 { JPAFSR_BP, JPAFSR_BP_msg },
774 { JPAFSR_WBP, JPAFSR_WBP_msg },
775 { JPAFSR_FRC, JPAFSR_FRC_msg },
776 { JPAFSR_FRU, JPAFSR_FRU_msg },
777 /* These two do not update the AFAR. */
778 { CHAFSR_IVU, CHAFSR_IVU_msg },
779 { 0, NULL },
780 };
781 static struct afsr_error_table *cheetah_error_table;
782 static unsigned long cheetah_afsr_errors;
783
784 struct cheetah_err_info *cheetah_error_log;
785
786 static inline struct cheetah_err_info *cheetah_get_error_log(unsigned long afsr)
787 {
788 struct cheetah_err_info *p;
789 int cpu = smp_processor_id();
790
791 if (!cheetah_error_log)
792 return NULL;
793
794 p = cheetah_error_log + (cpu * 2);
795 if ((afsr & CHAFSR_TL1) != 0UL)
796 p++;
797
798 return p;
799 }
800
801 extern unsigned int tl0_icpe[], tl1_icpe[];
802 extern unsigned int tl0_dcpe[], tl1_dcpe[];
803 extern unsigned int tl0_fecc[], tl1_fecc[];
804 extern unsigned int tl0_cee[], tl1_cee[];
805 extern unsigned int tl0_iae[], tl1_iae[];
806 extern unsigned int tl0_dae[], tl1_dae[];
807 extern unsigned int cheetah_plus_icpe_trap_vector[], cheetah_plus_icpe_trap_vector_tl1[];
808 extern unsigned int cheetah_plus_dcpe_trap_vector[], cheetah_plus_dcpe_trap_vector_tl1[];
809 extern unsigned int cheetah_fecc_trap_vector[], cheetah_fecc_trap_vector_tl1[];
810 extern unsigned int cheetah_cee_trap_vector[], cheetah_cee_trap_vector_tl1[];
811 extern unsigned int cheetah_deferred_trap_vector[], cheetah_deferred_trap_vector_tl1[];
812
813 void __init cheetah_ecache_flush_init(void)
814 {
815 unsigned long largest_size, smallest_linesize, order, ver;
816 int i, sz;
817
818 /* Scan all cpu device tree nodes, note two values:
819 * 1) largest E-cache size
820 * 2) smallest E-cache line size
821 */
822 largest_size = 0UL;
823 smallest_linesize = ~0UL;
824
825 for (i = 0; i < NR_CPUS; i++) {
826 unsigned long val;
827
828 val = cpu_data(i).ecache_size;
829 if (!val)
830 continue;
831
832 if (val > largest_size)
833 largest_size = val;
834
835 val = cpu_data(i).ecache_line_size;
836 if (val < smallest_linesize)
837 smallest_linesize = val;
838
839 }
840
841 if (largest_size == 0UL || smallest_linesize == ~0UL) {
842 prom_printf("cheetah_ecache_flush_init: Cannot probe cpu E-cache "
843 "parameters.\n");
844 prom_halt();
845 }
846
847 ecache_flush_size = (2 * largest_size);
848 ecache_flush_linesize = smallest_linesize;
849
850 ecache_flush_physbase = find_ecache_flush_span(ecache_flush_size);
851
852 if (ecache_flush_physbase == ~0UL) {
853 prom_printf("cheetah_ecache_flush_init: Cannot find %d byte "
854 "contiguous physical memory.\n",
855 ecache_flush_size);
856 prom_halt();
857 }
858
859 /* Now allocate error trap reporting scoreboard. */
860 sz = NR_CPUS * (2 * sizeof(struct cheetah_err_info));
861 for (order = 0; order < MAX_ORDER; order++) {
862 if ((PAGE_SIZE << order) >= sz)
863 break;
864 }
865 cheetah_error_log = (struct cheetah_err_info *)
866 __get_free_pages(GFP_KERNEL, order);
867 if (!cheetah_error_log) {
868 prom_printf("cheetah_ecache_flush_init: Failed to allocate "
869 "error logging scoreboard (%d bytes).\n", sz);
870 prom_halt();
871 }
872 memset(cheetah_error_log, 0, PAGE_SIZE << order);
873
874 /* Mark all AFSRs as invalid so that the trap handler will
875 * log new new information there.
876 */
877 for (i = 0; i < 2 * NR_CPUS; i++)
878 cheetah_error_log[i].afsr = CHAFSR_INVALID;
879
880 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
881 if ((ver >> 32) == __JALAPENO_ID ||
882 (ver >> 32) == __SERRANO_ID) {
883 cheetah_error_table = &__jalapeno_error_table[0];
884 cheetah_afsr_errors = JPAFSR_ERRORS;
885 } else if ((ver >> 32) == 0x003e0015) {
886 cheetah_error_table = &__cheetah_plus_error_table[0];
887 cheetah_afsr_errors = CHPAFSR_ERRORS;
888 } else {
889 cheetah_error_table = &__cheetah_error_table[0];
890 cheetah_afsr_errors = CHAFSR_ERRORS;
891 }
892
893 /* Now patch trap tables. */
894 memcpy(tl0_fecc, cheetah_fecc_trap_vector, (8 * 4));
895 memcpy(tl1_fecc, cheetah_fecc_trap_vector_tl1, (8 * 4));
896 memcpy(tl0_cee, cheetah_cee_trap_vector, (8 * 4));
897 memcpy(tl1_cee, cheetah_cee_trap_vector_tl1, (8 * 4));
898 memcpy(tl0_iae, cheetah_deferred_trap_vector, (8 * 4));
899 memcpy(tl1_iae, cheetah_deferred_trap_vector_tl1, (8 * 4));
900 memcpy(tl0_dae, cheetah_deferred_trap_vector, (8 * 4));
901 memcpy(tl1_dae, cheetah_deferred_trap_vector_tl1, (8 * 4));
902 if (tlb_type == cheetah_plus) {
903 memcpy(tl0_dcpe, cheetah_plus_dcpe_trap_vector, (8 * 4));
904 memcpy(tl1_dcpe, cheetah_plus_dcpe_trap_vector_tl1, (8 * 4));
905 memcpy(tl0_icpe, cheetah_plus_icpe_trap_vector, (8 * 4));
906 memcpy(tl1_icpe, cheetah_plus_icpe_trap_vector_tl1, (8 * 4));
907 }
908 flushi(PAGE_OFFSET);
909 }
910
911 static void cheetah_flush_ecache(void)
912 {
913 unsigned long flush_base = ecache_flush_physbase;
914 unsigned long flush_linesize = ecache_flush_linesize;
915 unsigned long flush_size = ecache_flush_size;
916
917 __asm__ __volatile__("1: subcc %0, %4, %0\n\t"
918 " bne,pt %%xcc, 1b\n\t"
919 " ldxa [%2 + %0] %3, %%g0\n\t"
920 : "=&r" (flush_size)
921 : "0" (flush_size), "r" (flush_base),
922 "i" (ASI_PHYS_USE_EC), "r" (flush_linesize));
923 }
924
925 static void cheetah_flush_ecache_line(unsigned long physaddr)
926 {
927 unsigned long alias;
928
929 physaddr &= ~(8UL - 1UL);
930 physaddr = (ecache_flush_physbase +
931 (physaddr & ((ecache_flush_size>>1UL) - 1UL)));
932 alias = physaddr + (ecache_flush_size >> 1UL);
933 __asm__ __volatile__("ldxa [%0] %2, %%g0\n\t"
934 "ldxa [%1] %2, %%g0\n\t"
935 "membar #Sync"
936 : /* no outputs */
937 : "r" (physaddr), "r" (alias),
938 "i" (ASI_PHYS_USE_EC));
939 }
940
941 /* Unfortunately, the diagnostic access to the I-cache tags we need to
942 * use to clear the thing interferes with I-cache coherency transactions.
943 *
944 * So we must only flush the I-cache when it is disabled.
945 */
946 static void __cheetah_flush_icache(void)
947 {
948 unsigned int icache_size, icache_line_size;
949 unsigned long addr;
950
951 icache_size = local_cpu_data().icache_size;
952 icache_line_size = local_cpu_data().icache_line_size;
953
954 /* Clear the valid bits in all the tags. */
955 for (addr = 0; addr < icache_size; addr += icache_line_size) {
956 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
957 "membar #Sync"
958 : /* no outputs */
959 : "r" (addr | (2 << 3)),
960 "i" (ASI_IC_TAG));
961 }
962 }
963
964 static void cheetah_flush_icache(void)
965 {
966 unsigned long dcu_save;
967
968 /* Save current DCU, disable I-cache. */
969 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
970 "or %0, %2, %%g1\n\t"
971 "stxa %%g1, [%%g0] %1\n\t"
972 "membar #Sync"
973 : "=r" (dcu_save)
974 : "i" (ASI_DCU_CONTROL_REG), "i" (DCU_IC)
975 : "g1");
976
977 __cheetah_flush_icache();
978
979 /* Restore DCU register */
980 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
981 "membar #Sync"
982 : /* no outputs */
983 : "r" (dcu_save), "i" (ASI_DCU_CONTROL_REG));
984 }
985
986 static void cheetah_flush_dcache(void)
987 {
988 unsigned int dcache_size, dcache_line_size;
989 unsigned long addr;
990
991 dcache_size = local_cpu_data().dcache_size;
992 dcache_line_size = local_cpu_data().dcache_line_size;
993
994 for (addr = 0; addr < dcache_size; addr += dcache_line_size) {
995 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
996 "membar #Sync"
997 : /* no outputs */
998 : "r" (addr), "i" (ASI_DCACHE_TAG));
999 }
1000 }
1001
1002 /* In order to make the even parity correct we must do two things.
1003 * First, we clear DC_data_parity and set DC_utag to an appropriate value.
1004 * Next, we clear out all 32-bytes of data for that line. Data of
1005 * all-zero + tag parity value of zero == correct parity.
1006 */
1007 static void cheetah_plus_zap_dcache_parity(void)
1008 {
1009 unsigned int dcache_size, dcache_line_size;
1010 unsigned long addr;
1011
1012 dcache_size = local_cpu_data().dcache_size;
1013 dcache_line_size = local_cpu_data().dcache_line_size;
1014
1015 for (addr = 0; addr < dcache_size; addr += dcache_line_size) {
1016 unsigned long tag = (addr >> 14);
1017 unsigned long line;
1018
1019 __asm__ __volatile__("membar #Sync\n\t"
1020 "stxa %0, [%1] %2\n\t"
1021 "membar #Sync"
1022 : /* no outputs */
1023 : "r" (tag), "r" (addr),
1024 "i" (ASI_DCACHE_UTAG));
1025 for (line = addr; line < addr + dcache_line_size; line += 8)
1026 __asm__ __volatile__("membar #Sync\n\t"
1027 "stxa %%g0, [%0] %1\n\t"
1028 "membar #Sync"
1029 : /* no outputs */
1030 : "r" (line),
1031 "i" (ASI_DCACHE_DATA));
1032 }
1033 }
1034
1035 /* Conversion tables used to frob Cheetah AFSR syndrome values into
1036 * something palatable to the memory controller driver get_unumber
1037 * routine.
1038 */
1039 #define MT0 137
1040 #define MT1 138
1041 #define MT2 139
1042 #define NONE 254
1043 #define MTC0 140
1044 #define MTC1 141
1045 #define MTC2 142
1046 #define MTC3 143
1047 #define C0 128
1048 #define C1 129
1049 #define C2 130
1050 #define C3 131
1051 #define C4 132
1052 #define C5 133
1053 #define C6 134
1054 #define C7 135
1055 #define C8 136
1056 #define M2 144
1057 #define M3 145
1058 #define M4 146
1059 #define M 147
1060 static unsigned char cheetah_ecc_syntab[] = {
1061 /*00*/NONE, C0, C1, M2, C2, M2, M3, 47, C3, M2, M2, 53, M2, 41, 29, M,
1062 /*01*/C4, M, M, 50, M2, 38, 25, M2, M2, 33, 24, M2, 11, M, M2, 16,
1063 /*02*/C5, M, M, 46, M2, 37, 19, M2, M, 31, 32, M, 7, M2, M2, 10,
1064 /*03*/M2, 40, 13, M2, 59, M, M2, 66, M, M2, M2, 0, M2, 67, 71, M,
1065 /*04*/C6, M, M, 43, M, 36, 18, M, M2, 49, 15, M, 63, M2, M2, 6,
1066 /*05*/M2, 44, 28, M2, M, M2, M2, 52, 68, M2, M2, 62, M2, M3, M3, M4,
1067 /*06*/M2, 26, 106, M2, 64, M, M2, 2, 120, M, M2, M3, M, M3, M3, M4,
1068 /*07*/116, M2, M2, M3, M2, M3, M, M4, M2, 58, 54, M2, M, M4, M4, M3,
1069 /*08*/C7, M2, M, 42, M, 35, 17, M2, M, 45, 14, M2, 21, M2, M2, 5,
1070 /*09*/M, 27, M, M, 99, M, M, 3, 114, M2, M2, 20, M2, M3, M3, M,
1071 /*0a*/M2, 23, 113, M2, 112, M2, M, 51, 95, M, M2, M3, M2, M3, M3, M2,
1072 /*0b*/103, M, M2, M3, M2, M3, M3, M4, M2, 48, M, M, 73, M2, M, M3,
1073 /*0c*/M2, 22, 110, M2, 109, M2, M, 9, 108, M2, M, M3, M2, M3, M3, M,
1074 /*0d*/102, M2, M, M, M2, M3, M3, M, M2, M3, M3, M2, M, M4, M, M3,
1075 /*0e*/98, M, M2, M3, M2, M, M3, M4, M2, M3, M3, M4, M3, M, M, M,
1076 /*0f*/M2, M3, M3, M, M3, M, M, M, 56, M4, M, M3, M4, M, M, M,
1077 /*10*/C8, M, M2, 39, M, 34, 105, M2, M, 30, 104, M, 101, M, M, 4,
1078 /*11*/M, M, 100, M, 83, M, M2, 12, 87, M, M, 57, M2, M, M3, M,
1079 /*12*/M2, 97, 82, M2, 78, M2, M2, 1, 96, M, M, M, M, M, M3, M2,
1080 /*13*/94, M, M2, M3, M2, M, M3, M, M2, M, 79, M, 69, M, M4, M,
1081 /*14*/M2, 93, 92, M, 91, M, M2, 8, 90, M2, M2, M, M, M, M, M4,
1082 /*15*/89, M, M, M3, M2, M3, M3, M, M, M, M3, M2, M3, M2, M, M3,
1083 /*16*/86, M, M2, M3, M2, M, M3, M, M2, M, M3, M, M3, M, M, M3,
1084 /*17*/M, M, M3, M2, M3, M2, M4, M, 60, M, M2, M3, M4, M, M, M2,
1085 /*18*/M2, 88, 85, M2, 84, M, M2, 55, 81, M2, M2, M3, M2, M3, M3, M4,
1086 /*19*/77, M, M, M, M2, M3, M, M, M2, M3, M3, M4, M3, M2, M, M,
1087 /*1a*/74, M, M2, M3, M, M, M3, M, M, M, M3, M, M3, M, M4, M3,
1088 /*1b*/M2, 70, 107, M4, 65, M2, M2, M, 127, M, M, M, M2, M3, M3, M,
1089 /*1c*/80, M2, M2, 72, M, 119, 118, M, M2, 126, 76, M, 125, M, M4, M3,
1090 /*1d*/M2, 115, 124, M, 75, M, M, M3, 61, M, M4, M, M4, M, M, M,
1091 /*1e*/M, 123, 122, M4, 121, M4, M, M3, 117, M2, M2, M3, M4, M3, M, M,
1092 /*1f*/111, M, M, M, M4, M3, M3, M, M, M, M3, M, M3, M2, M, M
1093 };
1094 static unsigned char cheetah_mtag_syntab[] = {
1095 NONE, MTC0,
1096 MTC1, NONE,
1097 MTC2, NONE,
1098 NONE, MT0,
1099 MTC3, NONE,
1100 NONE, MT1,
1101 NONE, MT2,
1102 NONE, NONE
1103 };
1104
1105 /* Return the highest priority error conditon mentioned. */
1106 static inline unsigned long cheetah_get_hipri(unsigned long afsr)
1107 {
1108 unsigned long tmp = 0;
1109 int i;
1110
1111 for (i = 0; cheetah_error_table[i].mask; i++) {
1112 if ((tmp = (afsr & cheetah_error_table[i].mask)) != 0UL)
1113 return tmp;
1114 }
1115 return tmp;
1116 }
1117
1118 static const char *cheetah_get_string(unsigned long bit)
1119 {
1120 int i;
1121
1122 for (i = 0; cheetah_error_table[i].mask; i++) {
1123 if ((bit & cheetah_error_table[i].mask) != 0UL)
1124 return cheetah_error_table[i].name;
1125 }
1126 return "???";
1127 }
1128
1129 static void cheetah_log_errors(struct pt_regs *regs, struct cheetah_err_info *info,
1130 unsigned long afsr, unsigned long afar, int recoverable)
1131 {
1132 unsigned long hipri;
1133 char unum[256];
1134
1135 printk("%s" "ERROR(%d): Cheetah error trap taken afsr[%016lx] afar[%016lx] TL1(%d)\n",
1136 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1137 afsr, afar,
1138 (afsr & CHAFSR_TL1) ? 1 : 0);
1139 printk("%s" "ERROR(%d): TPC[%lx] TNPC[%lx] O7[%lx] TSTATE[%lx]\n",
1140 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1141 regs->tpc, regs->tnpc, regs->u_regs[UREG_I7], regs->tstate);
1142 printk("%s" "ERROR(%d): ",
1143 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id());
1144 printk("TPC<%pS>\n", (void *) regs->tpc);
1145 printk("%s" "ERROR(%d): M_SYND(%lx), E_SYND(%lx)%s%s\n",
1146 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1147 (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT,
1148 (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT,
1149 (afsr & CHAFSR_ME) ? ", Multiple Errors" : "",
1150 (afsr & CHAFSR_PRIV) ? ", Privileged" : "");
1151 hipri = cheetah_get_hipri(afsr);
1152 printk("%s" "ERROR(%d): Highest priority error (%016lx) \"%s\"\n",
1153 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1154 hipri, cheetah_get_string(hipri));
1155
1156 /* Try to get unumber if relevant. */
1157 #define ESYND_ERRORS (CHAFSR_IVC | CHAFSR_IVU | \
1158 CHAFSR_CPC | CHAFSR_CPU | \
1159 CHAFSR_UE | CHAFSR_CE | \
1160 CHAFSR_EDC | CHAFSR_EDU | \
1161 CHAFSR_UCC | CHAFSR_UCU | \
1162 CHAFSR_WDU | CHAFSR_WDC)
1163 #define MSYND_ERRORS (CHAFSR_EMC | CHAFSR_EMU)
1164 if (afsr & ESYND_ERRORS) {
1165 int syndrome;
1166 int ret;
1167
1168 syndrome = (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT;
1169 syndrome = cheetah_ecc_syntab[syndrome];
1170 ret = sprintf_dimm(syndrome, afar, unum, sizeof(unum));
1171 if (ret != -1)
1172 printk("%s" "ERROR(%d): AFAR E-syndrome [%s]\n",
1173 (recoverable ? KERN_WARNING : KERN_CRIT),
1174 smp_processor_id(), unum);
1175 } else if (afsr & MSYND_ERRORS) {
1176 int syndrome;
1177 int ret;
1178
1179 syndrome = (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT;
1180 syndrome = cheetah_mtag_syntab[syndrome];
1181 ret = sprintf_dimm(syndrome, afar, unum, sizeof(unum));
1182 if (ret != -1)
1183 printk("%s" "ERROR(%d): AFAR M-syndrome [%s]\n",
1184 (recoverable ? KERN_WARNING : KERN_CRIT),
1185 smp_processor_id(), unum);
1186 }
1187
1188 /* Now dump the cache snapshots. */
1189 printk("%s" "ERROR(%d): D-cache idx[%x] tag[%016llx] utag[%016llx] stag[%016llx]\n",
1190 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1191 (int) info->dcache_index,
1192 info->dcache_tag,
1193 info->dcache_utag,
1194 info->dcache_stag);
1195 printk("%s" "ERROR(%d): D-cache data0[%016llx] data1[%016llx] data2[%016llx] data3[%016llx]\n",
1196 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1197 info->dcache_data[0],
1198 info->dcache_data[1],
1199 info->dcache_data[2],
1200 info->dcache_data[3]);
1201 printk("%s" "ERROR(%d): I-cache idx[%x] tag[%016llx] utag[%016llx] stag[%016llx] "
1202 "u[%016llx] l[%016llx]\n",
1203 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1204 (int) info->icache_index,
1205 info->icache_tag,
1206 info->icache_utag,
1207 info->icache_stag,
1208 info->icache_upper,
1209 info->icache_lower);
1210 printk("%s" "ERROR(%d): I-cache INSN0[%016llx] INSN1[%016llx] INSN2[%016llx] INSN3[%016llx]\n",
1211 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1212 info->icache_data[0],
1213 info->icache_data[1],
1214 info->icache_data[2],
1215 info->icache_data[3]);
1216 printk("%s" "ERROR(%d): I-cache INSN4[%016llx] INSN5[%016llx] INSN6[%016llx] INSN7[%016llx]\n",
1217 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1218 info->icache_data[4],
1219 info->icache_data[5],
1220 info->icache_data[6],
1221 info->icache_data[7]);
1222 printk("%s" "ERROR(%d): E-cache idx[%x] tag[%016llx]\n",
1223 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1224 (int) info->ecache_index, info->ecache_tag);
1225 printk("%s" "ERROR(%d): E-cache data0[%016llx] data1[%016llx] data2[%016llx] data3[%016llx]\n",
1226 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1227 info->ecache_data[0],
1228 info->ecache_data[1],
1229 info->ecache_data[2],
1230 info->ecache_data[3]);
1231
1232 afsr = (afsr & ~hipri) & cheetah_afsr_errors;
1233 while (afsr != 0UL) {
1234 unsigned long bit = cheetah_get_hipri(afsr);
1235
1236 printk("%s" "ERROR: Multiple-error (%016lx) \"%s\"\n",
1237 (recoverable ? KERN_WARNING : KERN_CRIT),
1238 bit, cheetah_get_string(bit));
1239
1240 afsr &= ~bit;
1241 }
1242
1243 if (!recoverable)
1244 printk(KERN_CRIT "ERROR: This condition is not recoverable.\n");
1245 }
1246
1247 static int cheetah_recheck_errors(struct cheetah_err_info *logp)
1248 {
1249 unsigned long afsr, afar;
1250 int ret = 0;
1251
1252 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1253 : "=r" (afsr)
1254 : "i" (ASI_AFSR));
1255 if ((afsr & cheetah_afsr_errors) != 0) {
1256 if (logp != NULL) {
1257 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1258 : "=r" (afar)
1259 : "i" (ASI_AFAR));
1260 logp->afsr = afsr;
1261 logp->afar = afar;
1262 }
1263 ret = 1;
1264 }
1265 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1266 "membar #Sync\n\t"
1267 : : "r" (afsr), "i" (ASI_AFSR));
1268
1269 return ret;
1270 }
1271
1272 void cheetah_fecc_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1273 {
1274 struct cheetah_err_info local_snapshot, *p;
1275 int recoverable;
1276
1277 /* Flush E-cache */
1278 cheetah_flush_ecache();
1279
1280 p = cheetah_get_error_log(afsr);
1281 if (!p) {
1282 prom_printf("ERROR: Early Fast-ECC error afsr[%016lx] afar[%016lx]\n",
1283 afsr, afar);
1284 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1285 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1286 prom_halt();
1287 }
1288
1289 /* Grab snapshot of logged error. */
1290 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1291
1292 /* If the current trap snapshot does not match what the
1293 * trap handler passed along into our args, big trouble.
1294 * In such a case, mark the local copy as invalid.
1295 *
1296 * Else, it matches and we mark the afsr in the non-local
1297 * copy as invalid so we may log new error traps there.
1298 */
1299 if (p->afsr != afsr || p->afar != afar)
1300 local_snapshot.afsr = CHAFSR_INVALID;
1301 else
1302 p->afsr = CHAFSR_INVALID;
1303
1304 cheetah_flush_icache();
1305 cheetah_flush_dcache();
1306
1307 /* Re-enable I-cache/D-cache */
1308 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1309 "or %%g1, %1, %%g1\n\t"
1310 "stxa %%g1, [%%g0] %0\n\t"
1311 "membar #Sync"
1312 : /* no outputs */
1313 : "i" (ASI_DCU_CONTROL_REG),
1314 "i" (DCU_DC | DCU_IC)
1315 : "g1");
1316
1317 /* Re-enable error reporting */
1318 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1319 "or %%g1, %1, %%g1\n\t"
1320 "stxa %%g1, [%%g0] %0\n\t"
1321 "membar #Sync"
1322 : /* no outputs */
1323 : "i" (ASI_ESTATE_ERROR_EN),
1324 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1325 : "g1");
1326
1327 /* Decide if we can continue after handling this trap and
1328 * logging the error.
1329 */
1330 recoverable = 1;
1331 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1332 recoverable = 0;
1333
1334 /* Re-check AFSR/AFAR. What we are looking for here is whether a new
1335 * error was logged while we had error reporting traps disabled.
1336 */
1337 if (cheetah_recheck_errors(&local_snapshot)) {
1338 unsigned long new_afsr = local_snapshot.afsr;
1339
1340 /* If we got a new asynchronous error, die... */
1341 if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
1342 CHAFSR_WDU | CHAFSR_CPU |
1343 CHAFSR_IVU | CHAFSR_UE |
1344 CHAFSR_BERR | CHAFSR_TO))
1345 recoverable = 0;
1346 }
1347
1348 /* Log errors. */
1349 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1350
1351 if (!recoverable)
1352 panic("Irrecoverable Fast-ECC error trap.\n");
1353
1354 /* Flush E-cache to kick the error trap handlers out. */
1355 cheetah_flush_ecache();
1356 }
1357
1358 /* Try to fix a correctable error by pushing the line out from
1359 * the E-cache. Recheck error reporting registers to see if the
1360 * problem is intermittent.
1361 */
1362 static int cheetah_fix_ce(unsigned long physaddr)
1363 {
1364 unsigned long orig_estate;
1365 unsigned long alias1, alias2;
1366 int ret;
1367
1368 /* Make sure correctable error traps are disabled. */
1369 __asm__ __volatile__("ldxa [%%g0] %2, %0\n\t"
1370 "andn %0, %1, %%g1\n\t"
1371 "stxa %%g1, [%%g0] %2\n\t"
1372 "membar #Sync"
1373 : "=&r" (orig_estate)
1374 : "i" (ESTATE_ERROR_CEEN),
1375 "i" (ASI_ESTATE_ERROR_EN)
1376 : "g1");
1377
1378 /* We calculate alias addresses that will force the
1379 * cache line in question out of the E-cache. Then
1380 * we bring it back in with an atomic instruction so
1381 * that we get it in some modified/exclusive state,
1382 * then we displace it again to try and get proper ECC
1383 * pushed back into the system.
1384 */
1385 physaddr &= ~(8UL - 1UL);
1386 alias1 = (ecache_flush_physbase +
1387 (physaddr & ((ecache_flush_size >> 1) - 1)));
1388 alias2 = alias1 + (ecache_flush_size >> 1);
1389 __asm__ __volatile__("ldxa [%0] %3, %%g0\n\t"
1390 "ldxa [%1] %3, %%g0\n\t"
1391 "casxa [%2] %3, %%g0, %%g0\n\t"
1392 "ldxa [%0] %3, %%g0\n\t"
1393 "ldxa [%1] %3, %%g0\n\t"
1394 "membar #Sync"
1395 : /* no outputs */
1396 : "r" (alias1), "r" (alias2),
1397 "r" (physaddr), "i" (ASI_PHYS_USE_EC));
1398
1399 /* Did that trigger another error? */
1400 if (cheetah_recheck_errors(NULL)) {
1401 /* Try one more time. */
1402 __asm__ __volatile__("ldxa [%0] %1, %%g0\n\t"
1403 "membar #Sync"
1404 : : "r" (physaddr), "i" (ASI_PHYS_USE_EC));
1405 if (cheetah_recheck_errors(NULL))
1406 ret = 2;
1407 else
1408 ret = 1;
1409 } else {
1410 /* No new error, intermittent problem. */
1411 ret = 0;
1412 }
1413
1414 /* Restore error enables. */
1415 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1416 "membar #Sync"
1417 : : "r" (orig_estate), "i" (ASI_ESTATE_ERROR_EN));
1418
1419 return ret;
1420 }
1421
1422 /* Return non-zero if PADDR is a valid physical memory address. */
1423 static int cheetah_check_main_memory(unsigned long paddr)
1424 {
1425 unsigned long vaddr = PAGE_OFFSET + paddr;
1426
1427 if (vaddr > (unsigned long) high_memory)
1428 return 0;
1429
1430 return kern_addr_valid(vaddr);
1431 }
1432
1433 void cheetah_cee_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1434 {
1435 struct cheetah_err_info local_snapshot, *p;
1436 int recoverable, is_memory;
1437
1438 p = cheetah_get_error_log(afsr);
1439 if (!p) {
1440 prom_printf("ERROR: Early CEE error afsr[%016lx] afar[%016lx]\n",
1441 afsr, afar);
1442 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1443 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1444 prom_halt();
1445 }
1446
1447 /* Grab snapshot of logged error. */
1448 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1449
1450 /* If the current trap snapshot does not match what the
1451 * trap handler passed along into our args, big trouble.
1452 * In such a case, mark the local copy as invalid.
1453 *
1454 * Else, it matches and we mark the afsr in the non-local
1455 * copy as invalid so we may log new error traps there.
1456 */
1457 if (p->afsr != afsr || p->afar != afar)
1458 local_snapshot.afsr = CHAFSR_INVALID;
1459 else
1460 p->afsr = CHAFSR_INVALID;
1461
1462 is_memory = cheetah_check_main_memory(afar);
1463
1464 if (is_memory && (afsr & CHAFSR_CE) != 0UL) {
1465 /* XXX Might want to log the results of this operation
1466 * XXX somewhere... -DaveM
1467 */
1468 cheetah_fix_ce(afar);
1469 }
1470
1471 {
1472 int flush_all, flush_line;
1473
1474 flush_all = flush_line = 0;
1475 if ((afsr & CHAFSR_EDC) != 0UL) {
1476 if ((afsr & cheetah_afsr_errors) == CHAFSR_EDC)
1477 flush_line = 1;
1478 else
1479 flush_all = 1;
1480 } else if ((afsr & CHAFSR_CPC) != 0UL) {
1481 if ((afsr & cheetah_afsr_errors) == CHAFSR_CPC)
1482 flush_line = 1;
1483 else
1484 flush_all = 1;
1485 }
1486
1487 /* Trap handler only disabled I-cache, flush it. */
1488 cheetah_flush_icache();
1489
1490 /* Re-enable I-cache */
1491 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1492 "or %%g1, %1, %%g1\n\t"
1493 "stxa %%g1, [%%g0] %0\n\t"
1494 "membar #Sync"
1495 : /* no outputs */
1496 : "i" (ASI_DCU_CONTROL_REG),
1497 "i" (DCU_IC)
1498 : "g1");
1499
1500 if (flush_all)
1501 cheetah_flush_ecache();
1502 else if (flush_line)
1503 cheetah_flush_ecache_line(afar);
1504 }
1505
1506 /* Re-enable error reporting */
1507 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1508 "or %%g1, %1, %%g1\n\t"
1509 "stxa %%g1, [%%g0] %0\n\t"
1510 "membar #Sync"
1511 : /* no outputs */
1512 : "i" (ASI_ESTATE_ERROR_EN),
1513 "i" (ESTATE_ERROR_CEEN)
1514 : "g1");
1515
1516 /* Decide if we can continue after handling this trap and
1517 * logging the error.
1518 */
1519 recoverable = 1;
1520 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1521 recoverable = 0;
1522
1523 /* Re-check AFSR/AFAR */
1524 (void) cheetah_recheck_errors(&local_snapshot);
1525
1526 /* Log errors. */
1527 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1528
1529 if (!recoverable)
1530 panic("Irrecoverable Correctable-ECC error trap.\n");
1531 }
1532
1533 void cheetah_deferred_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1534 {
1535 struct cheetah_err_info local_snapshot, *p;
1536 int recoverable, is_memory;
1537
1538 #ifdef CONFIG_PCI
1539 /* Check for the special PCI poke sequence. */
1540 if (pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
1541 cheetah_flush_icache();
1542 cheetah_flush_dcache();
1543
1544 /* Re-enable I-cache/D-cache */
1545 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1546 "or %%g1, %1, %%g1\n\t"
1547 "stxa %%g1, [%%g0] %0\n\t"
1548 "membar #Sync"
1549 : /* no outputs */
1550 : "i" (ASI_DCU_CONTROL_REG),
1551 "i" (DCU_DC | DCU_IC)
1552 : "g1");
1553
1554 /* Re-enable error reporting */
1555 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1556 "or %%g1, %1, %%g1\n\t"
1557 "stxa %%g1, [%%g0] %0\n\t"
1558 "membar #Sync"
1559 : /* no outputs */
1560 : "i" (ASI_ESTATE_ERROR_EN),
1561 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1562 : "g1");
1563
1564 (void) cheetah_recheck_errors(NULL);
1565
1566 pci_poke_faulted = 1;
1567 regs->tpc += 4;
1568 regs->tnpc = regs->tpc + 4;
1569 return;
1570 }
1571 #endif
1572
1573 p = cheetah_get_error_log(afsr);
1574 if (!p) {
1575 prom_printf("ERROR: Early deferred error afsr[%016lx] afar[%016lx]\n",
1576 afsr, afar);
1577 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1578 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1579 prom_halt();
1580 }
1581
1582 /* Grab snapshot of logged error. */
1583 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1584
1585 /* If the current trap snapshot does not match what the
1586 * trap handler passed along into our args, big trouble.
1587 * In such a case, mark the local copy as invalid.
1588 *
1589 * Else, it matches and we mark the afsr in the non-local
1590 * copy as invalid so we may log new error traps there.
1591 */
1592 if (p->afsr != afsr || p->afar != afar)
1593 local_snapshot.afsr = CHAFSR_INVALID;
1594 else
1595 p->afsr = CHAFSR_INVALID;
1596
1597 is_memory = cheetah_check_main_memory(afar);
1598
1599 {
1600 int flush_all, flush_line;
1601
1602 flush_all = flush_line = 0;
1603 if ((afsr & CHAFSR_EDU) != 0UL) {
1604 if ((afsr & cheetah_afsr_errors) == CHAFSR_EDU)
1605 flush_line = 1;
1606 else
1607 flush_all = 1;
1608 } else if ((afsr & CHAFSR_BERR) != 0UL) {
1609 if ((afsr & cheetah_afsr_errors) == CHAFSR_BERR)
1610 flush_line = 1;
1611 else
1612 flush_all = 1;
1613 }
1614
1615 cheetah_flush_icache();
1616 cheetah_flush_dcache();
1617
1618 /* Re-enable I/D caches */
1619 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1620 "or %%g1, %1, %%g1\n\t"
1621 "stxa %%g1, [%%g0] %0\n\t"
1622 "membar #Sync"
1623 : /* no outputs */
1624 : "i" (ASI_DCU_CONTROL_REG),
1625 "i" (DCU_IC | DCU_DC)
1626 : "g1");
1627
1628 if (flush_all)
1629 cheetah_flush_ecache();
1630 else if (flush_line)
1631 cheetah_flush_ecache_line(afar);
1632 }
1633
1634 /* Re-enable error reporting */
1635 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1636 "or %%g1, %1, %%g1\n\t"
1637 "stxa %%g1, [%%g0] %0\n\t"
1638 "membar #Sync"
1639 : /* no outputs */
1640 : "i" (ASI_ESTATE_ERROR_EN),
1641 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1642 : "g1");
1643
1644 /* Decide if we can continue after handling this trap and
1645 * logging the error.
1646 */
1647 recoverable = 1;
1648 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1649 recoverable = 0;
1650
1651 /* Re-check AFSR/AFAR. What we are looking for here is whether a new
1652 * error was logged while we had error reporting traps disabled.
1653 */
1654 if (cheetah_recheck_errors(&local_snapshot)) {
1655 unsigned long new_afsr = local_snapshot.afsr;
1656
1657 /* If we got a new asynchronous error, die... */
1658 if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
1659 CHAFSR_WDU | CHAFSR_CPU |
1660 CHAFSR_IVU | CHAFSR_UE |
1661 CHAFSR_BERR | CHAFSR_TO))
1662 recoverable = 0;
1663 }
1664
1665 /* Log errors. */
1666 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1667
1668 /* "Recoverable" here means we try to yank the page from ever
1669 * being newly used again. This depends upon a few things:
1670 * 1) Must be main memory, and AFAR must be valid.
1671 * 2) If we trapped from user, OK.
1672 * 3) Else, if we trapped from kernel we must find exception
1673 * table entry (ie. we have to have been accessing user
1674 * space).
1675 *
1676 * If AFAR is not in main memory, or we trapped from kernel
1677 * and cannot find an exception table entry, it is unacceptable
1678 * to try and continue.
1679 */
1680 if (recoverable && is_memory) {
1681 if ((regs->tstate & TSTATE_PRIV) == 0UL) {
1682 /* OK, usermode access. */
1683 recoverable = 1;
1684 } else {
1685 const struct exception_table_entry *entry;
1686
1687 entry = search_exception_tables(regs->tpc);
1688 if (entry) {
1689 /* OK, kernel access to userspace. */
1690 recoverable = 1;
1691
1692 } else {
1693 /* BAD, privileged state is corrupted. */
1694 recoverable = 0;
1695 }
1696
1697 if (recoverable) {
1698 if (pfn_valid(afar >> PAGE_SHIFT))
1699 get_page(pfn_to_page(afar >> PAGE_SHIFT));
1700 else
1701 recoverable = 0;
1702
1703 /* Only perform fixup if we still have a
1704 * recoverable condition.
1705 */
1706 if (recoverable) {
1707 regs->tpc = entry->fixup;
1708 regs->tnpc = regs->tpc + 4;
1709 }
1710 }
1711 }
1712 } else {
1713 recoverable = 0;
1714 }
1715
1716 if (!recoverable)
1717 panic("Irrecoverable deferred error trap.\n");
1718 }
1719
1720 /* Handle a D/I cache parity error trap. TYPE is encoded as:
1721 *
1722 * Bit0: 0=dcache,1=icache
1723 * Bit1: 0=recoverable,1=unrecoverable
1724 *
1725 * The hardware has disabled both the I-cache and D-cache in
1726 * the %dcr register.
1727 */
1728 void cheetah_plus_parity_error(int type, struct pt_regs *regs)
1729 {
1730 if (type & 0x1)
1731 __cheetah_flush_icache();
1732 else
1733 cheetah_plus_zap_dcache_parity();
1734 cheetah_flush_dcache();
1735
1736 /* Re-enable I-cache/D-cache */
1737 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1738 "or %%g1, %1, %%g1\n\t"
1739 "stxa %%g1, [%%g0] %0\n\t"
1740 "membar #Sync"
1741 : /* no outputs */
1742 : "i" (ASI_DCU_CONTROL_REG),
1743 "i" (DCU_DC | DCU_IC)
1744 : "g1");
1745
1746 if (type & 0x2) {
1747 printk(KERN_EMERG "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
1748 smp_processor_id(),
1749 (type & 0x1) ? 'I' : 'D',
1750 regs->tpc);
1751 printk(KERN_EMERG "TPC<%pS>\n", (void *) regs->tpc);
1752 panic("Irrecoverable Cheetah+ parity error.");
1753 }
1754
1755 printk(KERN_WARNING "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
1756 smp_processor_id(),
1757 (type & 0x1) ? 'I' : 'D',
1758 regs->tpc);
1759 printk(KERN_WARNING "TPC<%pS>\n", (void *) regs->tpc);
1760 }
1761
1762 struct sun4v_error_entry {
1763 u64 err_handle;
1764 u64 err_stick;
1765
1766 u32 err_type;
1767 #define SUN4V_ERR_TYPE_UNDEFINED 0
1768 #define SUN4V_ERR_TYPE_UNCORRECTED_RES 1
1769 #define SUN4V_ERR_TYPE_PRECISE_NONRES 2
1770 #define SUN4V_ERR_TYPE_DEFERRED_NONRES 3
1771 #define SUN4V_ERR_TYPE_WARNING_RES 4
1772
1773 u32 err_attrs;
1774 #define SUN4V_ERR_ATTRS_PROCESSOR 0x00000001
1775 #define SUN4V_ERR_ATTRS_MEMORY 0x00000002
1776 #define SUN4V_ERR_ATTRS_PIO 0x00000004
1777 #define SUN4V_ERR_ATTRS_INT_REGISTERS 0x00000008
1778 #define SUN4V_ERR_ATTRS_FPU_REGISTERS 0x00000010
1779 #define SUN4V_ERR_ATTRS_USER_MODE 0x01000000
1780 #define SUN4V_ERR_ATTRS_PRIV_MODE 0x02000000
1781 #define SUN4V_ERR_ATTRS_RES_QUEUE_FULL 0x80000000
1782
1783 u64 err_raddr;
1784 u32 err_size;
1785 u16 err_cpu;
1786 u16 err_pad;
1787 };
1788
1789 static atomic_t sun4v_resum_oflow_cnt = ATOMIC_INIT(0);
1790 static atomic_t sun4v_nonresum_oflow_cnt = ATOMIC_INIT(0);
1791
1792 static const char *sun4v_err_type_to_str(u32 type)
1793 {
1794 switch (type) {
1795 case SUN4V_ERR_TYPE_UNDEFINED:
1796 return "undefined";
1797 case SUN4V_ERR_TYPE_UNCORRECTED_RES:
1798 return "uncorrected resumable";
1799 case SUN4V_ERR_TYPE_PRECISE_NONRES:
1800 return "precise nonresumable";
1801 case SUN4V_ERR_TYPE_DEFERRED_NONRES:
1802 return "deferred nonresumable";
1803 case SUN4V_ERR_TYPE_WARNING_RES:
1804 return "warning resumable";
1805 default:
1806 return "unknown";
1807 }
1808 }
1809
1810 static void sun4v_log_error(struct pt_regs *regs, struct sun4v_error_entry *ent, int cpu, const char *pfx, atomic_t *ocnt)
1811 {
1812 int cnt;
1813
1814 printk("%s: Reporting on cpu %d\n", pfx, cpu);
1815 printk("%s: err_handle[%llx] err_stick[%llx] err_type[%08x:%s]\n",
1816 pfx,
1817 ent->err_handle, ent->err_stick,
1818 ent->err_type,
1819 sun4v_err_type_to_str(ent->err_type));
1820 printk("%s: err_attrs[%08x:%s %s %s %s %s %s %s %s]\n",
1821 pfx,
1822 ent->err_attrs,
1823 ((ent->err_attrs & SUN4V_ERR_ATTRS_PROCESSOR) ?
1824 "processor" : ""),
1825 ((ent->err_attrs & SUN4V_ERR_ATTRS_MEMORY) ?
1826 "memory" : ""),
1827 ((ent->err_attrs & SUN4V_ERR_ATTRS_PIO) ?
1828 "pio" : ""),
1829 ((ent->err_attrs & SUN4V_ERR_ATTRS_INT_REGISTERS) ?
1830 "integer-regs" : ""),
1831 ((ent->err_attrs & SUN4V_ERR_ATTRS_FPU_REGISTERS) ?
1832 "fpu-regs" : ""),
1833 ((ent->err_attrs & SUN4V_ERR_ATTRS_USER_MODE) ?
1834 "user" : ""),
1835 ((ent->err_attrs & SUN4V_ERR_ATTRS_PRIV_MODE) ?
1836 "privileged" : ""),
1837 ((ent->err_attrs & SUN4V_ERR_ATTRS_RES_QUEUE_FULL) ?
1838 "queue-full" : ""));
1839 printk("%s: err_raddr[%016llx] err_size[%u] err_cpu[%u]\n",
1840 pfx,
1841 ent->err_raddr, ent->err_size, ent->err_cpu);
1842
1843 show_regs(regs);
1844
1845 if ((cnt = atomic_read(ocnt)) != 0) {
1846 atomic_set(ocnt, 0);
1847 wmb();
1848 printk("%s: Queue overflowed %d times.\n",
1849 pfx, cnt);
1850 }
1851 }
1852
1853 /* We run with %pil set to PIL_NORMAL_MAX and PSTATE_IE enabled in %pstate.
1854 * Log the event and clear the first word of the entry.
1855 */
1856 void sun4v_resum_error(struct pt_regs *regs, unsigned long offset)
1857 {
1858 struct sun4v_error_entry *ent, local_copy;
1859 struct trap_per_cpu *tb;
1860 unsigned long paddr;
1861 int cpu;
1862
1863 cpu = get_cpu();
1864
1865 tb = &trap_block[cpu];
1866 paddr = tb->resum_kernel_buf_pa + offset;
1867 ent = __va(paddr);
1868
1869 memcpy(&local_copy, ent, sizeof(struct sun4v_error_entry));
1870
1871 /* We have a local copy now, so release the entry. */
1872 ent->err_handle = 0;
1873 wmb();
1874
1875 put_cpu();
1876
1877 if (ent->err_type == SUN4V_ERR_TYPE_WARNING_RES) {
1878 /* If err_type is 0x4, it's a powerdown request. Do
1879 * not do the usual resumable error log because that
1880 * makes it look like some abnormal error.
1881 */
1882 printk(KERN_INFO "Power down request...\n");
1883 kill_cad_pid(SIGINT, 1);
1884 return;
1885 }
1886
1887 sun4v_log_error(regs, &local_copy, cpu,
1888 KERN_ERR "RESUMABLE ERROR",
1889 &sun4v_resum_oflow_cnt);
1890 }
1891
1892 /* If we try to printk() we'll probably make matters worse, by trying
1893 * to retake locks this cpu already holds or causing more errors. So
1894 * just bump a counter, and we'll report these counter bumps above.
1895 */
1896 void sun4v_resum_overflow(struct pt_regs *regs)
1897 {
1898 atomic_inc(&sun4v_resum_oflow_cnt);
1899 }
1900
1901 /* We run with %pil set to PIL_NORMAL_MAX and PSTATE_IE enabled in %pstate.
1902 * Log the event, clear the first word of the entry, and die.
1903 */
1904 void sun4v_nonresum_error(struct pt_regs *regs, unsigned long offset)
1905 {
1906 struct sun4v_error_entry *ent, local_copy;
1907 struct trap_per_cpu *tb;
1908 unsigned long paddr;
1909 int cpu;
1910
1911 cpu = get_cpu();
1912
1913 tb = &trap_block[cpu];
1914 paddr = tb->nonresum_kernel_buf_pa + offset;
1915 ent = __va(paddr);
1916
1917 memcpy(&local_copy, ent, sizeof(struct sun4v_error_entry));
1918
1919 /* We have a local copy now, so release the entry. */
1920 ent->err_handle = 0;
1921 wmb();
1922
1923 put_cpu();
1924
1925 #ifdef CONFIG_PCI
1926 /* Check for the special PCI poke sequence. */
1927 if (pci_poke_in_progress && pci_poke_cpu == cpu) {
1928 pci_poke_faulted = 1;
1929 regs->tpc += 4;
1930 regs->tnpc = regs->tpc + 4;
1931 return;
1932 }
1933 #endif
1934
1935 sun4v_log_error(regs, &local_copy, cpu,
1936 KERN_EMERG "NON-RESUMABLE ERROR",
1937 &sun4v_nonresum_oflow_cnt);
1938
1939 panic("Non-resumable error.");
1940 }
1941
1942 /* If we try to printk() we'll probably make matters worse, by trying
1943 * to retake locks this cpu already holds or causing more errors. So
1944 * just bump a counter, and we'll report these counter bumps above.
1945 */
1946 void sun4v_nonresum_overflow(struct pt_regs *regs)
1947 {
1948 /* XXX Actually even this can make not that much sense. Perhaps
1949 * XXX we should just pull the plug and panic directly from here?
1950 */
1951 atomic_inc(&sun4v_nonresum_oflow_cnt);
1952 }
1953
1954 unsigned long sun4v_err_itlb_vaddr;
1955 unsigned long sun4v_err_itlb_ctx;
1956 unsigned long sun4v_err_itlb_pte;
1957 unsigned long sun4v_err_itlb_error;
1958
1959 void sun4v_itlb_error_report(struct pt_regs *regs, int tl)
1960 {
1961 if (tl > 1)
1962 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
1963
1964 printk(KERN_EMERG "SUN4V-ITLB: Error at TPC[%lx], tl %d\n",
1965 regs->tpc, tl);
1966 printk(KERN_EMERG "SUN4V-ITLB: TPC<%pS>\n", (void *) regs->tpc);
1967 printk(KERN_EMERG "SUN4V-ITLB: O7[%lx]\n", regs->u_regs[UREG_I7]);
1968 printk(KERN_EMERG "SUN4V-ITLB: O7<%pS>\n",
1969 (void *) regs->u_regs[UREG_I7]);
1970 printk(KERN_EMERG "SUN4V-ITLB: vaddr[%lx] ctx[%lx] "
1971 "pte[%lx] error[%lx]\n",
1972 sun4v_err_itlb_vaddr, sun4v_err_itlb_ctx,
1973 sun4v_err_itlb_pte, sun4v_err_itlb_error);
1974
1975 prom_halt();
1976 }
1977
1978 unsigned long sun4v_err_dtlb_vaddr;
1979 unsigned long sun4v_err_dtlb_ctx;
1980 unsigned long sun4v_err_dtlb_pte;
1981 unsigned long sun4v_err_dtlb_error;
1982
1983 void sun4v_dtlb_error_report(struct pt_regs *regs, int tl)
1984 {
1985 if (tl > 1)
1986 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
1987
1988 printk(KERN_EMERG "SUN4V-DTLB: Error at TPC[%lx], tl %d\n",
1989 regs->tpc, tl);
1990 printk(KERN_EMERG "SUN4V-DTLB: TPC<%pS>\n", (void *) regs->tpc);
1991 printk(KERN_EMERG "SUN4V-DTLB: O7[%lx]\n", regs->u_regs[UREG_I7]);
1992 printk(KERN_EMERG "SUN4V-DTLB: O7<%pS>\n",
1993 (void *) regs->u_regs[UREG_I7]);
1994 printk(KERN_EMERG "SUN4V-DTLB: vaddr[%lx] ctx[%lx] "
1995 "pte[%lx] error[%lx]\n",
1996 sun4v_err_dtlb_vaddr, sun4v_err_dtlb_ctx,
1997 sun4v_err_dtlb_pte, sun4v_err_dtlb_error);
1998
1999 prom_halt();
2000 }
2001
2002 void hypervisor_tlbop_error(unsigned long err, unsigned long op)
2003 {
2004 printk(KERN_CRIT "SUN4V: TLB hv call error %lu for op %lu\n",
2005 err, op);
2006 }
2007
2008 void hypervisor_tlbop_error_xcall(unsigned long err, unsigned long op)
2009 {
2010 printk(KERN_CRIT "SUN4V: XCALL TLB hv call error %lu for op %lu\n",
2011 err, op);
2012 }
2013
2014 void do_fpe_common(struct pt_regs *regs)
2015 {
2016 if (regs->tstate & TSTATE_PRIV) {
2017 regs->tpc = regs->tnpc;
2018 regs->tnpc += 4;
2019 } else {
2020 unsigned long fsr = current_thread_info()->xfsr[0];
2021 siginfo_t info;
2022
2023 if (test_thread_flag(TIF_32BIT)) {
2024 regs->tpc &= 0xffffffff;
2025 regs->tnpc &= 0xffffffff;
2026 }
2027 info.si_signo = SIGFPE;
2028 info.si_errno = 0;
2029 info.si_addr = (void __user *)regs->tpc;
2030 info.si_trapno = 0;
2031 info.si_code = __SI_FAULT;
2032 if ((fsr & 0x1c000) == (1 << 14)) {
2033 if (fsr & 0x10)
2034 info.si_code = FPE_FLTINV;
2035 else if (fsr & 0x08)
2036 info.si_code = FPE_FLTOVF;
2037 else if (fsr & 0x04)
2038 info.si_code = FPE_FLTUND;
2039 else if (fsr & 0x02)
2040 info.si_code = FPE_FLTDIV;
2041 else if (fsr & 0x01)
2042 info.si_code = FPE_FLTRES;
2043 }
2044 force_sig_info(SIGFPE, &info, current);
2045 }
2046 }
2047
2048 void do_fpieee(struct pt_regs *regs)
2049 {
2050 if (notify_die(DIE_TRAP, "fpu exception ieee", regs,
2051 0, 0x24, SIGFPE) == NOTIFY_STOP)
2052 return;
2053
2054 do_fpe_common(regs);
2055 }
2056
2057 extern int do_mathemu(struct pt_regs *, struct fpustate *);
2058
2059 void do_fpother(struct pt_regs *regs)
2060 {
2061 struct fpustate *f = FPUSTATE;
2062 int ret = 0;
2063
2064 if (notify_die(DIE_TRAP, "fpu exception other", regs,
2065 0, 0x25, SIGFPE) == NOTIFY_STOP)
2066 return;
2067
2068 switch ((current_thread_info()->xfsr[0] & 0x1c000)) {
2069 case (2 << 14): /* unfinished_FPop */
2070 case (3 << 14): /* unimplemented_FPop */
2071 ret = do_mathemu(regs, f);
2072 break;
2073 }
2074 if (ret)
2075 return;
2076 do_fpe_common(regs);
2077 }
2078
2079 void do_tof(struct pt_regs *regs)
2080 {
2081 siginfo_t info;
2082
2083 if (notify_die(DIE_TRAP, "tagged arithmetic overflow", regs,
2084 0, 0x26, SIGEMT) == NOTIFY_STOP)
2085 return;
2086
2087 if (regs->tstate & TSTATE_PRIV)
2088 die_if_kernel("Penguin overflow trap from kernel mode", regs);
2089 if (test_thread_flag(TIF_32BIT)) {
2090 regs->tpc &= 0xffffffff;
2091 regs->tnpc &= 0xffffffff;
2092 }
2093 info.si_signo = SIGEMT;
2094 info.si_errno = 0;
2095 info.si_code = EMT_TAGOVF;
2096 info.si_addr = (void __user *)regs->tpc;
2097 info.si_trapno = 0;
2098 force_sig_info(SIGEMT, &info, current);
2099 }
2100
2101 void do_div0(struct pt_regs *regs)
2102 {
2103 siginfo_t info;
2104
2105 if (notify_die(DIE_TRAP, "integer division by zero", regs,
2106 0, 0x28, SIGFPE) == NOTIFY_STOP)
2107 return;
2108
2109 if (regs->tstate & TSTATE_PRIV)
2110 die_if_kernel("TL0: Kernel divide by zero.", regs);
2111 if (test_thread_flag(TIF_32BIT)) {
2112 regs->tpc &= 0xffffffff;
2113 regs->tnpc &= 0xffffffff;
2114 }
2115 info.si_signo = SIGFPE;
2116 info.si_errno = 0;
2117 info.si_code = FPE_INTDIV;
2118 info.si_addr = (void __user *)regs->tpc;
2119 info.si_trapno = 0;
2120 force_sig_info(SIGFPE, &info, current);
2121 }
2122
2123 static void instruction_dump(unsigned int *pc)
2124 {
2125 int i;
2126
2127 if ((((unsigned long) pc) & 3))
2128 return;
2129
2130 printk("Instruction DUMP:");
2131 for (i = -3; i < 6; i++)
2132 printk("%c%08x%c",i?' ':'<',pc[i],i?' ':'>');
2133 printk("\n");
2134 }
2135
2136 static void user_instruction_dump(unsigned int __user *pc)
2137 {
2138 int i;
2139 unsigned int buf[9];
2140
2141 if ((((unsigned long) pc) & 3))
2142 return;
2143
2144 if (copy_from_user(buf, pc - 3, sizeof(buf)))
2145 return;
2146
2147 printk("Instruction DUMP:");
2148 for (i = 0; i < 9; i++)
2149 printk("%c%08x%c",i==3?' ':'<',buf[i],i==3?' ':'>');
2150 printk("\n");
2151 }
2152
2153 void show_stack(struct task_struct *tsk, unsigned long *_ksp)
2154 {
2155 unsigned long fp, ksp;
2156 struct thread_info *tp;
2157 int count = 0;
2158 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2159 int graph = 0;
2160 #endif
2161
2162 ksp = (unsigned long) _ksp;
2163 if (!tsk)
2164 tsk = current;
2165 tp = task_thread_info(tsk);
2166 if (ksp == 0UL) {
2167 if (tsk == current)
2168 asm("mov %%fp, %0" : "=r" (ksp));
2169 else
2170 ksp = tp->ksp;
2171 }
2172 if (tp == current_thread_info())
2173 flushw_all();
2174
2175 fp = ksp + STACK_BIAS;
2176
2177 printk("Call Trace:\n");
2178 do {
2179 struct sparc_stackf *sf;
2180 struct pt_regs *regs;
2181 unsigned long pc;
2182
2183 if (!kstack_valid(tp, fp))
2184 break;
2185 sf = (struct sparc_stackf *) fp;
2186 regs = (struct pt_regs *) (sf + 1);
2187
2188 if (kstack_is_trap_frame(tp, regs)) {
2189 if (!(regs->tstate & TSTATE_PRIV))
2190 break;
2191 pc = regs->tpc;
2192 fp = regs->u_regs[UREG_I6] + STACK_BIAS;
2193 } else {
2194 pc = sf->callers_pc;
2195 fp = (unsigned long)sf->fp + STACK_BIAS;
2196 }
2197
2198 printk(" [%016lx] %pS\n", pc, (void *) pc);
2199 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2200 if ((pc + 8UL) == (unsigned long) &return_to_handler) {
2201 int index = tsk->curr_ret_stack;
2202 if (tsk->ret_stack && index >= graph) {
2203 pc = tsk->ret_stack[index - graph].ret;
2204 printk(" [%016lx] %pS\n", pc, (void *) pc);
2205 graph++;
2206 }
2207 }
2208 #endif
2209 } while (++count < 16);
2210 }
2211
2212 void dump_stack(void)
2213 {
2214 show_stack(current, NULL);
2215 }
2216
2217 EXPORT_SYMBOL(dump_stack);
2218
2219 static inline struct reg_window *kernel_stack_up(struct reg_window *rw)
2220 {
2221 unsigned long fp = rw->ins[6];
2222
2223 if (!fp)
2224 return NULL;
2225
2226 return (struct reg_window *) (fp + STACK_BIAS);
2227 }
2228
2229 void die_if_kernel(char *str, struct pt_regs *regs)
2230 {
2231 static int die_counter;
2232 int count = 0;
2233
2234 /* Amuse the user. */
2235 printk(
2236 " \\|/ ____ \\|/\n"
2237 " \"@'/ .. \\`@\"\n"
2238 " /_| \\__/ |_\\\n"
2239 " \\__U_/\n");
2240
2241 printk("%s(%d): %s [#%d]\n", current->comm, task_pid_nr(current), str, ++die_counter);
2242 notify_die(DIE_OOPS, str, regs, 0, 255, SIGSEGV);
2243 __asm__ __volatile__("flushw");
2244 show_regs(regs);
2245 add_taint(TAINT_DIE);
2246 if (regs->tstate & TSTATE_PRIV) {
2247 struct thread_info *tp = current_thread_info();
2248 struct reg_window *rw = (struct reg_window *)
2249 (regs->u_regs[UREG_FP] + STACK_BIAS);
2250
2251 /* Stop the back trace when we hit userland or we
2252 * find some badly aligned kernel stack.
2253 */
2254 while (rw &&
2255 count++ < 30 &&
2256 kstack_valid(tp, (unsigned long) rw)) {
2257 printk("Caller[%016lx]: %pS\n", rw->ins[7],
2258 (void *) rw->ins[7]);
2259
2260 rw = kernel_stack_up(rw);
2261 }
2262 instruction_dump ((unsigned int *) regs->tpc);
2263 } else {
2264 if (test_thread_flag(TIF_32BIT)) {
2265 regs->tpc &= 0xffffffff;
2266 regs->tnpc &= 0xffffffff;
2267 }
2268 user_instruction_dump ((unsigned int __user *) regs->tpc);
2269 }
2270 if (regs->tstate & TSTATE_PRIV)
2271 do_exit(SIGKILL);
2272 do_exit(SIGSEGV);
2273 }
2274 EXPORT_SYMBOL(die_if_kernel);
2275
2276 #define VIS_OPCODE_MASK ((0x3 << 30) | (0x3f << 19))
2277 #define VIS_OPCODE_VAL ((0x2 << 30) | (0x36 << 19))
2278
2279 extern int handle_popc(u32 insn, struct pt_regs *regs);
2280 extern int handle_ldf_stq(u32 insn, struct pt_regs *regs);
2281
2282 void do_illegal_instruction(struct pt_regs *regs)
2283 {
2284 unsigned long pc = regs->tpc;
2285 unsigned long tstate = regs->tstate;
2286 u32 insn;
2287 siginfo_t info;
2288
2289 if (notify_die(DIE_TRAP, "illegal instruction", regs,
2290 0, 0x10, SIGILL) == NOTIFY_STOP)
2291 return;
2292
2293 if (tstate & TSTATE_PRIV)
2294 die_if_kernel("Kernel illegal instruction", regs);
2295 if (test_thread_flag(TIF_32BIT))
2296 pc = (u32)pc;
2297 if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
2298 if ((insn & 0xc1ffc000) == 0x81700000) /* POPC */ {
2299 if (handle_popc(insn, regs))
2300 return;
2301 } else if ((insn & 0xc1580000) == 0xc1100000) /* LDQ/STQ */ {
2302 if (handle_ldf_stq(insn, regs))
2303 return;
2304 } else if (tlb_type == hypervisor) {
2305 if ((insn & VIS_OPCODE_MASK) == VIS_OPCODE_VAL) {
2306 if (!vis_emul(regs, insn))
2307 return;
2308 } else {
2309 struct fpustate *f = FPUSTATE;
2310
2311 /* XXX maybe verify XFSR bits like
2312 * XXX do_fpother() does?
2313 */
2314 if (do_mathemu(regs, f))
2315 return;
2316 }
2317 }
2318 }
2319 info.si_signo = SIGILL;
2320 info.si_errno = 0;
2321 info.si_code = ILL_ILLOPC;
2322 info.si_addr = (void __user *)pc;
2323 info.si_trapno = 0;
2324 force_sig_info(SIGILL, &info, current);
2325 }
2326
2327 extern void kernel_unaligned_trap(struct pt_regs *regs, unsigned int insn);
2328
2329 void mem_address_unaligned(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr)
2330 {
2331 siginfo_t info;
2332
2333 if (notify_die(DIE_TRAP, "memory address unaligned", regs,
2334 0, 0x34, SIGSEGV) == NOTIFY_STOP)
2335 return;
2336
2337 if (regs->tstate & TSTATE_PRIV) {
2338 kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc));
2339 return;
2340 }
2341 info.si_signo = SIGBUS;
2342 info.si_errno = 0;
2343 info.si_code = BUS_ADRALN;
2344 info.si_addr = (void __user *)sfar;
2345 info.si_trapno = 0;
2346 force_sig_info(SIGBUS, &info, current);
2347 }
2348
2349 void sun4v_do_mna(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
2350 {
2351 siginfo_t info;
2352
2353 if (notify_die(DIE_TRAP, "memory address unaligned", regs,
2354 0, 0x34, SIGSEGV) == NOTIFY_STOP)
2355 return;
2356
2357 if (regs->tstate & TSTATE_PRIV) {
2358 kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc));
2359 return;
2360 }
2361 info.si_signo = SIGBUS;
2362 info.si_errno = 0;
2363 info.si_code = BUS_ADRALN;
2364 info.si_addr = (void __user *) addr;
2365 info.si_trapno = 0;
2366 force_sig_info(SIGBUS, &info, current);
2367 }
2368
2369 void do_privop(struct pt_regs *regs)
2370 {
2371 siginfo_t info;
2372
2373 if (notify_die(DIE_TRAP, "privileged operation", regs,
2374 0, 0x11, SIGILL) == NOTIFY_STOP)
2375 return;
2376
2377 if (test_thread_flag(TIF_32BIT)) {
2378 regs->tpc &= 0xffffffff;
2379 regs->tnpc &= 0xffffffff;
2380 }
2381 info.si_signo = SIGILL;
2382 info.si_errno = 0;
2383 info.si_code = ILL_PRVOPC;
2384 info.si_addr = (void __user *)regs->tpc;
2385 info.si_trapno = 0;
2386 force_sig_info(SIGILL, &info, current);
2387 }
2388
2389 void do_privact(struct pt_regs *regs)
2390 {
2391 do_privop(regs);
2392 }
2393
2394 /* Trap level 1 stuff or other traps we should never see... */
2395 void do_cee(struct pt_regs *regs)
2396 {
2397 die_if_kernel("TL0: Cache Error Exception", regs);
2398 }
2399
2400 void do_cee_tl1(struct pt_regs *regs)
2401 {
2402 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2403 die_if_kernel("TL1: Cache Error Exception", regs);
2404 }
2405
2406 void do_dae_tl1(struct pt_regs *regs)
2407 {
2408 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2409 die_if_kernel("TL1: Data Access Exception", regs);
2410 }
2411
2412 void do_iae_tl1(struct pt_regs *regs)
2413 {
2414 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2415 die_if_kernel("TL1: Instruction Access Exception", regs);
2416 }
2417
2418 void do_div0_tl1(struct pt_regs *regs)
2419 {
2420 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2421 die_if_kernel("TL1: DIV0 Exception", regs);
2422 }
2423
2424 void do_fpdis_tl1(struct pt_regs *regs)
2425 {
2426 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2427 die_if_kernel("TL1: FPU Disabled", regs);
2428 }
2429
2430 void do_fpieee_tl1(struct pt_regs *regs)
2431 {
2432 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2433 die_if_kernel("TL1: FPU IEEE Exception", regs);
2434 }
2435
2436 void do_fpother_tl1(struct pt_regs *regs)
2437 {
2438 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2439 die_if_kernel("TL1: FPU Other Exception", regs);
2440 }
2441
2442 void do_ill_tl1(struct pt_regs *regs)
2443 {
2444 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2445 die_if_kernel("TL1: Illegal Instruction Exception", regs);
2446 }
2447
2448 void do_irq_tl1(struct pt_regs *regs)
2449 {
2450 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2451 die_if_kernel("TL1: IRQ Exception", regs);
2452 }
2453
2454 void do_lddfmna_tl1(struct pt_regs *regs)
2455 {
2456 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2457 die_if_kernel("TL1: LDDF Exception", regs);
2458 }
2459
2460 void do_stdfmna_tl1(struct pt_regs *regs)
2461 {
2462 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2463 die_if_kernel("TL1: STDF Exception", regs);
2464 }
2465
2466 void do_paw(struct pt_regs *regs)
2467 {
2468 die_if_kernel("TL0: Phys Watchpoint Exception", regs);
2469 }
2470
2471 void do_paw_tl1(struct pt_regs *regs)
2472 {
2473 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2474 die_if_kernel("TL1: Phys Watchpoint Exception", regs);
2475 }
2476
2477 void do_vaw(struct pt_regs *regs)
2478 {
2479 die_if_kernel("TL0: Virt Watchpoint Exception", regs);
2480 }
2481
2482 void do_vaw_tl1(struct pt_regs *regs)
2483 {
2484 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2485 die_if_kernel("TL1: Virt Watchpoint Exception", regs);
2486 }
2487
2488 void do_tof_tl1(struct pt_regs *regs)
2489 {
2490 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2491 die_if_kernel("TL1: Tag Overflow Exception", regs);
2492 }
2493
2494 void do_getpsr(struct pt_regs *regs)
2495 {
2496 regs->u_regs[UREG_I0] = tstate_to_psr(regs->tstate);
2497 regs->tpc = regs->tnpc;
2498 regs->tnpc += 4;
2499 if (test_thread_flag(TIF_32BIT)) {
2500 regs->tpc &= 0xffffffff;
2501 regs->tnpc &= 0xffffffff;
2502 }
2503 }
2504
2505 struct trap_per_cpu trap_block[NR_CPUS];
2506 EXPORT_SYMBOL(trap_block);
2507
2508 /* This can get invoked before sched_init() so play it super safe
2509 * and use hard_smp_processor_id().
2510 */
2511 void notrace init_cur_cpu_trap(struct thread_info *t)
2512 {
2513 int cpu = hard_smp_processor_id();
2514 struct trap_per_cpu *p = &trap_block[cpu];
2515
2516 p->thread = t;
2517 p->pgd_paddr = 0;
2518 }
2519
2520 extern void thread_info_offsets_are_bolixed_dave(void);
2521 extern void trap_per_cpu_offsets_are_bolixed_dave(void);
2522 extern void tsb_config_offsets_are_bolixed_dave(void);
2523
2524 /* Only invoked on boot processor. */
2525 void __init trap_init(void)
2526 {
2527 /* Compile time sanity check. */
2528 BUILD_BUG_ON(TI_TASK != offsetof(struct thread_info, task) ||
2529 TI_FLAGS != offsetof(struct thread_info, flags) ||
2530 TI_CPU != offsetof(struct thread_info, cpu) ||
2531 TI_FPSAVED != offsetof(struct thread_info, fpsaved) ||
2532 TI_KSP != offsetof(struct thread_info, ksp) ||
2533 TI_FAULT_ADDR != offsetof(struct thread_info,
2534 fault_address) ||
2535 TI_KREGS != offsetof(struct thread_info, kregs) ||
2536 TI_UTRAPS != offsetof(struct thread_info, utraps) ||
2537 TI_EXEC_DOMAIN != offsetof(struct thread_info,
2538 exec_domain) ||
2539 TI_REG_WINDOW != offsetof(struct thread_info,
2540 reg_window) ||
2541 TI_RWIN_SPTRS != offsetof(struct thread_info,
2542 rwbuf_stkptrs) ||
2543 TI_GSR != offsetof(struct thread_info, gsr) ||
2544 TI_XFSR != offsetof(struct thread_info, xfsr) ||
2545 TI_PRE_COUNT != offsetof(struct thread_info,
2546 preempt_count) ||
2547 TI_NEW_CHILD != offsetof(struct thread_info, new_child) ||
2548 TI_SYS_NOERROR != offsetof(struct thread_info,
2549 syscall_noerror) ||
2550 TI_RESTART_BLOCK != offsetof(struct thread_info,
2551 restart_block) ||
2552 TI_KUNA_REGS != offsetof(struct thread_info,
2553 kern_una_regs) ||
2554 TI_KUNA_INSN != offsetof(struct thread_info,
2555 kern_una_insn) ||
2556 TI_FPREGS != offsetof(struct thread_info, fpregs) ||
2557 (TI_FPREGS & (64 - 1)));
2558
2559 BUILD_BUG_ON(TRAP_PER_CPU_THREAD != offsetof(struct trap_per_cpu,
2560 thread) ||
2561 (TRAP_PER_CPU_PGD_PADDR !=
2562 offsetof(struct trap_per_cpu, pgd_paddr)) ||
2563 (TRAP_PER_CPU_CPU_MONDO_PA !=
2564 offsetof(struct trap_per_cpu, cpu_mondo_pa)) ||
2565 (TRAP_PER_CPU_DEV_MONDO_PA !=
2566 offsetof(struct trap_per_cpu, dev_mondo_pa)) ||
2567 (TRAP_PER_CPU_RESUM_MONDO_PA !=
2568 offsetof(struct trap_per_cpu, resum_mondo_pa)) ||
2569 (TRAP_PER_CPU_RESUM_KBUF_PA !=
2570 offsetof(struct trap_per_cpu, resum_kernel_buf_pa)) ||
2571 (TRAP_PER_CPU_NONRESUM_MONDO_PA !=
2572 offsetof(struct trap_per_cpu, nonresum_mondo_pa)) ||
2573 (TRAP_PER_CPU_NONRESUM_KBUF_PA !=
2574 offsetof(struct trap_per_cpu, nonresum_kernel_buf_pa)) ||
2575 (TRAP_PER_CPU_FAULT_INFO !=
2576 offsetof(struct trap_per_cpu, fault_info)) ||
2577 (TRAP_PER_CPU_CPU_MONDO_BLOCK_PA !=
2578 offsetof(struct trap_per_cpu, cpu_mondo_block_pa)) ||
2579 (TRAP_PER_CPU_CPU_LIST_PA !=
2580 offsetof(struct trap_per_cpu, cpu_list_pa)) ||
2581 (TRAP_PER_CPU_TSB_HUGE !=
2582 offsetof(struct trap_per_cpu, tsb_huge)) ||
2583 (TRAP_PER_CPU_TSB_HUGE_TEMP !=
2584 offsetof(struct trap_per_cpu, tsb_huge_temp)) ||
2585 (TRAP_PER_CPU_IRQ_WORKLIST_PA !=
2586 offsetof(struct trap_per_cpu, irq_worklist_pa)) ||
2587 (TRAP_PER_CPU_CPU_MONDO_QMASK !=
2588 offsetof(struct trap_per_cpu, cpu_mondo_qmask)) ||
2589 (TRAP_PER_CPU_DEV_MONDO_QMASK !=
2590 offsetof(struct trap_per_cpu, dev_mondo_qmask)) ||
2591 (TRAP_PER_CPU_RESUM_QMASK !=
2592 offsetof(struct trap_per_cpu, resum_qmask)) ||
2593 (TRAP_PER_CPU_NONRESUM_QMASK !=
2594 offsetof(struct trap_per_cpu, nonresum_qmask)) ||
2595 (TRAP_PER_CPU_PER_CPU_BASE !=
2596 offsetof(struct trap_per_cpu, __per_cpu_base)));
2597
2598 BUILD_BUG_ON((TSB_CONFIG_TSB !=
2599 offsetof(struct tsb_config, tsb)) ||
2600 (TSB_CONFIG_RSS_LIMIT !=
2601 offsetof(struct tsb_config, tsb_rss_limit)) ||
2602 (TSB_CONFIG_NENTRIES !=
2603 offsetof(struct tsb_config, tsb_nentries)) ||
2604 (TSB_CONFIG_REG_VAL !=
2605 offsetof(struct tsb_config, tsb_reg_val)) ||
2606 (TSB_CONFIG_MAP_VADDR !=
2607 offsetof(struct tsb_config, tsb_map_vaddr)) ||
2608 (TSB_CONFIG_MAP_PTE !=
2609 offsetof(struct tsb_config, tsb_map_pte)));
2610
2611 /* Attach to the address space of init_task. On SMP we
2612 * do this in smp.c:smp_callin for other cpus.
2613 */
2614 atomic_inc(&init_mm.mm_count);
2615 current->active_mm = &init_mm;
2616 }