arch/tile/include/asm/irqflags.h

   1 /*
   2  * Copyright 2010 Tilera Corporation. All Rights Reserved.
   3  *
   4  *   This program is free software; you can redistribute it and/or
   5  *   modify it under the terms of the GNU General Public License
   6  *   as published by the Free Software Foundation, version 2.
   7  *
   8  *   This program is distributed in the hope that it will be useful, but
   9  *   WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  11  *   NON INFRINGEMENT.  See the GNU General Public License for
  12  *   more details.
  13  */
  14
  15 #ifndef _ASM_TILE_IRQFLAGS_H
  16 #define _ASM_TILE_IRQFLAGS_H
  17
  18 #include <arch/interrupts.h>
  19 #include <arch/chip.h>
  20
  21 #if !defined(__tilegx__) && defined(__ASSEMBLY__)
  22
  23 /*
  24  * The set of interrupts we want to allow when interrupts are nominally
  25  * disabled.  The remainder are effectively "NMI" interrupts from
  26  * the point of view of the generic Linux code.  Note that synchronous
  27  * interrupts (aka "non-queued") are not blocked by the mask in any case.
  28  */
  29 #if CHIP_HAS_AUX_PERF_COUNTERS()
  30 #define LINUX_MASKABLE_INTERRUPTS_HI \
  31        (~(INT_MASK_HI(INT_PERF_COUNT) | INT_MASK_HI(INT_AUX_PERF_COUNT)))
  32 #else
  33 #define LINUX_MASKABLE_INTERRUPTS_HI \
  34        (~(INT_MASK_HI(INT_PERF_COUNT)))
  35 #endif
  36
  37 #else
  38
  39 #if CHIP_HAS_AUX_PERF_COUNTERS()
  40 #define LINUX_MASKABLE_INTERRUPTS \
  41         (~(INT_MASK(INT_PERF_COUNT) | INT_MASK(INT_AUX_PERF_COUNT)))
  42 #else
  43 #define LINUX_MASKABLE_INTERRUPTS \
  44         (~(INT_MASK(INT_PERF_COUNT)))
  45 #endif
  46
  47 #endif
  48
  49 #ifndef __ASSEMBLY__
  50
  51 /* NOTE: we can't include <linux/percpu.h> due to #include dependencies. */
  52 #include <asm/percpu.h>
  53 #include <arch/spr_def.h>
  54
  55 /* Set and clear kernel interrupt masks. */
  56 #if CHIP_HAS_SPLIT_INTR_MASK()
  57 #if INT_PERF_COUNT < 32 || INT_AUX_PERF_COUNT < 32 || INT_MEM_ERROR >= 32
  58 # error Fix assumptions about which word various interrupts are in
  59 #endif
  60 #define interrupt_mask_set(n) do { \
  61         int __n = (n); \
  62         int __mask = 1 << (__n & 0x1f); \
  63         if (__n < 32) \
  64                 __insn_mtspr(SPR_INTERRUPT_MASK_SET_K_0, __mask); \
  65         else \
  66                 __insn_mtspr(SPR_INTERRUPT_MASK_SET_K_1, __mask); \
  67 } while (0)
  68 #define interrupt_mask_reset(n) do { \
  69         int __n = (n); \
  70         int __mask = 1 << (__n & 0x1f); \
  71         if (__n < 32) \
  72                 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_0, __mask); \
  73         else \
  74                 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_1, __mask); \
  75 } while (0)
  76 #define interrupt_mask_check(n) ({ \
  77         int __n = (n); \
  78         (((__n < 32) ? \
  79          __insn_mfspr(SPR_INTERRUPT_MASK_K_0) : \
  80          __insn_mfspr(SPR_INTERRUPT_MASK_K_1)) \
  81           >> (__n & 0x1f)) & 1; \
  82 })
  83 #define interrupt_mask_set_mask(mask) do { \
  84         unsigned long long __m = (mask); \
  85         __insn_mtspr(SPR_INTERRUPT_MASK_SET_K_0, (unsigned long)(__m)); \
  86         __insn_mtspr(SPR_INTERRUPT_MASK_SET_K_1, (unsigned long)(__m>>32)); \
  87 } while (0)
  88 #define interrupt_mask_reset_mask(mask) do { \
  89         unsigned long long __m = (mask); \
  90         __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_0, (unsigned long)(__m)); \
  91         __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_1, (unsigned long)(__m>>32)); \
  92 } while (0)
  93 #else
  94 #define interrupt_mask_set(n) \
  95         __insn_mtspr(SPR_INTERRUPT_MASK_SET_K, (1UL << (n)))
  96 #define interrupt_mask_reset(n) \
  97         __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K, (1UL << (n)))
  98 #define interrupt_mask_check(n) \
  99         ((__insn_mfspr(SPR_INTERRUPT_MASK_K) >> (n)) & 1)
 100 #define interrupt_mask_set_mask(mask) \
 101         __insn_mtspr(SPR_INTERRUPT_MASK_SET_K, (mask))
 102 #define interrupt_mask_reset_mask(mask) \
 103         __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K, (mask))
 104 #endif
 105
 106 /*
 107  * The set of interrupts we want active if irqs are enabled.
 108  * Note that in particular, the tile timer interrupt comes and goes
 109  * from this set, since we have no other way to turn off the timer.
 110  * Likewise, INTCTRL_K is removed and re-added during device
 111  * interrupts, as is the the hardwall UDN_FIREWALL interrupt.
 112  * We use a low bit (MEM_ERROR) as our sentinel value and make sure it
 113  * is always claimed as an "active interrupt" so we can query that bit
 114  * to know our current state.
 115  */
 116 DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
 117 #define INITIAL_INTERRUPTS_ENABLED INT_MASK(INT_MEM_ERROR)
 118
 119 /* Disable interrupts. */
 120 #define arch_local_irq_disable() \
 121         interrupt_mask_set_mask(LINUX_MASKABLE_INTERRUPTS)
 122
 123 /* Disable all interrupts, including NMIs. */
 124 #define arch_local_irq_disable_all() \
 125         interrupt_mask_set_mask(-1UL)
 126
 127 /* Re-enable all maskable interrupts. */
 128 #define arch_local_irq_enable() \
 129         interrupt_mask_reset_mask(__get_cpu_var(interrupts_enabled_mask))
 130
 131 /* Disable or enable interrupts based on flag argument. */
 132 #define arch_local_irq_restore(disabled) do { \
 133         if (disabled) \
 134                 arch_local_irq_disable(); \
 135         else \
 136                 arch_local_irq_enable(); \
 137 } while (0)
 138
 139 /* Return true if "flags" argument means interrupts are disabled. */
 140 #define arch_irqs_disabled_flags(flags) ((flags) != 0)
 141
 142 /* Return true if interrupts are currently disabled. */
 143 #define arch_irqs_disabled() interrupt_mask_check(INT_MEM_ERROR)
 144
 145 /* Save whether interrupts are currently disabled. */
 146 #define arch_local_save_flags() arch_irqs_disabled()
 147
 148 /* Save whether interrupts are currently disabled, then disable them. */
 149 #define arch_local_irq_save() ({ \
 150         unsigned long __flags = arch_local_save_flags(); \
 151         arch_local_irq_disable(); \
 152         __flags; })
 153
 154 /* Prevent the given interrupt from being enabled next time we enable irqs. */
 155 #define arch_local_irq_mask(interrupt) \
 156         (__get_cpu_var(interrupts_enabled_mask) &= ~INT_MASK(interrupt))
 157
 158 /* Prevent the given interrupt from being enabled immediately. */
 159 #define arch_local_irq_mask_now(interrupt) do { \
 160         arch_local_irq_mask(interrupt); \
 161         interrupt_mask_set(interrupt); \
 162 } while (0)
 163
 164 /* Allow the given interrupt to be enabled next time we enable irqs. */
 165 #define arch_local_irq_unmask(interrupt) \
 166         (__get_cpu_var(interrupts_enabled_mask) |= INT_MASK(interrupt))
 167
 168 /* Allow the given interrupt to be enabled immediately, if !irqs_disabled. */
 169 #define arch_local_irq_unmask_now(interrupt) do { \
 170         arch_local_irq_unmask(interrupt); \
 171         if (!irqs_disabled()) \
 172                 interrupt_mask_reset(interrupt); \
 173 } while (0)
 174
 175 #else /* __ASSEMBLY__ */
 176
 177 /* We provide a somewhat more restricted set for assembly. */
 178
 179 #ifdef __tilegx__
 180
 181 #if INT_MEM_ERROR != 0
 182 # error Fix IRQ_DISABLED() macro
 183 #endif
 184
 185 /* Return 0 or 1 to indicate whether interrupts are currently disabled. */
 186 #define IRQS_DISABLED(tmp)                                      \
 187         mfspr   tmp, SPR_INTERRUPT_MASK_K;                      \
 188         andi    tmp, tmp, 1
 189
 190 /* Load up a pointer to &interrupts_enabled_mask. */
 191 #define GET_INTERRUPTS_ENABLED_MASK_PTR(reg)                    \
 192         moveli reg, hw2_last(interrupts_enabled_mask);          \
 193         shl16insli reg, reg, hw1(interrupts_enabled_mask);      \
 194         shl16insli reg, reg, hw0(interrupts_enabled_mask);      \
 195         add     reg, reg, tp
 196
 197 /* Disable interrupts. */
 198 #define IRQ_DISABLE(tmp0, tmp1)                                 \
 199         moveli  tmp0, hw2_last(LINUX_MASKABLE_INTERRUPTS);      \
 200         shl16insli tmp0, tmp0, hw1(LINUX_MASKABLE_INTERRUPTS);  \
 201         shl16insli tmp0, tmp0, hw0(LINUX_MASKABLE_INTERRUPTS);  \
 202         mtspr   SPR_INTERRUPT_MASK_SET_K, tmp0
 203
 204 /* Disable ALL synchronous interrupts (used by NMI entry). */
 205 #define IRQ_DISABLE_ALL(tmp)                                    \
 206         movei   tmp, -1;                                        \
 207         mtspr   SPR_INTERRUPT_MASK_SET_K, tmp
 208
 209 /* Enable interrupts. */
 210 #define IRQ_ENABLE(tmp0, tmp1)                                  \
 211         GET_INTERRUPTS_ENABLED_MASK_PTR(tmp0);                  \
 212         ld      tmp0, tmp0;                                     \
 213         mtspr   SPR_INTERRUPT_MASK_RESET_K, tmp0
 214
 215 #else /* !__tilegx__ */
 216
 217 /*
 218  * Return 0 or 1 to indicate whether interrupts are currently disabled.
 219  * Note that it's important that we use a bit from the "low" mask word,
 220  * since when we are enabling, that is the word we write first, so if we
 221  * are interrupted after only writing half of the mask, the interrupt
 222  * handler will correctly observe that we have interrupts enabled, and
 223  * will enable interrupts itself on return from the interrupt handler
 224  * (making the original code's write of the "high" mask word idempotent).
 225  */
 226 #define IRQS_DISABLED(tmp)                                      \
 227         mfspr   tmp, SPR_INTERRUPT_MASK_K_0;                    \
 228         shri    tmp, tmp, INT_MEM_ERROR;                        \
 229         andi    tmp, tmp, 1
 230
 231 /* Load up a pointer to &interrupts_enabled_mask. */
 232 #define GET_INTERRUPTS_ENABLED_MASK_PTR(reg)                    \
 233         moveli  reg, lo16(interrupts_enabled_mask);             \
 234         auli    reg, reg, ha16(interrupts_enabled_mask);        \
 235         add     reg, reg, tp
 236
 237 /* Disable interrupts. */
 238 #define IRQ_DISABLE(tmp0, tmp1)                                 \
 239         {                                                       \
 240          movei  tmp0, -1;                                       \
 241          moveli tmp1, lo16(LINUX_MASKABLE_INTERRUPTS_HI)        \
 242         };                                                      \
 243         {                                                       \
 244          mtspr  SPR_INTERRUPT_MASK_SET_K_0, tmp0;               \
 245          auli   tmp1, tmp1, ha16(LINUX_MASKABLE_INTERRUPTS_HI)  \
 246         };                                                      \
 247         mtspr   SPR_INTERRUPT_MASK_SET_K_1, tmp1
 248
 249 /* Disable ALL synchronous interrupts (used by NMI entry). */
 250 #define IRQ_DISABLE_ALL(tmp)                                    \
 251         movei   tmp, -1;                                        \
 252         mtspr   SPR_INTERRUPT_MASK_SET_K_0, tmp;                \
 253         mtspr   SPR_INTERRUPT_MASK_SET_K_1, tmp
 254
 255 /* Enable interrupts. */
 256 #define IRQ_ENABLE(tmp0, tmp1)                                  \
 257         GET_INTERRUPTS_ENABLED_MASK_PTR(tmp0);                  \
 258         {                                                       \
 259          lw     tmp0, tmp0;                                     \
 260          addi   tmp1, tmp0, 4                                   \
 261         };                                                      \
 262         lw      tmp1, tmp1;                                     \
 263         mtspr   SPR_INTERRUPT_MASK_RESET_K_0, tmp0;             \
 264         mtspr   SPR_INTERRUPT_MASK_RESET_K_1, tmp1
 265 #endif
 266
 267 /*
 268  * Do the CPU's IRQ-state tracing from assembly code. We call a
 269  * C function, but almost everywhere we do, we don't mind clobbering
 270  * all the caller-saved registers.
 271  */
 272 #ifdef CONFIG_TRACE_IRQFLAGS
 273 # define TRACE_IRQS_ON  jal trace_hardirqs_on
 274 # define TRACE_IRQS_OFF jal trace_hardirqs_off
 275 #else
 276 # define TRACE_IRQS_ON
 277 # define TRACE_IRQS_OFF
 278 #endif
 279
 280 #endif /* __ASSEMBLY__ */
 281
 282 #endif /* _ASM_TILE_IRQFLAGS_H */