include/drm/i915_drm.h

   1 /*
   2  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  20  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #ifndef _I915_DRM_H_
  28 #define _I915_DRM_H_
  29
  30 #include "drm.h"
  31
  32 /* Please note that modifications to all structs defined here are
  33  * subject to backwards-compatibility constraints.
  34  */
  35
  36 #ifdef __KERNEL__
  37 /* For use by IPS driver */
  38 extern unsigned long i915_read_mch_val(void);
  39 extern bool i915_gpu_raise(void);
  40 extern bool i915_gpu_lower(void);
  41 extern bool i915_gpu_busy(void);
  42 extern bool i915_gpu_turbo_disable(void);
  43 #endif
  44
  45 /* Each region is a minimum of 16k, and there are at most 255 of them.
  46  */
  47 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
  48                                  * of chars for next/prev indices */
  49 #define I915_LOG_MIN_TEX_REGION_SIZE 14
  50
  51 typedef struct _drm_i915_init {
  52         enum {
  53                 I915_INIT_DMA = 0x01,
  54                 I915_CLEANUP_DMA = 0x02,
  55                 I915_RESUME_DMA = 0x03
  56         } func;
  57         unsigned int mmio_offset;
  58         int sarea_priv_offset;
  59         unsigned int ring_start;
  60         unsigned int ring_end;
  61         unsigned int ring_size;
  62         unsigned int front_offset;
  63         unsigned int back_offset;
  64         unsigned int depth_offset;
  65         unsigned int w;
  66         unsigned int h;
  67         unsigned int pitch;
  68         unsigned int pitch_bits;
  69         unsigned int back_pitch;
  70         unsigned int depth_pitch;
  71         unsigned int cpp;
  72         unsigned int chipset;
  73 } drm_i915_init_t;
  74
  75 typedef struct _drm_i915_sarea {
  76         struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
  77         int last_upload;        /* last time texture was uploaded */
  78         int last_enqueue;       /* last time a buffer was enqueued */
  79         int last_dispatch;      /* age of the most recently dispatched buffer */
  80         int ctxOwner;           /* last context to upload state */
  81         int texAge;
  82         int pf_enabled;         /* is pageflipping allowed? */
  83         int pf_active;
  84         int pf_current_page;    /* which buffer is being displayed? */
  85         int perf_boxes;         /* performance boxes to be displayed */
  86         int width, height;      /* screen size in pixels */
  87
  88         drm_handle_t front_handle;
  89         int front_offset;
  90         int front_size;
  91
  92         drm_handle_t back_handle;
  93         int back_offset;
  94         int back_size;
  95
  96         drm_handle_t depth_handle;
  97         int depth_offset;
  98         int depth_size;
  99
 100         drm_handle_t tex_handle;
 101         int tex_offset;
 102         int tex_size;
 103         int log_tex_granularity;
 104         int pitch;
 105         int rotation;           /* 0, 90, 180 or 270 */
 106         int rotated_offset;
 107         int rotated_size;
 108         int rotated_pitch;
 109         int virtualX, virtualY;
 110
 111         unsigned int front_tiled;
 112         unsigned int back_tiled;
 113         unsigned int depth_tiled;
 114         unsigned int rotated_tiled;
 115         unsigned int rotated2_tiled;
 116
 117         int pipeA_x;
 118         int pipeA_y;
 119         int pipeA_w;
 120         int pipeA_h;
 121         int pipeB_x;
 122         int pipeB_y;
 123         int pipeB_w;
 124         int pipeB_h;
 125
 126         /* fill out some space for old userspace triple buffer */
 127         drm_handle_t unused_handle;
 128         __u32 unused1, unused2, unused3;
 129
 130         /* buffer object handles for static buffers. May change
 131          * over the lifetime of the client.
 132          */
 133         __u32 front_bo_handle;
 134         __u32 back_bo_handle;
 135         __u32 unused_bo_handle;
 136         __u32 depth_bo_handle;
 137
 138 } drm_i915_sarea_t;
 139
 140 /* due to userspace building against these headers we need some compat here */
 141 #define planeA_x pipeA_x
 142 #define planeA_y pipeA_y
 143 #define planeA_w pipeA_w
 144 #define planeA_h pipeA_h
 145 #define planeB_x pipeB_x
 146 #define planeB_y pipeB_y
 147 #define planeB_w pipeB_w
 148 #define planeB_h pipeB_h
 149
 150 /* Flags for perf_boxes
 151  */
 152 #define I915_BOX_RING_EMPTY    0x1
 153 #define I915_BOX_FLIP          0x2
 154 #define I915_BOX_WAIT          0x4
 155 #define I915_BOX_TEXTURE_LOAD  0x8
 156 #define I915_BOX_LOST_CONTEXT  0x10
 157
 158 /* I915 specific ioctls
 159  * The device specific ioctl range is 0x40 to 0x79.
 160  */
 161 #define DRM_I915_INIT           0x00
 162 #define DRM_I915_FLUSH          0x01
 163 #define DRM_I915_FLIP           0x02
 164 #define DRM_I915_BATCHBUFFER    0x03
 165 #define DRM_I915_IRQ_EMIT       0x04
 166 #define DRM_I915_IRQ_WAIT       0x05
 167 #define DRM_I915_GETPARAM       0x06
 168 #define DRM_I915_SETPARAM       0x07
 169 #define DRM_I915_ALLOC          0x08
 170 #define DRM_I915_FREE           0x09
 171 #define DRM_I915_INIT_HEAP      0x0a
 172 #define DRM_I915_CMDBUFFER      0x0b
 173 #define DRM_I915_DESTROY_HEAP   0x0c
 174 #define DRM_I915_SET_VBLANK_PIPE        0x0d
 175 #define DRM_I915_GET_VBLANK_PIPE        0x0e
 176 #define DRM_I915_VBLANK_SWAP    0x0f
 177 #define DRM_I915_HWS_ADDR       0x11
 178 #define DRM_I915_GEM_INIT       0x13
 179 #define DRM_I915_GEM_EXECBUFFER 0x14
 180 #define DRM_I915_GEM_PIN        0x15
 181 #define DRM_I915_GEM_UNPIN      0x16
 182 #define DRM_I915_GEM_BUSY       0x17
 183 #define DRM_I915_GEM_THROTTLE   0x18
 184 #define DRM_I915_GEM_ENTERVT    0x19
 185 #define DRM_I915_GEM_LEAVEVT    0x1a
 186 #define DRM_I915_GEM_CREATE     0x1b
 187 #define DRM_I915_GEM_PREAD      0x1c
 188 #define DRM_I915_GEM_PWRITE     0x1d
 189 #define DRM_I915_GEM_MMAP       0x1e
 190 #define DRM_I915_GEM_SET_DOMAIN 0x1f
 191 #define DRM_I915_GEM_SW_FINISH  0x20
 192 #define DRM_I915_GEM_SET_TILING 0x21
 193 #define DRM_I915_GEM_GET_TILING 0x22
 194 #define DRM_I915_GEM_GET_APERTURE 0x23
 195 #define DRM_I915_GEM_MMAP_GTT   0x24
 196 #define DRM_I915_GET_PIPE_FROM_CRTC_ID  0x25
 197 #define DRM_I915_GEM_MADVISE    0x26
 198 #define DRM_I915_OVERLAY_PUT_IMAGE      0x27
 199 #define DRM_I915_OVERLAY_ATTRS  0x28
 200 #define DRM_I915_GEM_EXECBUFFER2        0x29
 201 #define DRM_I915_GET_SPRITE_COLORKEY    0x2a
 202 #define DRM_I915_SET_SPRITE_COLORKEY    0x2b
 203
 204 #define DRM_IOCTL_I915_INIT             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 205 #define DRM_IOCTL_I915_FLUSH            DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
 206 #define DRM_IOCTL_I915_FLIP             DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
 207 #define DRM_IOCTL_I915_BATCHBUFFER      DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
 208 #define DRM_IOCTL_I915_IRQ_EMIT         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
 209 #define DRM_IOCTL_I915_IRQ_WAIT         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
 210 #define DRM_IOCTL_I915_GETPARAM         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
 211 #define DRM_IOCTL_I915_SETPARAM         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
 212 #define DRM_IOCTL_I915_ALLOC            DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
 213 #define DRM_IOCTL_I915_FREE             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
 214 #define DRM_IOCTL_I915_INIT_HEAP        DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
 215 #define DRM_IOCTL_I915_CMDBUFFER        DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
 216 #define DRM_IOCTL_I915_DESTROY_HEAP     DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
 217 #define DRM_IOCTL_I915_SET_VBLANK_PIPE  DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
 218 #define DRM_IOCTL_I915_GET_VBLANK_PIPE  DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
 219 #define DRM_IOCTL_I915_VBLANK_SWAP      DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
 220 #define DRM_IOCTL_I915_HWS_ADDR         DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
 221 #define DRM_IOCTL_I915_GEM_INIT         DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
 222 #define DRM_IOCTL_I915_GEM_EXECBUFFER   DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
 223 #define DRM_IOCTL_I915_GEM_EXECBUFFER2  DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
 224 #define DRM_IOCTL_I915_GEM_PIN          DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
 225 #define DRM_IOCTL_I915_GEM_UNPIN        DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
 226 #define DRM_IOCTL_I915_GEM_BUSY         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
 227 #define DRM_IOCTL_I915_GEM_THROTTLE     DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
 228 #define DRM_IOCTL_I915_GEM_ENTERVT      DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
 229 #define DRM_IOCTL_I915_GEM_LEAVEVT      DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
 230 #define DRM_IOCTL_I915_GEM_CREATE       DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
 231 #define DRM_IOCTL_I915_GEM_PREAD        DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
 232 #define DRM_IOCTL_I915_GEM_PWRITE       DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
 233 #define DRM_IOCTL_I915_GEM_MMAP         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
 234 #define DRM_IOCTL_I915_GEM_MMAP_GTT     DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
 235 #define DRM_IOCTL_I915_GEM_SET_DOMAIN   DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
 236 #define DRM_IOCTL_I915_GEM_SW_FINISH    DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
 237 #define DRM_IOCTL_I915_GEM_SET_TILING   DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
 238 #define DRM_IOCTL_I915_GEM_GET_TILING   DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
 239 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR  (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
 240 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
 241 #define DRM_IOCTL_I915_GEM_MADVISE      DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
 242 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE        DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
 243 #define DRM_IOCTL_I915_OVERLAY_ATTRS    DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
 244 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
 245 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
 246
 247 /* Allow drivers to submit batchbuffers directly to hardware, relying
 248  * on the security mechanisms provided by hardware.
 249  */
 250 typedef struct drm_i915_batchbuffer {
 251         int start;              /* agp offset */
 252         int used;               /* nr bytes in use */
 253         int DR1;                /* hw flags for GFX_OP_DRAWRECT_INFO */
 254         int DR4;                /* window origin for GFX_OP_DRAWRECT_INFO */
 255         int num_cliprects;      /* mulitpass with multiple cliprects? */
 256         struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
 257 } drm_i915_batchbuffer_t;
 258
 259 /* As above, but pass a pointer to userspace buffer which can be
 260  * validated by the kernel prior to sending to hardware.
 261  */
 262 typedef struct _drm_i915_cmdbuffer {
 263         char __user *buf;       /* pointer to userspace command buffer */
 264         int sz;                 /* nr bytes in buf */
 265         int DR1;                /* hw flags for GFX_OP_DRAWRECT_INFO */
 266         int DR4;                /* window origin for GFX_OP_DRAWRECT_INFO */
 267         int num_cliprects;      /* mulitpass with multiple cliprects? */
 268         struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
 269 } drm_i915_cmdbuffer_t;
 270
 271 /* Userspace can request & wait on irq's:
 272  */
 273 typedef struct drm_i915_irq_emit {
 274         int __user *irq_seq;
 275 } drm_i915_irq_emit_t;
 276
 277 typedef struct drm_i915_irq_wait {
 278         int irq_seq;
 279 } drm_i915_irq_wait_t;
 280
 281 /* Ioctl to query kernel params:
 282  */
 283 #define I915_PARAM_IRQ_ACTIVE            1
 284 #define I915_PARAM_ALLOW_BATCHBUFFER     2
 285 #define I915_PARAM_LAST_DISPATCH         3
 286 #define I915_PARAM_CHIPSET_ID            4
 287 #define I915_PARAM_HAS_GEM               5
 288 #define I915_PARAM_NUM_FENCES_AVAIL      6
 289 #define I915_PARAM_HAS_OVERLAY           7
 290 #define I915_PARAM_HAS_PAGEFLIPPING      8
 291 #define I915_PARAM_HAS_EXECBUF2          9
 292 #define I915_PARAM_HAS_BSD               10
 293 #define I915_PARAM_HAS_BLT               11
 294 #define I915_PARAM_HAS_RELAXED_FENCING   12
 295 #define I915_PARAM_HAS_COHERENT_RINGS    13
 296 #define I915_PARAM_HAS_EXEC_CONSTANTS    14
 297 #define I915_PARAM_HAS_RELAXED_DELTA     15
 298 #define I915_PARAM_HAS_GEN7_SOL_RESET    16
 299
 300 typedef struct drm_i915_getparam {
 301         int param;
 302         int __user *value;
 303 } drm_i915_getparam_t;
 304
 305 /* Ioctl to set kernel params:
 306  */
 307 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START            1
 308 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY             2
 309 #define I915_SETPARAM_ALLOW_BATCHBUFFER                   3
 310 #define I915_SETPARAM_NUM_USED_FENCES                     4
 311
 312 typedef struct drm_i915_setparam {
 313         int param;
 314         int value;
 315 } drm_i915_setparam_t;
 316
 317 /* A memory manager for regions of shared memory:
 318  */
 319 #define I915_MEM_REGION_AGP 1
 320
 321 typedef struct drm_i915_mem_alloc {
 322         int region;
 323         int alignment;
 324         int size;
 325         int __user *region_offset;      /* offset from start of fb or agp */
 326 } drm_i915_mem_alloc_t;
 327
 328 typedef struct drm_i915_mem_free {
 329         int region;
 330         int region_offset;
 331 } drm_i915_mem_free_t;
 332
 333 typedef struct drm_i915_mem_init_heap {
 334         int region;
 335         int size;
 336         int start;
 337 } drm_i915_mem_init_heap_t;
 338
 339 /* Allow memory manager to be torn down and re-initialized (eg on
 340  * rotate):
 341  */
 342 typedef struct drm_i915_mem_destroy_heap {
 343         int region;
 344 } drm_i915_mem_destroy_heap_t;
 345
 346 /* Allow X server to configure which pipes to monitor for vblank signals
 347  */
 348 #define DRM_I915_VBLANK_PIPE_A  1
 349 #define DRM_I915_VBLANK_PIPE_B  2
 350
 351 typedef struct drm_i915_vblank_pipe {
 352         int pipe;
 353 } drm_i915_vblank_pipe_t;
 354
 355 /* Schedule buffer swap at given vertical blank:
 356  */
 357 typedef struct drm_i915_vblank_swap {
 358         drm_drawable_t drawable;
 359         enum drm_vblank_seq_type seqtype;
 360         unsigned int sequence;
 361 } drm_i915_vblank_swap_t;
 362
 363 typedef struct drm_i915_hws_addr {
 364         __u64 addr;
 365 } drm_i915_hws_addr_t;
 366
 367 struct drm_i915_gem_init {
 368         /**
 369          * Beginning offset in the GTT to be managed by the DRM memory
 370          * manager.
 371          */
 372         __u64 gtt_start;
 373         /**
 374          * Ending offset in the GTT to be managed by the DRM memory
 375          * manager.
 376          */
 377         __u64 gtt_end;
 378 };
 379
 380 struct drm_i915_gem_create {
 381         /**
 382          * Requested size for the object.
 383          *
 384          * The (page-aligned) allocated size for the object will be returned.
 385          */
 386         __u64 size;
 387         /**
 388          * Returned handle for the object.
 389          *
 390          * Object handles are nonzero.
 391          */
 392         __u32 handle;
 393         __u32 pad;
 394 };
 395
 396 struct drm_i915_gem_pread {
 397         /** Handle for the object being read. */
 398         __u32 handle;
 399         __u32 pad;
 400         /** Offset into the object to read from */
 401         __u64 offset;
 402         /** Length of data to read */
 403         __u64 size;
 404         /**
 405          * Pointer to write the data into.
 406          *
 407          * This is a fixed-size type for 32/64 compatibility.
 408          */
 409         __u64 data_ptr;
 410 };
 411
 412 struct drm_i915_gem_pwrite {
 413         /** Handle for the object being written to. */
 414         __u32 handle;
 415         __u32 pad;
 416         /** Offset into the object to write to */
 417         __u64 offset;
 418         /** Length of data to write */
 419         __u64 size;
 420         /**
 421          * Pointer to read the data from.
 422          *
 423          * This is a fixed-size type for 32/64 compatibility.
 424          */
 425         __u64 data_ptr;
 426 };
 427
 428 struct drm_i915_gem_mmap {
 429         /** Handle for the object being mapped. */
 430         __u32 handle;
 431         __u32 pad;
 432         /** Offset in the object to map. */
 433         __u64 offset;
 434         /**
 435          * Length of data to map.
 436          *
 437          * The value will be page-aligned.
 438          */
 439         __u64 size;
 440         /**
 441          * Returned pointer the data was mapped at.
 442          *
 443          * This is a fixed-size type for 32/64 compatibility.
 444          */
 445         __u64 addr_ptr;
 446 };
 447
 448 struct drm_i915_gem_mmap_gtt {
 449         /** Handle for the object being mapped. */
 450         __u32 handle;
 451         __u32 pad;
 452         /**
 453          * Fake offset to use for subsequent mmap call
 454          *
 455          * This is a fixed-size type for 32/64 compatibility.
 456          */
 457         __u64 offset;
 458 };
 459
 460 struct drm_i915_gem_set_domain {
 461         /** Handle for the object */
 462         __u32 handle;
 463
 464         /** New read domains */
 465         __u32 read_domains;
 466
 467         /** New write domain */
 468         __u32 write_domain;
 469 };
 470
 471 struct drm_i915_gem_sw_finish {
 472         /** Handle for the object */
 473         __u32 handle;
 474 };
 475
 476 struct drm_i915_gem_relocation_entry {
 477         /**
 478          * Handle of the buffer being pointed to by this relocation entry.
 479          *
 480          * It's appealing to make this be an index into the mm_validate_entry
 481          * list to refer to the buffer, but this allows the driver to create
 482          * a relocation list for state buffers and not re-write it per
 483          * exec using the buffer.
 484          */
 485         __u32 target_handle;
 486
 487         /**
 488          * Value to be added to the offset of the target buffer to make up
 489          * the relocation entry.
 490          */
 491         __u32 delta;
 492
 493         /** Offset in the buffer the relocation entry will be written into */
 494         __u64 offset;
 495
 496         /**
 497          * Offset value of the target buffer that the relocation entry was last
 498          * written as.
 499          *
 500          * If the buffer has the same offset as last time, we can skip syncing
 501          * and writing the relocation.  This value is written back out by
 502          * the execbuffer ioctl when the relocation is written.
 503          */
 504         __u64 presumed_offset;
 505
 506         /**
 507          * Target memory domains read by this operation.
 508          */
 509         __u32 read_domains;
 510
 511         /**
 512          * Target memory domains written by this operation.
 513          *
 514          * Note that only one domain may be written by the whole
 515          * execbuffer operation, so that where there are conflicts,
 516          * the application will get -EINVAL back.
 517          */
 518         __u32 write_domain;
 519 };
 520
 521 /** @{
 522  * Intel memory domains
 523  *
 524  * Most of these just align with the various caches in
 525  * the system and are used to flush and invalidate as
 526  * objects end up cached in different domains.
 527  */
 528 /** CPU cache */
 529 #define I915_GEM_DOMAIN_CPU             0x00000001
 530 /** Render cache, used by 2D and 3D drawing */
 531 #define I915_GEM_DOMAIN_RENDER          0x00000002
 532 /** Sampler cache, used by texture engine */
 533 #define I915_GEM_DOMAIN_SAMPLER         0x00000004
 534 /** Command queue, used to load batch buffers */
 535 #define I915_GEM_DOMAIN_COMMAND         0x00000008
 536 /** Instruction cache, used by shader programs */
 537 #define I915_GEM_DOMAIN_INSTRUCTION     0x00000010
 538 /** Vertex address cache */
 539 #define I915_GEM_DOMAIN_VERTEX          0x00000020
 540 /** GTT domain - aperture and scanout */
 541 #define I915_GEM_DOMAIN_GTT             0x00000040
 542 /** @} */
 543
 544 struct drm_i915_gem_exec_object {
 545         /**
 546          * User's handle for a buffer to be bound into the GTT for this
 547          * operation.
 548          */
 549         __u32 handle;
 550
 551         /** Number of relocations to be performed on this buffer */
 552         __u32 relocation_count;
 553         /**
 554          * Pointer to array of struct drm_i915_gem_relocation_entry containing
 555          * the relocations to be performed in this buffer.
 556          */
 557         __u64 relocs_ptr;
 558
 559         /** Required alignment in graphics aperture */
 560         __u64 alignment;
 561
 562         /**
 563          * Returned value of the updated offset of the object, for future
 564          * presumed_offset writes.
 565          */
 566         __u64 offset;
 567 };
 568
 569 struct drm_i915_gem_execbuffer {
 570         /**
 571          * List of buffers to be validated with their relocations to be
 572          * performend on them.
 573          *
 574          * This is a pointer to an array of struct drm_i915_gem_validate_entry.
 575          *
 576          * These buffers must be listed in an order such that all relocations
 577          * a buffer is performing refer to buffers that have already appeared
 578          * in the validate list.
 579          */
 580         __u64 buffers_ptr;
 581         __u32 buffer_count;
 582
 583         /** Offset in the batchbuffer to start execution from. */
 584         __u32 batch_start_offset;
 585         /** Bytes used in batchbuffer from batch_start_offset */
 586         __u32 batch_len;
 587         __u32 DR1;
 588         __u32 DR4;
 589         __u32 num_cliprects;
 590         /** This is a struct drm_clip_rect *cliprects */
 591         __u64 cliprects_ptr;
 592 };
 593
 594 struct drm_i915_gem_exec_object2 {
 595         /**
 596          * User's handle for a buffer to be bound into the GTT for this
 597          * operation.
 598          */
 599         __u32 handle;
 600
 601         /** Number of relocations to be performed on this buffer */
 602         __u32 relocation_count;
 603         /**
 604          * Pointer to array of struct drm_i915_gem_relocation_entry containing
 605          * the relocations to be performed in this buffer.
 606          */
 607         __u64 relocs_ptr;
 608
 609         /** Required alignment in graphics aperture */
 610         __u64 alignment;
 611
 612         /**
 613          * Returned value of the updated offset of the object, for future
 614          * presumed_offset writes.
 615          */
 616         __u64 offset;
 617
 618 #define EXEC_OBJECT_NEEDS_FENCE (1<<0)
 619         __u64 flags;
 620         __u64 rsvd1;
 621         __u64 rsvd2;
 622 };
 623
 624 struct drm_i915_gem_execbuffer2 {
 625         /**
 626          * List of gem_exec_object2 structs
 627          */
 628         __u64 buffers_ptr;
 629         __u32 buffer_count;
 630
 631         /** Offset in the batchbuffer to start execution from. */
 632         __u32 batch_start_offset;
 633         /** Bytes used in batchbuffer from batch_start_offset */
 634         __u32 batch_len;
 635         __u32 DR1;
 636         __u32 DR4;
 637         __u32 num_cliprects;
 638         /** This is a struct drm_clip_rect *cliprects */
 639         __u64 cliprects_ptr;
 640 #define I915_EXEC_RING_MASK              (7<<0)
 641 #define I915_EXEC_DEFAULT                (0<<0)
 642 #define I915_EXEC_RENDER                 (1<<0)
 643 #define I915_EXEC_BSD                    (2<<0)
 644 #define I915_EXEC_BLT                    (3<<0)
 645
 646 /* Used for switching the constants addressing mode on gen4+ RENDER ring.
 647  * Gen6+ only supports relative addressing to dynamic state (default) and
 648  * absolute addressing.
 649  *
 650  * These flags are ignored for the BSD and BLT rings.
 651  */
 652 #define I915_EXEC_CONSTANTS_MASK        (3<<6)
 653 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
 654 #define I915_EXEC_CONSTANTS_ABSOLUTE    (1<<6)
 655 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
 656         __u64 flags;
 657         __u64 rsvd1;
 658         __u64 rsvd2;
 659 };
 660
 661 /** Resets the SO write offset registers for transform feedback on gen7. */
 662 #define I915_EXEC_GEN7_SOL_RESET        (1<<8)
 663
 664 struct drm_i915_gem_pin {
 665         /** Handle of the buffer to be pinned. */
 666         __u32 handle;
 667         __u32 pad;
 668
 669         /** alignment required within the aperture */
 670         __u64 alignment;
 671
 672         /** Returned GTT offset of the buffer. */
 673         __u64 offset;
 674 };
 675
 676 struct drm_i915_gem_unpin {
 677         /** Handle of the buffer to be unpinned. */
 678         __u32 handle;
 679         __u32 pad;
 680 };
 681
 682 struct drm_i915_gem_busy {
 683         /** Handle of the buffer to check for busy */
 684         __u32 handle;
 685
 686         /** Return busy status (1 if busy, 0 if idle) */
 687         __u32 busy;
 688 };
 689
 690 #define I915_TILING_NONE        0
 691 #define I915_TILING_X           1
 692 #define I915_TILING_Y           2
 693
 694 #define I915_BIT_6_SWIZZLE_NONE         0
 695 #define I915_BIT_6_SWIZZLE_9            1
 696 #define I915_BIT_6_SWIZZLE_9_10         2
 697 #define I915_BIT_6_SWIZZLE_9_11         3
 698 #define I915_BIT_6_SWIZZLE_9_10_11      4
 699 /* Not seen by userland */
 700 #define I915_BIT_6_SWIZZLE_UNKNOWN      5
 701 /* Seen by userland. */
 702 #define I915_BIT_6_SWIZZLE_9_17         6
 703 #define I915_BIT_6_SWIZZLE_9_10_17      7
 704
 705 struct drm_i915_gem_set_tiling {
 706         /** Handle of the buffer to have its tiling state updated */
 707         __u32 handle;
 708
 709         /**
 710          * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
 711          * I915_TILING_Y).
 712          *
 713          * This value is to be set on request, and will be updated by the
 714          * kernel on successful return with the actual chosen tiling layout.
 715          *
 716          * The tiling mode may be demoted to I915_TILING_NONE when the system
 717          * has bit 6 swizzling that can't be managed correctly by GEM.
 718          *
 719          * Buffer contents become undefined when changing tiling_mode.
 720          */
 721         __u32 tiling_mode;
 722
 723         /**
 724          * Stride in bytes for the object when in I915_TILING_X or
 725          * I915_TILING_Y.
 726          */
 727         __u32 stride;
 728
 729         /**
 730          * Returned address bit 6 swizzling required for CPU access through
 731          * mmap mapping.
 732          */
 733         __u32 swizzle_mode;
 734 };
 735
 736 struct drm_i915_gem_get_tiling {
 737         /** Handle of the buffer to get tiling state for. */
 738         __u32 handle;
 739
 740         /**
 741          * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
 742          * I915_TILING_Y).
 743          */
 744         __u32 tiling_mode;
 745
 746         /**
 747          * Returned address bit 6 swizzling required for CPU access through
 748          * mmap mapping.
 749          */
 750         __u32 swizzle_mode;
 751 };
 752
 753 struct drm_i915_gem_get_aperture {
 754         /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
 755         __u64 aper_size;
 756
 757         /**
 758          * Available space in the aperture used by i915_gem_execbuffer, in
 759          * bytes
 760          */
 761         __u64 aper_available_size;
 762 };
 763
 764 struct drm_i915_get_pipe_from_crtc_id {
 765         /** ID of CRTC being requested **/
 766         __u32 crtc_id;
 767
 768         /** pipe of requested CRTC **/
 769         __u32 pipe;
 770 };
 771
 772 #define I915_MADV_WILLNEED 0
 773 #define I915_MADV_DONTNEED 1
 774 #define __I915_MADV_PURGED 2 /* internal state */
 775
 776 struct drm_i915_gem_madvise {
 777         /** Handle of the buffer to change the backing store advice */
 778         __u32 handle;
 779
 780         /* Advice: either the buffer will be needed again in the near future,
 781          *         or wont be and could be discarded under memory pressure.
 782          */
 783         __u32 madv;
 784
 785         /** Whether the backing store still exists. */
 786         __u32 retained;
 787 };
 788
 789 /* flags */
 790 #define I915_OVERLAY_TYPE_MASK          0xff
 791 #define I915_OVERLAY_YUV_PLANAR         0x01
 792 #define I915_OVERLAY_YUV_PACKED         0x02
 793 #define I915_OVERLAY_RGB                0x03
 794
 795 #define I915_OVERLAY_DEPTH_MASK         0xff00
 796 #define I915_OVERLAY_RGB24              0x1000
 797 #define I915_OVERLAY_RGB16              0x2000
 798 #define I915_OVERLAY_RGB15              0x3000
 799 #define I915_OVERLAY_YUV422             0x0100
 800 #define I915_OVERLAY_YUV411             0x0200
 801 #define I915_OVERLAY_YUV420             0x0300
 802 #define I915_OVERLAY_YUV410             0x0400
 803
 804 #define I915_OVERLAY_SWAP_MASK          0xff0000
 805 #define I915_OVERLAY_NO_SWAP            0x000000
 806 #define I915_OVERLAY_UV_SWAP            0x010000
 807 #define I915_OVERLAY_Y_SWAP             0x020000
 808 #define I915_OVERLAY_Y_AND_UV_SWAP      0x030000
 809
 810 #define I915_OVERLAY_FLAGS_MASK         0xff000000
 811 #define I915_OVERLAY_ENABLE             0x01000000
 812
 813 struct drm_intel_overlay_put_image {
 814         /* various flags and src format description */
 815         __u32 flags;
 816         /* source picture description */
 817         __u32 bo_handle;
 818         /* stride values and offsets are in bytes, buffer relative */
 819         __u16 stride_Y; /* stride for packed formats */
 820         __u16 stride_UV;
 821         __u32 offset_Y; /* offset for packet formats */
 822         __u32 offset_U;
 823         __u32 offset_V;
 824         /* in pixels */
 825         __u16 src_width;
 826         __u16 src_height;
 827         /* to compensate the scaling factors for partially covered surfaces */
 828         __u16 src_scan_width;
 829         __u16 src_scan_height;
 830         /* output crtc description */
 831         __u32 crtc_id;
 832         __u16 dst_x;
 833         __u16 dst_y;
 834         __u16 dst_width;
 835         __u16 dst_height;
 836 };
 837
 838 /* flags */
 839 #define I915_OVERLAY_UPDATE_ATTRS       (1<<0)
 840 #define I915_OVERLAY_UPDATE_GAMMA       (1<<1)
 841 struct drm_intel_overlay_attrs {
 842         __u32 flags;
 843         __u32 color_key;
 844         __s32 brightness;
 845         __u32 contrast;
 846         __u32 saturation;
 847         __u32 gamma0;
 848         __u32 gamma1;
 849         __u32 gamma2;
 850         __u32 gamma3;
 851         __u32 gamma4;
 852         __u32 gamma5;
 853 };
 854
 855 /*
 856  * Intel sprite handling
 857  *
 858  * Color keying works with a min/mask/max tuple.  Both source and destination
 859  * color keying is allowed.
 860  *
 861  * Source keying:
 862  * Sprite pixels within the min & max values, masked against the color channels
 863  * specified in the mask field, will be transparent.  All other pixels will
 864  * be displayed on top of the primary plane.  For RGB surfaces, only the min
 865  * and mask fields will be used; ranged compares are not allowed.
 866  *
 867  * Destination keying:
 868  * Primary plane pixels that match the min value, masked against the color
 869  * channels specified in the mask field, will be replaced by corresponding
 870  * pixels from the sprite plane.
 871  *
 872  * Note that source & destination keying are exclusive; only one can be
 873  * active on a given plane.
 874  */
 875
 876 #define I915_SET_COLORKEY_NONE          (1<<0) /* disable color key matching */
 877 #define I915_SET_COLORKEY_DESTINATION   (1<<1)
 878 #define I915_SET_COLORKEY_SOURCE        (1<<2)
 879 struct drm_intel_sprite_colorkey {
 880         __u32 plane_id;
 881         __u32 min_value;
 882         __u32 channel_mask;
 883         __u32 max_value;
 884         __u32 flags;
 885 };
 886
 887 #endif                          /* _I915_DRM_H_ */