include/linux/amba/serial.h

   1 /*
   2  *  linux/include/asm-arm/hardware/serial_amba.h
   3  *
   4  *  Internal header file for AMBA serial ports
   5  *
   6  *  Copyright (C) ARM Limited
   7  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22  */
  23 #ifndef ASM_ARM_HARDWARE_SERIAL_AMBA_H
  24 #define ASM_ARM_HARDWARE_SERIAL_AMBA_H
  25
  26 #include <linux/types.h>
  27
  28 /* -------------------------------------------------------------------------------
  29  *  From AMBA UART (PL010) Block Specification
  30  * -------------------------------------------------------------------------------
  31  *  UART Register Offsets.
  32  */
  33 #define UART01x_DR              0x00    /* Data read or written from the interface. */
  34 #define UART01x_RSR             0x04    /* Receive status register (Read). */
  35 #define UART01x_ECR             0x04    /* Error clear register (Write). */
  36 #define UART010_LCRH            0x08    /* Line control register, high byte. */
  37 #define ST_UART011_DMAWM        0x08    /* DMA watermark configure register. */
  38 #define UART010_LCRM            0x0C    /* Line control register, middle byte. */
  39 #define ST_UART011_TIMEOUT      0x0C    /* Timeout period register. */
  40 #define UART010_LCRL            0x10    /* Line control register, low byte. */
  41 #define UART010_CR              0x14    /* Control register. */
  42 #define UART01x_FR              0x18    /* Flag register (Read only). */
  43 #define UART010_IIR             0x1C    /* Interrupt indentification register (Read). */
  44 #define UART010_ICR             0x1C    /* Interrupt clear register (Write). */
  45 #define ST_UART011_LCRH_RX      0x1C    /* Rx line control register. */
  46 #define UART01x_ILPR            0x20    /* IrDA low power counter register. */
  47 #define UART011_IBRD            0x24    /* Integer baud rate divisor register. */
  48 #define UART011_FBRD            0x28    /* Fractional baud rate divisor register. */
  49 #define UART011_LCRH            0x2c    /* Line control register. */
  50 #define ST_UART011_LCRH_TX      0x2c    /* Tx Line control register. */
  51 #define UART011_CR              0x30    /* Control register. */
  52 #define UART011_IFLS            0x34    /* Interrupt fifo level select. */
  53 #define UART011_IMSC            0x38    /* Interrupt mask. */
  54 #define UART011_RIS             0x3c    /* Raw interrupt status. */
  55 #define UART011_MIS             0x40    /* Masked interrupt status. */
  56 #define UART011_ICR             0x44    /* Interrupt clear register. */
  57 #define UART011_DMACR           0x48    /* DMA control register. */
  58 #define ST_UART011_XFCR         0x50    /* XON/XOFF control register. */
  59 #define ST_UART011_XON1         0x54    /* XON1 register. */
  60 #define ST_UART011_XON2         0x58    /* XON2 register. */
  61 #define ST_UART011_XOFF1        0x5C    /* XON1 register. */
  62 #define ST_UART011_XOFF2        0x60    /* XON2 register. */
  63 #define ST_UART011_ITCR         0x80    /* Integration test control register. */
  64 #define ST_UART011_ITIP         0x84    /* Integration test input register. */
  65 #define ST_UART011_ABCR         0x100   /* Autobaud control register. */
  66 #define ST_UART011_ABIMSC       0x15C   /* Autobaud interrupt mask/clear register. */
  67
  68 #define UART011_DR_OE           (1 << 11)
  69 #define UART011_DR_BE           (1 << 10)
  70 #define UART011_DR_PE           (1 << 9)
  71 #define UART011_DR_FE           (1 << 8)
  72
  73 #define UART01x_RSR_OE          0x08
  74 #define UART01x_RSR_BE          0x04
  75 #define UART01x_RSR_PE          0x02
  76 #define UART01x_RSR_FE          0x01
  77
  78 #define UART011_FR_RI           0x100
  79 #define UART011_FR_TXFE         0x080
  80 #define UART011_FR_RXFF         0x040
  81 #define UART01x_FR_TXFF         0x020
  82 #define UART01x_FR_RXFE         0x010
  83 #define UART01x_FR_BUSY         0x008
  84 #define UART01x_FR_DCD          0x004
  85 #define UART01x_FR_DSR          0x002
  86 #define UART01x_FR_CTS          0x001
  87 #define UART01x_FR_TMSK         (UART01x_FR_TXFF + UART01x_FR_BUSY)
  88
  89 #define UART011_CR_CTSEN        0x8000  /* CTS hardware flow control */
  90 #define UART011_CR_RTSEN        0x4000  /* RTS hardware flow control */
  91 #define UART011_CR_OUT2         0x2000  /* OUT2 */
  92 #define UART011_CR_OUT1         0x1000  /* OUT1 */
  93 #define UART011_CR_RTS          0x0800  /* RTS */
  94 #define UART011_CR_DTR          0x0400  /* DTR */
  95 #define UART011_CR_RXE          0x0200  /* receive enable */
  96 #define UART011_CR_TXE          0x0100  /* transmit enable */
  97 #define UART011_CR_LBE          0x0080  /* loopback enable */
  98 #define UART010_CR_RTIE         0x0040
  99 #define UART010_CR_TIE          0x0020
 100 #define UART010_CR_RIE          0x0010
 101 #define UART010_CR_MSIE         0x0008
 102 #define ST_UART011_CR_OVSFACT   0x0008  /* Oversampling factor */
 103 #define UART01x_CR_IIRLP        0x0004  /* SIR low power mode */
 104 #define UART01x_CR_SIREN        0x0002  /* SIR enable */
 105 #define UART01x_CR_UARTEN       0x0001  /* UART enable */
 106
 107 #define UART011_LCRH_SPS        0x80
 108 #define UART01x_LCRH_WLEN_8     0x60
 109 #define UART01x_LCRH_WLEN_7     0x40
 110 #define UART01x_LCRH_WLEN_6     0x20
 111 #define UART01x_LCRH_WLEN_5     0x00
 112 #define UART01x_LCRH_FEN        0x10
 113 #define UART01x_LCRH_STP2       0x08
 114 #define UART01x_LCRH_EPS        0x04
 115 #define UART01x_LCRH_PEN        0x02
 116 #define UART01x_LCRH_BRK        0x01
 117
 118 #define ST_UART011_DMAWM_RX_1   (0 << 3)
 119 #define ST_UART011_DMAWM_RX_2   (1 << 3)
 120 #define ST_UART011_DMAWM_RX_4   (2 << 3)
 121 #define ST_UART011_DMAWM_RX_8   (3 << 3)
 122 #define ST_UART011_DMAWM_RX_16  (4 << 3)
 123 #define ST_UART011_DMAWM_RX_32  (5 << 3)
 124 #define ST_UART011_DMAWM_RX_48  (6 << 3)
 125 #define ST_UART011_DMAWM_TX_1   0
 126 #define ST_UART011_DMAWM_TX_2   1
 127 #define ST_UART011_DMAWM_TX_4   2
 128 #define ST_UART011_DMAWM_TX_8   3
 129 #define ST_UART011_DMAWM_TX_16  4
 130 #define ST_UART011_DMAWM_TX_32  5
 131 #define ST_UART011_DMAWM_TX_48  6
 132
 133 #define UART010_IIR_RTIS        0x08
 134 #define UART010_IIR_TIS         0x04
 135 #define UART010_IIR_RIS         0x02
 136 #define UART010_IIR_MIS         0x01
 137
 138 #define UART011_IFLS_RX1_8      (0 << 3)
 139 #define UART011_IFLS_RX2_8      (1 << 3)
 140 #define UART011_IFLS_RX4_8      (2 << 3)
 141 #define UART011_IFLS_RX6_8      (3 << 3)
 142 #define UART011_IFLS_RX7_8      (4 << 3)
 143 #define UART011_IFLS_TX1_8      (0 << 0)
 144 #define UART011_IFLS_TX2_8      (1 << 0)
 145 #define UART011_IFLS_TX4_8      (2 << 0)
 146 #define UART011_IFLS_TX6_8      (3 << 0)
 147 #define UART011_IFLS_TX7_8      (4 << 0)
 148 /* special values for ST vendor with deeper fifo */
 149 #define UART011_IFLS_RX_HALF    (5 << 3)
 150 #define UART011_IFLS_TX_HALF    (5 << 0)
 151
 152 #define UART011_OEIM            (1 << 10)       /* overrun error interrupt mask */
 153 #define UART011_BEIM            (1 << 9)        /* break error interrupt mask */
 154 #define UART011_PEIM            (1 << 8)        /* parity error interrupt mask */
 155 #define UART011_FEIM            (1 << 7)        /* framing error interrupt mask */
 156 #define UART011_RTIM            (1 << 6)        /* receive timeout interrupt mask */
 157 #define UART011_TXIM            (1 << 5)        /* transmit interrupt mask */
 158 #define UART011_RXIM            (1 << 4)        /* receive interrupt mask */
 159 #define UART011_DSRMIM          (1 << 3)        /* DSR interrupt mask */
 160 #define UART011_DCDMIM          (1 << 2)        /* DCD interrupt mask */
 161 #define UART011_CTSMIM          (1 << 1)        /* CTS interrupt mask */
 162 #define UART011_RIMIM           (1 << 0)        /* RI interrupt mask */
 163
 164 #define UART011_OEIS            (1 << 10)       /* overrun error interrupt status */
 165 #define UART011_BEIS            (1 << 9)        /* break error interrupt status */
 166 #define UART011_PEIS            (1 << 8)        /* parity error interrupt status */
 167 #define UART011_FEIS            (1 << 7)        /* framing error interrupt status */
 168 #define UART011_RTIS            (1 << 6)        /* receive timeout interrupt status */
 169 #define UART011_TXIS            (1 << 5)        /* transmit interrupt status */
 170 #define UART011_RXIS            (1 << 4)        /* receive interrupt status */
 171 #define UART011_DSRMIS          (1 << 3)        /* DSR interrupt status */
 172 #define UART011_DCDMIS          (1 << 2)        /* DCD interrupt status */
 173 #define UART011_CTSMIS          (1 << 1)        /* CTS interrupt status */
 174 #define UART011_RIMIS           (1 << 0)        /* RI interrupt status */
 175
 176 #define UART011_OEIC            (1 << 10)       /* overrun error interrupt clear */
 177 #define UART011_BEIC            (1 << 9)        /* break error interrupt clear */
 178 #define UART011_PEIC            (1 << 8)        /* parity error interrupt clear */
 179 #define UART011_FEIC            (1 << 7)        /* framing error interrupt clear */
 180 #define UART011_RTIC            (1 << 6)        /* receive timeout interrupt clear */
 181 #define UART011_TXIC            (1 << 5)        /* transmit interrupt clear */
 182 #define UART011_RXIC            (1 << 4)        /* receive interrupt clear */
 183 #define UART011_DSRMIC          (1 << 3)        /* DSR interrupt clear */
 184 #define UART011_DCDMIC          (1 << 2)        /* DCD interrupt clear */
 185 #define UART011_CTSMIC          (1 << 1)        /* CTS interrupt clear */
 186 #define UART011_RIMIC           (1 << 0)        /* RI interrupt clear */
 187
 188 #define UART011_DMAONERR        (1 << 2)        /* disable dma on error */
 189 #define UART011_TXDMAE          (1 << 1)        /* enable transmit dma */
 190 #define UART011_RXDMAE          (1 << 0)        /* enable receive dma */
 191
 192 #define UART01x_RSR_ANY         (UART01x_RSR_OE|UART01x_RSR_BE|UART01x_RSR_PE|UART01x_RSR_FE)
 193 #define UART01x_FR_MODEM_ANY    (UART01x_FR_DCD|UART01x_FR_DSR|UART01x_FR_CTS)
 194
 195 #ifndef __ASSEMBLY__
 196 struct amba_device; /* in uncompress this is included but amba/bus.h is not */
 197 struct amba_pl010_data {
 198         void (*set_mctrl)(struct amba_device *dev, void __iomem *base, unsigned int mctrl);
 199 };
 200
 201 struct dma_chan;
 202 struct amba_pl011_data {
 203         bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
 204         void *dma_rx_param;
 205         void *dma_tx_param;
 206         void (*init) (void);
 207         void (*exit) (void);
 208         void (*reset) (void);
 209 };
 210 #endif
 211
 212 #endif