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spi-topcliff-pch: Fix issue for transmitting over 4KByte
[zen-stable.git] / include / linux / mlx4 / device.h
blobaea61905499b0e20598969cb02e63f32a3010d2d
1 /*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX4_DEVICE_H
34 #define MLX4_DEVICE_H
35
36 #include <linux/pci.h>
37 #include <linux/completion.h>
38 #include <linux/radix-tree.h>
39
40 #include <linux/atomic.h>
41
42 #define MAX_MSIX_P_PORT 17
43 #define MAX_MSIX 64
44 #define MSIX_LEGACY_SZ 4
45 #define MIN_MSIX_P_PORT 5
46
47 enum {
48 MLX4_FLAG_MSI_X = 1 << 0,
49 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
50 MLX4_FLAG_MASTER = 1 << 2,
51 MLX4_FLAG_SLAVE = 1 << 3,
52 MLX4_FLAG_SRIOV = 1 << 4,
53 };
54
55 enum {
56 MLX4_MAX_PORTS = 2
57 };
58
59 enum {
60 MLX4_BOARD_ID_LEN = 64
61 };
62
63 enum {
64 MLX4_MAX_NUM_PF = 16,
65 MLX4_MAX_NUM_VF = 64,
66 MLX4_MFUNC_MAX = 80,
67 MLX4_MFUNC_EQ_NUM = 4,
68 MLX4_MFUNC_MAX_EQES = 8,
69 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
70 };
71
72 enum {
73 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
74 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
75 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
76 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
77 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
78 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
79 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
80 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
81 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
82 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
83 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
84 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
85 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
86 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
87 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
88 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
89 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
90 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
91 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
92 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
93 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
94 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
95 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
96 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
97 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
98 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55
99 };
100
101 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
102
103 enum {
104 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
105 };
106
107 enum {
108 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
109 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
110 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
111 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
112 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
113 };
114
115 enum mlx4_event {
116 MLX4_EVENT_TYPE_COMP = 0x00,
117 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
118 MLX4_EVENT_TYPE_COMM_EST = 0x02,
119 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
120 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
121 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
122 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
123 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
124 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
125 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
126 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
127 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
128 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
129 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
130 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
131 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
132 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
133 MLX4_EVENT_TYPE_CMD = 0x0a,
134 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
135 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
136 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
137 MLX4_EVENT_TYPE_NONE = 0xff,
138 };
139
140 enum {
141 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
142 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
143 };
144
145 enum {
146 MLX4_PERM_LOCAL_READ = 1 << 10,
147 MLX4_PERM_LOCAL_WRITE = 1 << 11,
148 MLX4_PERM_REMOTE_READ = 1 << 12,
149 MLX4_PERM_REMOTE_WRITE = 1 << 13,
150 MLX4_PERM_ATOMIC = 1 << 14
151 };
152
153 enum {
154 MLX4_OPCODE_NOP = 0x00,
155 MLX4_OPCODE_SEND_INVAL = 0x01,
156 MLX4_OPCODE_RDMA_WRITE = 0x08,
157 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
158 MLX4_OPCODE_SEND = 0x0a,
159 MLX4_OPCODE_SEND_IMM = 0x0b,
160 MLX4_OPCODE_LSO = 0x0e,
161 MLX4_OPCODE_RDMA_READ = 0x10,
162 MLX4_OPCODE_ATOMIC_CS = 0x11,
163 MLX4_OPCODE_ATOMIC_FA = 0x12,
164 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
165 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
166 MLX4_OPCODE_BIND_MW = 0x18,
167 MLX4_OPCODE_FMR = 0x19,
168 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
169 MLX4_OPCODE_CONFIG_CMD = 0x1f,
170
171 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
172 MLX4_RECV_OPCODE_SEND = 0x01,
173 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
174 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
175
176 MLX4_CQE_OPCODE_ERROR = 0x1e,
177 MLX4_CQE_OPCODE_RESIZE = 0x16,
178 };
179
180 enum {
181 MLX4_STAT_RATE_OFFSET = 5
182 };
183
184 enum mlx4_protocol {
185 MLX4_PROT_IB_IPV6 = 0,
186 MLX4_PROT_ETH,
187 MLX4_PROT_IB_IPV4,
188 MLX4_PROT_FCOE
189 };
190
191 enum {
192 MLX4_MTT_FLAG_PRESENT = 1
193 };
194
195 enum mlx4_qp_region {
196 MLX4_QP_REGION_FW = 0,
197 MLX4_QP_REGION_ETH_ADDR,
198 MLX4_QP_REGION_FC_ADDR,
199 MLX4_QP_REGION_FC_EXCH,
200 MLX4_NUM_QP_REGION
201 };
202
203 enum mlx4_port_type {
204 MLX4_PORT_TYPE_NONE = 0,
205 MLX4_PORT_TYPE_IB = 1,
206 MLX4_PORT_TYPE_ETH = 2,
207 MLX4_PORT_TYPE_AUTO = 3
208 };
209
210 enum mlx4_special_vlan_idx {
211 MLX4_NO_VLAN_IDX = 0,
212 MLX4_VLAN_MISS_IDX,
213 MLX4_VLAN_REGULAR
214 };
215
216 enum mlx4_steer_type {
217 MLX4_MC_STEER = 0,
218 MLX4_UC_STEER,
219 MLX4_NUM_STEERS
220 };
221
222 enum {
223 MLX4_NUM_FEXCH = 64 * 1024,
224 };
225
226 enum {
227 MLX4_MAX_FAST_REG_PAGES = 511,
228 };
229
230 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
231 {
232 return (major << 32) | (minor << 16) | subminor;
233 }
234
235 struct mlx4_caps {
236 u64 fw_ver;
237 u32 function;
238 int num_ports;
239 int vl_cap[MLX4_MAX_PORTS + 1];
240 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
241 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
242 u64 def_mac[MLX4_MAX_PORTS + 1];
243 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
244 int gid_table_len[MLX4_MAX_PORTS + 1];
245 int pkey_table_len[MLX4_MAX_PORTS + 1];
246 int trans_type[MLX4_MAX_PORTS + 1];
247 int vendor_oui[MLX4_MAX_PORTS + 1];
248 int wavelength[MLX4_MAX_PORTS + 1];
249 u64 trans_code[MLX4_MAX_PORTS + 1];
250 int local_ca_ack_delay;
251 int num_uars;
252 u32 uar_page_size;
253 int bf_reg_size;
254 int bf_regs_per_page;
255 int max_sq_sg;
256 int max_rq_sg;
257 int num_qps;
258 int max_wqes;
259 int max_sq_desc_sz;
260 int max_rq_desc_sz;
261 int max_qp_init_rdma;
262 int max_qp_dest_rdma;
263 int sqp_start;
264 int num_srqs;
265 int max_srq_wqes;
266 int max_srq_sge;
267 int reserved_srqs;
268 int num_cqs;
269 int max_cqes;
270 int reserved_cqs;
271 int num_eqs;
272 int reserved_eqs;
273 int num_comp_vectors;
274 int comp_pool;
275 int num_mpts;
276 int num_mtts;
277 int fmr_reserved_mtts;
278 int reserved_mtts;
279 int reserved_mrws;
280 int reserved_uars;
281 int num_mgms;
282 int num_amgms;
283 int reserved_mcgs;
284 int num_qp_per_mgm;
285 int num_pds;
286 int reserved_pds;
287 int max_xrcds;
288 int reserved_xrcds;
289 int mtt_entry_sz;
290 u32 max_msg_sz;
291 u32 page_size_cap;
292 u64 flags;
293 u32 bmme_flags;
294 u32 reserved_lkey;
295 u16 stat_rate_support;
296 u8 port_width_cap[MLX4_MAX_PORTS + 1];
297 int max_gso_sz;
298 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
299 int reserved_qps;
300 int reserved_qps_base[MLX4_NUM_QP_REGION];
301 int log_num_macs;
302 int log_num_vlans;
303 int log_num_prios;
304 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
305 u8 supported_type[MLX4_MAX_PORTS + 1];
306 u8 suggested_type[MLX4_MAX_PORTS + 1];
307 u8 default_sense[MLX4_MAX_PORTS + 1];
308 u32 port_mask[MLX4_MAX_PORTS + 1];
309 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
310 u32 max_counters;
311 u8 ext_port_cap[MLX4_MAX_PORTS + 1];
312 };
313
314 struct mlx4_buf_list {
315 void *buf;
316 dma_addr_t map;
317 };
318
319 struct mlx4_buf {
320 struct mlx4_buf_list direct;
321 struct mlx4_buf_list *page_list;
322 int nbufs;
323 int npages;
324 int page_shift;
325 };
326
327 struct mlx4_mtt {
328 u32 offset;
329 int order;
330 int page_shift;
331 };
332
333 enum {
334 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
335 };
336
337 struct mlx4_db_pgdir {
338 struct list_head list;
339 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
340 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
341 unsigned long *bits[2];
342 __be32 *db_page;
343 dma_addr_t db_dma;
344 };
345
346 struct mlx4_ib_user_db_page;
347
348 struct mlx4_db {
349 __be32 *db;
350 union {
351 struct mlx4_db_pgdir *pgdir;
352 struct mlx4_ib_user_db_page *user_page;
353 } u;
354 dma_addr_t dma;
355 int index;
356 int order;
357 };
358
359 struct mlx4_hwq_resources {
360 struct mlx4_db db;
361 struct mlx4_mtt mtt;
362 struct mlx4_buf buf;
363 };
364
365 struct mlx4_mr {
366 struct mlx4_mtt mtt;
367 u64 iova;
368 u64 size;
369 u32 key;
370 u32 pd;
371 u32 access;
372 int enabled;
373 };
374
375 struct mlx4_fmr {
376 struct mlx4_mr mr;
377 struct mlx4_mpt_entry *mpt;
378 __be64 *mtts;
379 dma_addr_t dma_handle;
380 int max_pages;
381 int max_maps;
382 int maps;
383 u8 page_shift;
384 };
385
386 struct mlx4_uar {
387 unsigned long pfn;
388 int index;
389 struct list_head bf_list;
390 unsigned free_bf_bmap;
391 void __iomem *map;
392 void __iomem *bf_map;
393 };
394
395 struct mlx4_bf {
396 unsigned long offset;
397 int buf_size;
398 struct mlx4_uar *uar;
399 void __iomem *reg;
400 };
401
402 struct mlx4_cq {
403 void (*comp) (struct mlx4_cq *);
404 void (*event) (struct mlx4_cq *, enum mlx4_event);
405
406 struct mlx4_uar *uar;
407
408 u32 cons_index;
409
410 __be32 *set_ci_db;
411 __be32 *arm_db;
412 int arm_sn;
413
414 int cqn;
415 unsigned vector;
416
417 atomic_t refcount;
418 struct completion free;
419 };
420
421 struct mlx4_qp {
422 void (*event) (struct mlx4_qp *, enum mlx4_event);
423
424 int qpn;
425
426 atomic_t refcount;
427 struct completion free;
428 };
429
430 struct mlx4_srq {
431 void (*event) (struct mlx4_srq *, enum mlx4_event);
432
433 int srqn;
434 int max;
435 int max_gs;
436 int wqe_shift;
437
438 atomic_t refcount;
439 struct completion free;
440 };
441
442 struct mlx4_av {
443 __be32 port_pd;
444 u8 reserved1;
445 u8 g_slid;
446 __be16 dlid;
447 u8 reserved2;
448 u8 gid_index;
449 u8 stat_rate;
450 u8 hop_limit;
451 __be32 sl_tclass_flowlabel;
452 u8 dgid[16];
453 };
454
455 struct mlx4_eth_av {
456 __be32 port_pd;
457 u8 reserved1;
458 u8 smac_idx;
459 u16 reserved2;
460 u8 reserved3;
461 u8 gid_index;
462 u8 stat_rate;
463 u8 hop_limit;
464 __be32 sl_tclass_flowlabel;
465 u8 dgid[16];
466 u32 reserved4[2];
467 __be16 vlan;
468 u8 mac[6];
469 };
470
471 union mlx4_ext_av {
472 struct mlx4_av ib;
473 struct mlx4_eth_av eth;
474 };
475
476 struct mlx4_counter {
477 u8 reserved1[3];
478 u8 counter_mode;
479 __be32 num_ifc;
480 u32 reserved2[2];
481 __be64 rx_frames;
482 __be64 rx_bytes;
483 __be64 tx_frames;
484 __be64 tx_bytes;
485 };
486
487 struct mlx4_dev {
488 struct pci_dev *pdev;
489 unsigned long flags;
490 unsigned long num_slaves;
491 struct mlx4_caps caps;
492 struct radix_tree_root qp_table_tree;
493 u8 rev_id;
494 char board_id[MLX4_BOARD_ID_LEN];
495 int num_vfs;
496 };
497
498 struct mlx4_init_port_param {
499 int set_guid0;
500 int set_node_guid;
501 int set_si_guid;
502 u16 mtu;
503 int port_width_cap;
504 u16 vl_cap;
505 u16 max_gid;
506 u16 max_pkey;
507 u64 guid0;
508 u64 node_guid;
509 u64 si_guid;
510 };
511
512 #define mlx4_foreach_port(port, dev, type) \
513 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
514 if ((type) == (dev)->caps.port_mask[(port)])
515
516 #define mlx4_foreach_ib_transport_port(port, dev) \
517 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
518 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
519 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
520
521 static inline int mlx4_is_master(struct mlx4_dev *dev)
522 {
523 return dev->flags & MLX4_FLAG_MASTER;
524 }
525
526 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
527 {
528 return (qpn < dev->caps.sqp_start + 8);
529 }
530
531 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
532 {
533 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
534 }
535
536 static inline int mlx4_is_slave(struct mlx4_dev *dev)
537 {
538 return dev->flags & MLX4_FLAG_SLAVE;
539 }
540
541 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
542 struct mlx4_buf *buf);
543 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
544 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
545 {
546 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
547 return buf->direct.buf + offset;
548 else
549 return buf->page_list[offset >> PAGE_SHIFT].buf +
550 (offset & (PAGE_SIZE - 1));
551 }
552
553 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
554 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
555 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
556 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
557
558 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
559 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
560 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf);
561 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
562
563 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
564 struct mlx4_mtt *mtt);
565 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
566 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
567
568 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
569 int npages, int page_shift, struct mlx4_mr *mr);
570 void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
571 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
572 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
573 int start_index, int npages, u64 *page_list);
574 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
575 struct mlx4_buf *buf);
576
577 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
578 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
579
580 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
581 int size, int max_direct);
582 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
583 int size);
584
585 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
586 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
587 unsigned vector, int collapsed);
588 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
589
590 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
591 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
592
593 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
594 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
595
596 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
597 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
598 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
599 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
600 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
601
602 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
603 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
604
605 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
606 int block_mcast_loopback, enum mlx4_protocol prot);
607 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
608 enum mlx4_protocol prot);
609 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
610 int block_mcast_loopback, enum mlx4_protocol protocol);
611 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
612 enum mlx4_protocol protocol);
613 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
614 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
615 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
616 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
617 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
618
619 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
620 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
621 int mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
622 int mlx4_get_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int *qpn);
623 void mlx4_put_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int qpn);
624 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap);
625
626 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
627 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
628 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
629
630 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
631 int npages, u64 iova, u32 *lkey, u32 *rkey);
632 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
633 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
634 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
635 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
636 u32 *lkey, u32 *rkey);
637 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
638 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
639 int mlx4_test_interrupts(struct mlx4_dev *dev);
640 int mlx4_assign_eq(struct mlx4_dev *dev, char* name , int* vector);
641 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
642
643 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
644 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
645
646 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
647 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
648
649 #endif /* MLX4_DEVICE_H */