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spi-topcliff-pch: Fix issue for transmitting over 4KByte
[zen-stable.git] / include / linux / pci.h
bloba16b1df3deff0c47212f09667704ef369a08cf1c
1 /*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17 #ifndef LINUX_PCI_H
18 #define LINUX_PCI_H
19
20 #include <linux/pci_regs.h> /* The pci register defines */
21
22 /*
23 * The PCI interface treats multi-function devices as independent
24 * devices. The slot/function address of each device is encoded
25 * in a single byte as follows:
26 *
27 * 7:3 = slot
28 * 2:0 = function
29 */
30 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
31 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
32 #define PCI_FUNC(devfn) ((devfn) & 0x07)
33
34 /* Ioctls for /proc/bus/pci/X/Y nodes. */
35 #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
36 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
37 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
38 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
39 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
40
41 #ifdef __KERNEL__
42
43 #include <linux/mod_devicetable.h>
44
45 #include <linux/types.h>
46 #include <linux/init.h>
47 #include <linux/ioport.h>
48 #include <linux/list.h>
49 #include <linux/compiler.h>
50 #include <linux/errno.h>
51 #include <linux/kobject.h>
52 #include <linux/atomic.h>
53 #include <linux/device.h>
54 #include <linux/io.h>
55 #include <linux/irqreturn.h>
56
57 /* Include the ID list */
58 #include <linux/pci_ids.h>
59
60 /* pci_slot represents a physical slot */
61 struct pci_slot {
62 struct pci_bus *bus; /* The bus this slot is on */
63 struct list_head list; /* node in list of slots on this bus */
64 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
65 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
66 struct kobject kobj;
67 };
68
69 static inline const char *pci_slot_name(const struct pci_slot *slot)
70 {
71 return kobject_name(&slot->kobj);
72 }
73
74 /* File state for mmap()s on /proc/bus/pci/X/Y */
75 enum pci_mmap_state {
76 pci_mmap_io,
77 pci_mmap_mem
78 };
79
80 /* This defines the direction arg to the DMA mapping routines. */
81 #define PCI_DMA_BIDIRECTIONAL 0
82 #define PCI_DMA_TODEVICE 1
83 #define PCI_DMA_FROMDEVICE 2
84 #define PCI_DMA_NONE 3
85
86 /*
87 * For PCI devices, the region numbers are assigned this way:
88 */
89 enum {
90 /* #0-5: standard PCI resources */
91 PCI_STD_RESOURCES,
92 PCI_STD_RESOURCE_END = 5,
93
94 /* #6: expansion ROM resource */
95 PCI_ROM_RESOURCE,
96
97 /* device specific resources */
98 #ifdef CONFIG_PCI_IOV
99 PCI_IOV_RESOURCES,
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
101 #endif
102
103 /* resources assigned to buses behind the bridge */
104 #define PCI_BRIDGE_RESOURCE_NUM 4
105
106 PCI_BRIDGE_RESOURCES,
107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
108 PCI_BRIDGE_RESOURCE_NUM - 1,
109
110 /* total resources associated with a PCI device */
111 PCI_NUM_RESOURCES,
112
113 /* preserve this for compatibility */
114 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
115 };
116
117 typedef int __bitwise pci_power_t;
118
119 #define PCI_D0 ((pci_power_t __force) 0)
120 #define PCI_D1 ((pci_power_t __force) 1)
121 #define PCI_D2 ((pci_power_t __force) 2)
122 #define PCI_D3hot ((pci_power_t __force) 3)
123 #define PCI_D3cold ((pci_power_t __force) 4)
124 #define PCI_UNKNOWN ((pci_power_t __force) 5)
125 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
126
127 /* Remember to update this when the list above changes! */
128 extern const char *pci_power_names[];
129
130 static inline const char *pci_power_name(pci_power_t state)
131 {
132 return pci_power_names[1 + (int) state];
133 }
134
135 #define PCI_PM_D2_DELAY 200
136 #define PCI_PM_D3_WAIT 10
137 #define PCI_PM_BUS_WAIT 50
138
139 /** The pci_channel state describes connectivity between the CPU and
140 * the pci device. If some PCI bus between here and the pci device
141 * has crashed or locked up, this info is reflected here.
142 */
143 typedef unsigned int __bitwise pci_channel_state_t;
144
145 enum pci_channel_state {
146 /* I/O channel is in normal state */
147 pci_channel_io_normal = (__force pci_channel_state_t) 1,
148
149 /* I/O to channel is blocked */
150 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
151
152 /* PCI card is dead */
153 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
154 };
155
156 typedef unsigned int __bitwise pcie_reset_state_t;
157
158 enum pcie_reset_state {
159 /* Reset is NOT asserted (Use to deassert reset) */
160 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
161
162 /* Use #PERST to reset PCI-E device */
163 pcie_warm_reset = (__force pcie_reset_state_t) 2,
164
165 /* Use PCI-E Hot Reset to reset device */
166 pcie_hot_reset = (__force pcie_reset_state_t) 3
167 };
168
169 typedef unsigned short __bitwise pci_dev_flags_t;
170 enum pci_dev_flags {
171 /* INTX_DISABLE in PCI_COMMAND register disables MSI
172 * generation too.
173 */
174 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
175 /* Device configuration is irrevocably lost if disabled into D3 */
176 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
177 /* Provide indication device is assigned by a Virtual Machine Manager */
178 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4,
179 };
180
181 enum pci_irq_reroute_variant {
182 INTEL_IRQ_REROUTE_VARIANT = 1,
183 MAX_IRQ_REROUTE_VARIANTS = 3
184 };
185
186 typedef unsigned short __bitwise pci_bus_flags_t;
187 enum pci_bus_flags {
188 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
189 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
190 };
191
192 /* Based on the PCI Hotplug Spec, but some values are made up by us */
193 enum pci_bus_speed {
194 PCI_SPEED_33MHz = 0x00,
195 PCI_SPEED_66MHz = 0x01,
196 PCI_SPEED_66MHz_PCIX = 0x02,
197 PCI_SPEED_100MHz_PCIX = 0x03,
198 PCI_SPEED_133MHz_PCIX = 0x04,
199 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
200 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
201 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
202 PCI_SPEED_66MHz_PCIX_266 = 0x09,
203 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
204 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
205 AGP_UNKNOWN = 0x0c,
206 AGP_1X = 0x0d,
207 AGP_2X = 0x0e,
208 AGP_4X = 0x0f,
209 AGP_8X = 0x10,
210 PCI_SPEED_66MHz_PCIX_533 = 0x11,
211 PCI_SPEED_100MHz_PCIX_533 = 0x12,
212 PCI_SPEED_133MHz_PCIX_533 = 0x13,
213 PCIE_SPEED_2_5GT = 0x14,
214 PCIE_SPEED_5_0GT = 0x15,
215 PCIE_SPEED_8_0GT = 0x16,
216 PCI_SPEED_UNKNOWN = 0xff,
217 };
218
219 struct pci_cap_saved_data {
220 char cap_nr;
221 unsigned int size;
222 u32 data[0];
223 };
224
225 struct pci_cap_saved_state {
226 struct hlist_node next;
227 struct pci_cap_saved_data cap;
228 };
229
230 struct pcie_link_state;
231 struct pci_vpd;
232 struct pci_sriov;
233 struct pci_ats;
234
235 /*
236 * The pci_dev structure is used to describe PCI devices.
237 */
238 struct pci_dev {
239 struct list_head bus_list; /* node in per-bus list */
240 struct pci_bus *bus; /* bus this device is on */
241 struct pci_bus *subordinate; /* bus this device bridges to */
242
243 void *sysdata; /* hook for sys-specific extension */
244 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
245 struct pci_slot *slot; /* Physical slot this device is in */
246
247 unsigned int devfn; /* encoded device & function index */
248 unsigned short vendor;
249 unsigned short device;
250 unsigned short subsystem_vendor;
251 unsigned short subsystem_device;
252 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
253 u8 revision; /* PCI revision, low byte of class word */
254 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
255 u8 pcie_cap; /* PCI-E capability offset */
256 u8 pcie_type:4; /* PCI-E device/port type */
257 u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */
258 u8 rom_base_reg; /* which config register controls the ROM */
259 u8 pin; /* which interrupt pin this device uses */
260
261 struct pci_driver *driver; /* which driver has allocated this device */
262 u64 dma_mask; /* Mask of the bits of bus address this
263 device implements. Normally this is
264 0xffffffff. You only need to change
265 this if your device has broken DMA
266 or supports 64-bit transfers. */
267
268 struct device_dma_parameters dma_parms;
269
270 pci_power_t current_state; /* Current operating state. In ACPI-speak,
271 this is D0-D3, D0 being fully functional,
272 and D3 being off. */
273 int pm_cap; /* PM capability offset in the
274 configuration space */
275 unsigned int pme_support:5; /* Bitmask of states from which PME#
276 can be generated */
277 unsigned int pme_interrupt:1;
278 unsigned int pme_poll:1; /* Poll device's PME status bit */
279 unsigned int d1_support:1; /* Low power state D1 is supported */
280 unsigned int d2_support:1; /* Low power state D2 is supported */
281 unsigned int no_d1d2:1; /* Only allow D0 and D3 */
282 unsigned int mmio_always_on:1; /* disallow turning off io/mem
283 decoding during bar sizing */
284 unsigned int wakeup_prepared:1;
285 unsigned int d3_delay; /* D3->D0 transition time in ms */
286
287 #ifdef CONFIG_PCIEASPM
288 struct pcie_link_state *link_state; /* ASPM link state. */
289 #endif
290
291 pci_channel_state_t error_state; /* current connectivity state */
292 struct device dev; /* Generic device interface */
293
294 int cfg_size; /* Size of configuration space */
295
296 /*
297 * Instead of touching interrupt line and base address registers
298 * directly, use the values stored here. They might be different!
299 */
300 unsigned int irq;
301 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
302 resource_size_t fw_addr[DEVICE_COUNT_RESOURCE]; /* FW-assigned addr */
303
304 /* These fields are used by common fixups */
305 unsigned int transparent:1; /* Transparent PCI bridge */
306 unsigned int multifunction:1;/* Part of multi-function device */
307 /* keep track of device state */
308 unsigned int is_added:1;
309 unsigned int is_busmaster:1; /* device is busmaster */
310 unsigned int no_msi:1; /* device may not use msi */
311 unsigned int block_cfg_access:1; /* config space access is blocked */
312 unsigned int broken_parity_status:1; /* Device generates false positive parity */
313 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
314 unsigned int msi_enabled:1;
315 unsigned int msix_enabled:1;
316 unsigned int ari_enabled:1; /* ARI forwarding */
317 unsigned int is_managed:1;
318 unsigned int is_pcie:1; /* Obsolete. Will be removed.
319 Use pci_is_pcie() instead */
320 unsigned int needs_freset:1; /* Dev requires fundamental reset */
321 unsigned int state_saved:1;
322 unsigned int is_physfn:1;
323 unsigned int is_virtfn:1;
324 unsigned int reset_fn:1;
325 unsigned int is_hotplug_bridge:1;
326 unsigned int __aer_firmware_first_valid:1;
327 unsigned int __aer_firmware_first:1;
328 pci_dev_flags_t dev_flags;
329 atomic_t enable_cnt; /* pci_enable_device has been called */
330
331 u32 saved_config_space[16]; /* config space saved at suspend time */
332 struct hlist_head saved_cap_space;
333 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
334 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
335 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
336 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
337 #ifdef CONFIG_PCI_MSI
338 struct list_head msi_list;
339 struct kset *msi_kset;
340 #endif
341 struct pci_vpd *vpd;
342 #ifdef CONFIG_PCI_ATS
343 union {
344 struct pci_sriov *sriov; /* SR-IOV capability related */
345 struct pci_dev *physfn; /* the PF this VF is associated with */
346 };
347 struct pci_ats *ats; /* Address Translation Service */
348 #endif
349 };
350
351 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
352 {
353 #ifdef CONFIG_PCI_IOV
354 if (dev->is_virtfn)
355 dev = dev->physfn;
356 #endif
357
358 return dev;
359 }
360
361 extern struct pci_dev *alloc_pci_dev(void);
362
363 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
364 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
365 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
366
367 static inline int pci_channel_offline(struct pci_dev *pdev)
368 {
369 return (pdev->error_state != pci_channel_io_normal);
370 }
371
372 static inline struct pci_cap_saved_state *pci_find_saved_cap(
373 struct pci_dev *pci_dev, char cap)
374 {
375 struct pci_cap_saved_state *tmp;
376 struct hlist_node *pos;
377
378 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
379 if (tmp->cap.cap_nr == cap)
380 return tmp;
381 }
382 return NULL;
383 }
384
385 static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
386 struct pci_cap_saved_state *new_cap)
387 {
388 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
389 }
390
391 /*
392 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
393 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
394 * buses below host bridges or subtractive decode bridges) go in the list.
395 * Use pci_bus_for_each_resource() to iterate through all the resources.
396 */
397
398 /*
399 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
400 * and there's no way to program the bridge with the details of the window.
401 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
402 * decode bit set, because they are explicit and can be programmed with _SRS.
403 */
404 #define PCI_SUBTRACTIVE_DECODE 0x1
405
406 struct pci_bus_resource {
407 struct list_head list;
408 struct resource *res;
409 unsigned int flags;
410 };
411
412 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
413
414 struct pci_bus {
415 struct list_head node; /* node in list of buses */
416 struct pci_bus *parent; /* parent bus this bridge is on */
417 struct list_head children; /* list of child buses */
418 struct list_head devices; /* list of devices on this bus */
419 struct pci_dev *self; /* bridge device as seen by parent */
420 struct list_head slots; /* list of slots on this bus */
421 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
422 struct list_head resources; /* address space routed to this bus */
423
424 struct pci_ops *ops; /* configuration access functions */
425 void *sysdata; /* hook for sys-specific extension */
426 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
427
428 unsigned char number; /* bus number */
429 unsigned char primary; /* number of primary bridge */
430 unsigned char secondary; /* number of secondary bridge */
431 unsigned char subordinate; /* max number of subordinate buses */
432 unsigned char max_bus_speed; /* enum pci_bus_speed */
433 unsigned char cur_bus_speed; /* enum pci_bus_speed */
434
435 char name[48];
436
437 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
438 pci_bus_flags_t bus_flags; /* Inherited by child busses */
439 struct device *bridge;
440 struct device dev;
441 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
442 struct bin_attribute *legacy_mem; /* legacy mem */
443 unsigned int is_added:1;
444 };
445
446 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
447 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
448
449 /*
450 * Returns true if the pci bus is root (behind host-pci bridge),
451 * false otherwise
452 */
453 static inline bool pci_is_root_bus(struct pci_bus *pbus)
454 {
455 return !(pbus->parent);
456 }
457
458 #ifdef CONFIG_PCI_MSI
459 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
460 {
461 return pci_dev->msi_enabled || pci_dev->msix_enabled;
462 }
463 #else
464 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
465 #endif
466
467 /*
468 * Error values that may be returned by PCI functions.
469 */
470 #define PCIBIOS_SUCCESSFUL 0x00
471 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
472 #define PCIBIOS_BAD_VENDOR_ID 0x83
473 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
474 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
475 #define PCIBIOS_SET_FAILED 0x88
476 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
477
478 /* Low-level architecture-dependent routines */
479
480 struct pci_ops {
481 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
482 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
483 };
484
485 /*
486 * ACPI needs to be able to access PCI config space before we've done a
487 * PCI bus scan and created pci_bus structures.
488 */
489 extern int raw_pci_read(unsigned int domain, unsigned int bus,
490 unsigned int devfn, int reg, int len, u32 *val);
491 extern int raw_pci_write(unsigned int domain, unsigned int bus,
492 unsigned int devfn, int reg, int len, u32 val);
493
494 struct pci_bus_region {
495 resource_size_t start;
496 resource_size_t end;
497 };
498
499 struct pci_dynids {
500 spinlock_t lock; /* protects list, index */
501 struct list_head list; /* for IDs added at runtime */
502 };
503
504 /* ---------------------------------------------------------------- */
505 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
506 * a set of callbacks in struct pci_error_handlers, then that device driver
507 * will be notified of PCI bus errors, and will be driven to recovery
508 * when an error occurs.
509 */
510
511 typedef unsigned int __bitwise pci_ers_result_t;
512
513 enum pci_ers_result {
514 /* no result/none/not supported in device driver */
515 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
516
517 /* Device driver can recover without slot reset */
518 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
519
520 /* Device driver wants slot to be reset. */
521 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
522
523 /* Device has completely failed, is unrecoverable */
524 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
525
526 /* Device driver is fully recovered and operational */
527 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
528 };
529
530 /* PCI bus error event callbacks */
531 struct pci_error_handlers {
532 /* PCI bus error detected on this device */
533 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
534 enum pci_channel_state error);
535
536 /* MMIO has been re-enabled, but not DMA */
537 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
538
539 /* PCI Express link has been reset */
540 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
541
542 /* PCI slot has been reset */
543 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
544
545 /* Device driver may resume normal operations */
546 void (*resume)(struct pci_dev *dev);
547 };
548
549 /* ---------------------------------------------------------------- */
550
551 struct module;
552 struct pci_driver {
553 struct list_head node;
554 const char *name;
555 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
556 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
557 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
558 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
559 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
560 int (*resume_early) (struct pci_dev *dev);
561 int (*resume) (struct pci_dev *dev); /* Device woken up */
562 void (*shutdown) (struct pci_dev *dev);
563 struct pci_error_handlers *err_handler;
564 struct device_driver driver;
565 struct pci_dynids dynids;
566 };
567
568 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
569
570 /**
571 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
572 * @_table: device table name
573 *
574 * This macro is used to create a struct pci_device_id array (a device table)
575 * in a generic manner.
576 */
577 #define DEFINE_PCI_DEVICE_TABLE(_table) \
578 const struct pci_device_id _table[] __devinitconst
579
580 /**
581 * PCI_DEVICE - macro used to describe a specific pci device
582 * @vend: the 16 bit PCI Vendor ID
583 * @dev: the 16 bit PCI Device ID
584 *
585 * This macro is used to create a struct pci_device_id that matches a
586 * specific device. The subvendor and subdevice fields will be set to
587 * PCI_ANY_ID.
588 */
589 #define PCI_DEVICE(vend,dev) \
590 .vendor = (vend), .device = (dev), \
591 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
592
593 /**
594 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
595 * @dev_class: the class, subclass, prog-if triple for this device
596 * @dev_class_mask: the class mask for this device
597 *
598 * This macro is used to create a struct pci_device_id that matches a
599 * specific PCI class. The vendor, device, subvendor, and subdevice
600 * fields will be set to PCI_ANY_ID.
601 */
602 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
603 .class = (dev_class), .class_mask = (dev_class_mask), \
604 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
605 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
606
607 /**
608 * PCI_VDEVICE - macro used to describe a specific pci device in short form
609 * @vendor: the vendor name
610 * @device: the 16 bit PCI Device ID
611 *
612 * This macro is used to create a struct pci_device_id that matches a
613 * specific PCI device. The subvendor, and subdevice fields will be set
614 * to PCI_ANY_ID. The macro allows the next field to follow as the device
615 * private data.
616 */
617
618 #define PCI_VDEVICE(vendor, device) \
619 PCI_VENDOR_ID_##vendor, (device), \
620 PCI_ANY_ID, PCI_ANY_ID, 0, 0
621
622 /* these external functions are only available when PCI support is enabled */
623 #ifdef CONFIG_PCI
624
625 extern void pcie_bus_configure_settings(struct pci_bus *bus, u8 smpss);
626
627 enum pcie_bus_config_types {
628 PCIE_BUS_TUNE_OFF,
629 PCIE_BUS_SAFE,
630 PCIE_BUS_PERFORMANCE,
631 PCIE_BUS_PEER2PEER,
632 };
633
634 extern enum pcie_bus_config_types pcie_bus_config;
635
636 extern struct bus_type pci_bus_type;
637
638 /* Do NOT directly access these two variables, unless you are arch specific pci
639 * code, or pci core code. */
640 extern struct list_head pci_root_buses; /* list of all known PCI buses */
641 /* Some device drivers need know if pci is initiated */
642 extern int no_pci_devices(void);
643
644 void pcibios_fixup_bus(struct pci_bus *);
645 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
646 char *pcibios_setup(char *str);
647
648 /* Used only when drivers/pci/setup.c is used */
649 resource_size_t pcibios_align_resource(void *, const struct resource *,
650 resource_size_t,
651 resource_size_t);
652 void pcibios_update_irq(struct pci_dev *, int irq);
653
654 /* Weak but can be overriden by arch */
655 void pci_fixup_cardbus(struct pci_bus *);
656
657 /* Generic PCI functions used internally */
658
659 void pcibios_scan_specific_bus(int busn);
660 extern struct pci_bus *pci_find_bus(int domain, int busnr);
661 void pci_bus_add_devices(const struct pci_bus *bus);
662 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
663 struct pci_ops *ops, void *sysdata);
664 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
665 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
666 struct pci_ops *ops, void *sysdata,
667 struct list_head *resources);
668 struct pci_bus * __devinit pci_scan_root_bus(struct device *parent, int bus,
669 struct pci_ops *ops, void *sysdata,
670 struct list_head *resources);
671 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
672 int busnr);
673 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
674 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
675 const char *name,
676 struct hotplug_slot *hotplug);
677 void pci_destroy_slot(struct pci_slot *slot);
678 void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
679 int pci_scan_slot(struct pci_bus *bus, int devfn);
680 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
681 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
682 unsigned int pci_scan_child_bus(struct pci_bus *bus);
683 int __must_check pci_bus_add_device(struct pci_dev *dev);
684 void pci_read_bridge_bases(struct pci_bus *child);
685 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
686 struct resource *res);
687 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin);
688 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
689 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
690 extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
691 extern void pci_dev_put(struct pci_dev *dev);
692 extern void pci_remove_bus(struct pci_bus *b);
693 extern void pci_remove_bus_device(struct pci_dev *dev);
694 extern void pci_stop_bus_device(struct pci_dev *dev);
695 void pci_setup_cardbus(struct pci_bus *bus);
696 extern void pci_sort_breadthfirst(void);
697 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
698 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
699 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
700
701 /* Generic PCI functions exported to card drivers */
702
703 enum pci_lost_interrupt_reason {
704 PCI_LOST_IRQ_NO_INFORMATION = 0,
705 PCI_LOST_IRQ_DISABLE_MSI,
706 PCI_LOST_IRQ_DISABLE_MSIX,
707 PCI_LOST_IRQ_DISABLE_ACPI,
708 };
709 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
710 int pci_find_capability(struct pci_dev *dev, int cap);
711 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
712 int pci_find_ext_capability(struct pci_dev *dev, int cap);
713 int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
714 int cap);
715 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
716 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
717 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
718
719 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
720 struct pci_dev *from);
721 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
722 unsigned int ss_vendor, unsigned int ss_device,
723 struct pci_dev *from);
724 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
725 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
726 unsigned int devfn);
727 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
728 unsigned int devfn)
729 {
730 return pci_get_domain_bus_and_slot(0, bus, devfn);
731 }
732 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
733 int pci_dev_present(const struct pci_device_id *ids);
734
735 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
736 int where, u8 *val);
737 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
738 int where, u16 *val);
739 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
740 int where, u32 *val);
741 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
742 int where, u8 val);
743 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
744 int where, u16 val);
745 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
746 int where, u32 val);
747 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
748
749 static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
750 {
751 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
752 }
753 static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
754 {
755 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
756 }
757 static inline int pci_read_config_dword(struct pci_dev *dev, int where,
758 u32 *val)
759 {
760 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
761 }
762 static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
763 {
764 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
765 }
766 static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
767 {
768 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
769 }
770 static inline int pci_write_config_dword(struct pci_dev *dev, int where,
771 u32 val)
772 {
773 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
774 }
775
776 int __must_check pci_enable_device(struct pci_dev *dev);
777 int __must_check pci_enable_device_io(struct pci_dev *dev);
778 int __must_check pci_enable_device_mem(struct pci_dev *dev);
779 int __must_check pci_reenable_device(struct pci_dev *);
780 int __must_check pcim_enable_device(struct pci_dev *pdev);
781 void pcim_pin_device(struct pci_dev *pdev);
782
783 static inline int pci_is_enabled(struct pci_dev *pdev)
784 {
785 return (atomic_read(&pdev->enable_cnt) > 0);
786 }
787
788 static inline int pci_is_managed(struct pci_dev *pdev)
789 {
790 return pdev->is_managed;
791 }
792
793 void pci_disable_device(struct pci_dev *dev);
794
795 extern unsigned int pcibios_max_latency;
796 void pci_set_master(struct pci_dev *dev);
797 void pci_clear_master(struct pci_dev *dev);
798
799 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
800 int pci_set_cacheline_size(struct pci_dev *dev);
801 #define HAVE_PCI_SET_MWI
802 int __must_check pci_set_mwi(struct pci_dev *dev);
803 int pci_try_set_mwi(struct pci_dev *dev);
804 void pci_clear_mwi(struct pci_dev *dev);
805 void pci_intx(struct pci_dev *dev, int enable);
806 bool pci_intx_mask_supported(struct pci_dev *dev);
807 bool pci_check_and_mask_intx(struct pci_dev *dev);
808 bool pci_check_and_unmask_intx(struct pci_dev *dev);
809 void pci_msi_off(struct pci_dev *dev);
810 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
811 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
812 int pcix_get_max_mmrbc(struct pci_dev *dev);
813 int pcix_get_mmrbc(struct pci_dev *dev);
814 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
815 int pcie_get_readrq(struct pci_dev *dev);
816 int pcie_set_readrq(struct pci_dev *dev, int rq);
817 int pcie_get_mps(struct pci_dev *dev);
818 int pcie_set_mps(struct pci_dev *dev, int mps);
819 int __pci_reset_function(struct pci_dev *dev);
820 int pci_reset_function(struct pci_dev *dev);
821 void pci_update_resource(struct pci_dev *dev, int resno);
822 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
823 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
824 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
825
826 /* ROM control related routines */
827 int pci_enable_rom(struct pci_dev *pdev);
828 void pci_disable_rom(struct pci_dev *pdev);
829 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
830 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
831 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
832
833 /* Power management related routines */
834 int pci_save_state(struct pci_dev *dev);
835 void pci_restore_state(struct pci_dev *dev);
836 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
837 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state);
838 int pci_load_and_free_saved_state(struct pci_dev *dev,
839 struct pci_saved_state **state);
840 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
841 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
842 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
843 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
844 void pci_pme_active(struct pci_dev *dev, bool enable);
845 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
846 bool runtime, bool enable);
847 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
848 pci_power_t pci_target_state(struct pci_dev *dev);
849 int pci_prepare_to_sleep(struct pci_dev *dev);
850 int pci_back_from_sleep(struct pci_dev *dev);
851 bool pci_dev_run_wake(struct pci_dev *dev);
852 bool pci_check_pme_status(struct pci_dev *dev);
853 void pci_pme_wakeup_bus(struct pci_bus *bus);
854
855 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
856 bool enable)
857 {
858 return __pci_enable_wake(dev, state, false, enable);
859 }
860
861 #define PCI_EXP_IDO_REQUEST (1<<0)
862 #define PCI_EXP_IDO_COMPLETION (1<<1)
863 void pci_enable_ido(struct pci_dev *dev, unsigned long type);
864 void pci_disable_ido(struct pci_dev *dev, unsigned long type);
865
866 enum pci_obff_signal_type {
867 PCI_EXP_OBFF_SIGNAL_L0 = 0,
868 PCI_EXP_OBFF_SIGNAL_ALWAYS = 1,
869 };
870 int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
871 void pci_disable_obff(struct pci_dev *dev);
872
873 bool pci_ltr_supported(struct pci_dev *dev);
874 int pci_enable_ltr(struct pci_dev *dev);
875 void pci_disable_ltr(struct pci_dev *dev);
876 int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns);
877
878 /* For use by arch with custom probe code */
879 void set_pcie_port_type(struct pci_dev *pdev);
880 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
881
882 /* Functions for PCI Hotplug drivers to use */
883 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
884 #ifdef CONFIG_HOTPLUG
885 unsigned int pci_rescan_bus(struct pci_bus *bus);
886 #endif
887
888 /* Vital product data routines */
889 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
890 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
891 int pci_vpd_truncate(struct pci_dev *dev, size_t size);
892
893 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
894 void pci_bus_assign_resources(const struct pci_bus *bus);
895 void pci_bus_size_bridges(struct pci_bus *bus);
896 int pci_claim_resource(struct pci_dev *, int);
897 void pci_assign_unassigned_resources(void);
898 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
899 void pdev_enable_device(struct pci_dev *);
900 void pdev_sort_resources(struct pci_dev *, struct resource_list *);
901 int pci_enable_resources(struct pci_dev *, int mask);
902 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
903 int (*)(const struct pci_dev *, u8, u8));
904 #define HAVE_PCI_REQ_REGIONS 2
905 int __must_check pci_request_regions(struct pci_dev *, const char *);
906 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
907 void pci_release_regions(struct pci_dev *);
908 int __must_check pci_request_region(struct pci_dev *, int, const char *);
909 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
910 void pci_release_region(struct pci_dev *, int);
911 int pci_request_selected_regions(struct pci_dev *, int, const char *);
912 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
913 void pci_release_selected_regions(struct pci_dev *, int);
914
915 /* drivers/pci/bus.c */
916 void pci_add_resource(struct list_head *resources, struct resource *res);
917 void pci_free_resource_list(struct list_head *resources);
918 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
919 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
920 void pci_bus_remove_resources(struct pci_bus *bus);
921
922 #define pci_bus_for_each_resource(bus, res, i) \
923 for (i = 0; \
924 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
925 i++)
926
927 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
928 struct resource *res, resource_size_t size,
929 resource_size_t align, resource_size_t min,
930 unsigned int type_mask,
931 resource_size_t (*alignf)(void *,
932 const struct resource *,
933 resource_size_t,
934 resource_size_t),
935 void *alignf_data);
936 void pci_enable_bridges(struct pci_bus *bus);
937
938 /* Proper probing supporting hot-pluggable devices */
939 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
940 const char *mod_name);
941
942 /*
943 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
944 */
945 #define pci_register_driver(driver) \
946 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
947
948 void pci_unregister_driver(struct pci_driver *dev);
949 void pci_remove_behind_bridge(struct pci_dev *dev);
950 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
951 int pci_add_dynid(struct pci_driver *drv,
952 unsigned int vendor, unsigned int device,
953 unsigned int subvendor, unsigned int subdevice,
954 unsigned int class, unsigned int class_mask,
955 unsigned long driver_data);
956 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
957 struct pci_dev *dev);
958 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
959 int pass);
960
961 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
962 void *userdata);
963 int pci_cfg_space_size_ext(struct pci_dev *dev);
964 int pci_cfg_space_size(struct pci_dev *dev);
965 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
966 void pci_setup_bridge(struct pci_bus *bus);
967
968 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
969 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
970
971 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
972 unsigned int command_bits, u32 flags);
973 /* kmem_cache style wrapper around pci_alloc_consistent() */
974
975 #include <linux/pci-dma.h>
976 #include <linux/dmapool.h>
977
978 #define pci_pool dma_pool
979 #define pci_pool_create(name, pdev, size, align, allocation) \
980 dma_pool_create(name, &pdev->dev, size, align, allocation)
981 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
982 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
983 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
984
985 enum pci_dma_burst_strategy {
986 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
987 strategy_parameter is N/A */
988 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
989 byte boundaries */
990 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
991 strategy_parameter byte boundaries */
992 };
993
994 struct msix_entry {
995 u32 vector; /* kernel uses to write allocated vector */
996 u16 entry; /* driver uses to specify entry, OS writes */
997 };
998
999
1000 #ifndef CONFIG_PCI_MSI
1001 static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
1002 {
1003 return -1;
1004 }
1005
1006 static inline void pci_msi_shutdown(struct pci_dev *dev)
1007 { }
1008 static inline void pci_disable_msi(struct pci_dev *dev)
1009 { }
1010
1011 static inline int pci_msix_table_size(struct pci_dev *dev)
1012 {
1013 return 0;
1014 }
1015 static inline int pci_enable_msix(struct pci_dev *dev,
1016 struct msix_entry *entries, int nvec)
1017 {
1018 return -1;
1019 }
1020
1021 static inline void pci_msix_shutdown(struct pci_dev *dev)
1022 { }
1023 static inline void pci_disable_msix(struct pci_dev *dev)
1024 { }
1025
1026 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
1027 { }
1028
1029 static inline void pci_restore_msi_state(struct pci_dev *dev)
1030 { }
1031 static inline int pci_msi_enabled(void)
1032 {
1033 return 0;
1034 }
1035 #else
1036 extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
1037 extern void pci_msi_shutdown(struct pci_dev *dev);
1038 extern void pci_disable_msi(struct pci_dev *dev);
1039 extern int pci_msix_table_size(struct pci_dev *dev);
1040 extern int pci_enable_msix(struct pci_dev *dev,
1041 struct msix_entry *entries, int nvec);
1042 extern void pci_msix_shutdown(struct pci_dev *dev);
1043 extern void pci_disable_msix(struct pci_dev *dev);
1044 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
1045 extern void pci_restore_msi_state(struct pci_dev *dev);
1046 extern int pci_msi_enabled(void);
1047 #endif
1048
1049 #ifdef CONFIG_PCIEPORTBUS
1050 extern bool pcie_ports_disabled;
1051 extern bool pcie_ports_auto;
1052 #else
1053 #define pcie_ports_disabled true
1054 #define pcie_ports_auto false
1055 #endif
1056
1057 #ifndef CONFIG_PCIEASPM
1058 static inline int pcie_aspm_enabled(void) { return 0; }
1059 static inline bool pcie_aspm_support_enabled(void) { return false; }
1060 #else
1061 extern int pcie_aspm_enabled(void);
1062 extern bool pcie_aspm_support_enabled(void);
1063 #endif
1064
1065 #ifdef CONFIG_PCIEAER
1066 void pci_no_aer(void);
1067 bool pci_aer_available(void);
1068 #else
1069 static inline void pci_no_aer(void) { }
1070 static inline bool pci_aer_available(void) { return false; }
1071 #endif
1072
1073 #ifndef CONFIG_PCIE_ECRC
1074 static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
1075 {
1076 return;
1077 }
1078 static inline void pcie_ecrc_get_policy(char *str) {};
1079 #else
1080 extern void pcie_set_ecrc_checking(struct pci_dev *dev);
1081 extern void pcie_ecrc_get_policy(char *str);
1082 #endif
1083
1084 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
1085
1086 #ifdef CONFIG_HT_IRQ
1087 /* The functions a driver should call */
1088 int ht_create_irq(struct pci_dev *dev, int idx);
1089 void ht_destroy_irq(unsigned int irq);
1090 #endif /* CONFIG_HT_IRQ */
1091
1092 extern void pci_cfg_access_lock(struct pci_dev *dev);
1093 extern bool pci_cfg_access_trylock(struct pci_dev *dev);
1094 extern void pci_cfg_access_unlock(struct pci_dev *dev);
1095
1096 /*
1097 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1098 * a PCI domain is defined to be a set of PCI busses which share
1099 * configuration space.
1100 */
1101 #ifdef CONFIG_PCI_DOMAINS
1102 extern int pci_domains_supported;
1103 #else
1104 enum { pci_domains_supported = 0 };
1105 static inline int pci_domain_nr(struct pci_bus *bus)
1106 {
1107 return 0;
1108 }
1109
1110 static inline int pci_proc_domain(struct pci_bus *bus)
1111 {
1112 return 0;
1113 }
1114 #endif /* CONFIG_PCI_DOMAINS */
1115
1116 /* some architectures require additional setup to direct VGA traffic */
1117 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1118 unsigned int command_bits, u32 flags);
1119 extern void pci_register_set_vga_state(arch_set_vga_state_t func);
1120
1121 #else /* CONFIG_PCI is not enabled */
1122
1123 /*
1124 * If the system does not have PCI, clearly these return errors. Define
1125 * these as simple inline functions to avoid hair in drivers.
1126 */
1127
1128 #define _PCI_NOP(o, s, t) \
1129 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1130 int where, t val) \
1131 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1132
1133 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1134 _PCI_NOP(o, word, u16 x) \
1135 _PCI_NOP(o, dword, u32 x)
1136 _PCI_NOP_ALL(read, *)
1137 _PCI_NOP_ALL(write,)
1138
1139 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1140 unsigned int device,
1141 struct pci_dev *from)
1142 {
1143 return NULL;
1144 }
1145
1146 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1147 unsigned int device,
1148 unsigned int ss_vendor,
1149 unsigned int ss_device,
1150 struct pci_dev *from)
1151 {
1152 return NULL;
1153 }
1154
1155 static inline struct pci_dev *pci_get_class(unsigned int class,
1156 struct pci_dev *from)
1157 {
1158 return NULL;
1159 }
1160
1161 #define pci_dev_present(ids) (0)
1162 #define no_pci_devices() (1)
1163 #define pci_dev_put(dev) do { } while (0)
1164
1165 static inline void pci_set_master(struct pci_dev *dev)
1166 { }
1167
1168 static inline int pci_enable_device(struct pci_dev *dev)
1169 {
1170 return -EIO;
1171 }
1172
1173 static inline void pci_disable_device(struct pci_dev *dev)
1174 { }
1175
1176 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1177 {
1178 return -EIO;
1179 }
1180
1181 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1182 {
1183 return -EIO;
1184 }
1185
1186 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1187 unsigned int size)
1188 {
1189 return -EIO;
1190 }
1191
1192 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1193 unsigned long mask)
1194 {
1195 return -EIO;
1196 }
1197
1198 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1199 {
1200 return -EBUSY;
1201 }
1202
1203 static inline int __pci_register_driver(struct pci_driver *drv,
1204 struct module *owner)
1205 {
1206 return 0;
1207 }
1208
1209 static inline int pci_register_driver(struct pci_driver *drv)
1210 {
1211 return 0;
1212 }
1213
1214 static inline void pci_unregister_driver(struct pci_driver *drv)
1215 { }
1216
1217 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1218 {
1219 return 0;
1220 }
1221
1222 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1223 int cap)
1224 {
1225 return 0;
1226 }
1227
1228 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1229 {
1230 return 0;
1231 }
1232
1233 /* Power management related routines */
1234 static inline int pci_save_state(struct pci_dev *dev)
1235 {
1236 return 0;
1237 }
1238
1239 static inline void pci_restore_state(struct pci_dev *dev)
1240 { }
1241
1242 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1243 {
1244 return 0;
1245 }
1246
1247 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1248 {
1249 return 0;
1250 }
1251
1252 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1253 pm_message_t state)
1254 {
1255 return PCI_D0;
1256 }
1257
1258 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1259 int enable)
1260 {
1261 return 0;
1262 }
1263
1264 static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1265 {
1266 }
1267
1268 static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1269 {
1270 }
1271
1272 static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type)
1273 {
1274 return 0;
1275 }
1276
1277 static inline void pci_disable_obff(struct pci_dev *dev)
1278 {
1279 }
1280
1281 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1282 {
1283 return -EIO;
1284 }
1285
1286 static inline void pci_release_regions(struct pci_dev *dev)
1287 { }
1288
1289 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1290
1291 static inline void pci_block_cfg_access(struct pci_dev *dev)
1292 { }
1293
1294 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1295 { return 0; }
1296
1297 static inline void pci_unblock_cfg_access(struct pci_dev *dev)
1298 { }
1299
1300 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1301 { return NULL; }
1302
1303 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1304 unsigned int devfn)
1305 { return NULL; }
1306
1307 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1308 unsigned int devfn)
1309 { return NULL; }
1310
1311 static inline int pci_domain_nr(struct pci_bus *bus)
1312 { return 0; }
1313
1314 #define dev_is_pci(d) (false)
1315 #define dev_is_pf(d) (false)
1316 #define dev_num_vf(d) (0)
1317 #endif /* CONFIG_PCI */
1318
1319 /* Include architecture-dependent settings and functions */
1320
1321 #include <asm/pci.h>
1322
1323 #ifndef PCIBIOS_MAX_MEM_32
1324 #define PCIBIOS_MAX_MEM_32 (-1)
1325 #endif
1326
1327 /* these helpers provide future and backwards compatibility
1328 * for accessing popular PCI BAR info */
1329 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1330 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1331 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1332 #define pci_resource_len(dev,bar) \
1333 ((pci_resource_start((dev), (bar)) == 0 && \
1334 pci_resource_end((dev), (bar)) == \
1335 pci_resource_start((dev), (bar))) ? 0 : \
1336 \
1337 (pci_resource_end((dev), (bar)) - \
1338 pci_resource_start((dev), (bar)) + 1))
1339
1340 /* Similar to the helpers above, these manipulate per-pci_dev
1341 * driver-specific data. They are really just a wrapper around
1342 * the generic device structure functions of these calls.
1343 */
1344 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1345 {
1346 return dev_get_drvdata(&pdev->dev);
1347 }
1348
1349 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1350 {
1351 dev_set_drvdata(&pdev->dev, data);
1352 }
1353
1354 /* If you want to know what to call your pci_dev, ask this function.
1355 * Again, it's a wrapper around the generic device.
1356 */
1357 static inline const char *pci_name(const struct pci_dev *pdev)
1358 {
1359 return dev_name(&pdev->dev);
1360 }
1361
1362
1363 /* Some archs don't want to expose struct resource to userland as-is
1364 * in sysfs and /proc
1365 */
1366 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1367 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1368 const struct resource *rsrc, resource_size_t *start,
1369 resource_size_t *end)
1370 {
1371 *start = rsrc->start;
1372 *end = rsrc->end;
1373 }
1374 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1375
1376
1377 /*
1378 * The world is not perfect and supplies us with broken PCI devices.
1379 * For at least a part of these bugs we need a work-around, so both
1380 * generic (drivers/pci/quirks.c) and per-architecture code can define
1381 * fixup hooks to be called for particular buggy devices.
1382 */
1383
1384 struct pci_fixup {
1385 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
1386 void (*hook)(struct pci_dev *dev);
1387 };
1388
1389 enum pci_fixup_pass {
1390 pci_fixup_early, /* Before probing BARs */
1391 pci_fixup_header, /* After reading configuration header */
1392 pci_fixup_final, /* Final phase of device fixups */
1393 pci_fixup_enable, /* pci_enable_device() time */
1394 pci_fixup_resume, /* pci_device_resume() */
1395 pci_fixup_suspend, /* pci_device_suspend */
1396 pci_fixup_resume_early, /* pci_device_resume_early() */
1397 };
1398
1399 /* Anonymous variables would be nice... */
1400 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
1401 static const struct pci_fixup __pci_fixup_##name __used \
1402 __attribute__((__section__(#section))) = { vendor, device, hook };
1403 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1404 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1405 vendor##device##hook, vendor, device, hook)
1406 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1407 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1408 vendor##device##hook, vendor, device, hook)
1409 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1410 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1411 vendor##device##hook, vendor, device, hook)
1412 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1413 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1414 vendor##device##hook, vendor, device, hook)
1415 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1416 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1417 resume##vendor##device##hook, vendor, device, hook)
1418 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1419 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1420 resume_early##vendor##device##hook, vendor, device, hook)
1421 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1422 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1423 suspend##vendor##device##hook, vendor, device, hook)
1424
1425 #ifdef CONFIG_PCI_QUIRKS
1426 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1427 #else
1428 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1429 struct pci_dev *dev) {}
1430 #endif
1431
1432 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1433 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1434 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1435 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1436 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1437 const char *name);
1438 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1439
1440 extern int pci_pci_problems;
1441 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1442 #define PCIPCI_TRITON 2
1443 #define PCIPCI_NATOMA 4
1444 #define PCIPCI_VIAETBF 8
1445 #define PCIPCI_VSFX 16
1446 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1447 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1448
1449 extern unsigned long pci_cardbus_io_size;
1450 extern unsigned long pci_cardbus_mem_size;
1451 extern u8 __devinitdata pci_dfl_cache_line_size;
1452 extern u8 pci_cache_line_size;
1453
1454 extern unsigned long pci_hotplug_io_size;
1455 extern unsigned long pci_hotplug_mem_size;
1456
1457 /* Architecture specific versions may override these (weak) */
1458 int pcibios_add_platform_entries(struct pci_dev *dev);
1459 void pcibios_disable_device(struct pci_dev *dev);
1460 void pcibios_set_master(struct pci_dev *dev);
1461 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1462 enum pcie_reset_state state);
1463
1464 #ifdef CONFIG_PCI_MMCONFIG
1465 extern void __init pci_mmcfg_early_init(void);
1466 extern void __init pci_mmcfg_late_init(void);
1467 #else
1468 static inline void pci_mmcfg_early_init(void) { }
1469 static inline void pci_mmcfg_late_init(void) { }
1470 #endif
1471
1472 int pci_ext_cfg_avail(struct pci_dev *dev);
1473
1474 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1475
1476 #ifdef CONFIG_PCI_IOV
1477 extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1478 extern void pci_disable_sriov(struct pci_dev *dev);
1479 extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1480 extern int pci_num_vf(struct pci_dev *dev);
1481 #else
1482 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1483 {
1484 return -ENODEV;
1485 }
1486 static inline void pci_disable_sriov(struct pci_dev *dev)
1487 {
1488 }
1489 static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1490 {
1491 return IRQ_NONE;
1492 }
1493 static inline int pci_num_vf(struct pci_dev *dev)
1494 {
1495 return 0;
1496 }
1497 #endif
1498
1499 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1500 extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1501 extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1502 #endif
1503
1504 /**
1505 * pci_pcie_cap - get the saved PCIe capability offset
1506 * @dev: PCI device
1507 *
1508 * PCIe capability offset is calculated at PCI device initialization
1509 * time and saved in the data structure. This function returns saved
1510 * PCIe capability offset. Using this instead of pci_find_capability()
1511 * reduces unnecessary search in the PCI configuration space. If you
1512 * need to calculate PCIe capability offset from raw device for some
1513 * reasons, please use pci_find_capability() instead.
1514 */
1515 static inline int pci_pcie_cap(struct pci_dev *dev)
1516 {
1517 return dev->pcie_cap;
1518 }
1519
1520 /**
1521 * pci_is_pcie - check if the PCI device is PCI Express capable
1522 * @dev: PCI device
1523 *
1524 * Retrun true if the PCI device is PCI Express capable, false otherwise.
1525 */
1526 static inline bool pci_is_pcie(struct pci_dev *dev)
1527 {
1528 return !!pci_pcie_cap(dev);
1529 }
1530
1531 void pci_request_acs(void);
1532
1533
1534 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1535 #define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT)
1536
1537 /* Large Resource Data Type Tag Item Names */
1538 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1539 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1540 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1541
1542 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1543 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1544 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1545
1546 /* Small Resource Data Type Tag Item Names */
1547 #define PCI_VPD_STIN_END 0x78 /* End */
1548
1549 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1550
1551 #define PCI_VPD_SRDT_TIN_MASK 0x78
1552 #define PCI_VPD_SRDT_LEN_MASK 0x07
1553
1554 #define PCI_VPD_LRDT_TAG_SIZE 3
1555 #define PCI_VPD_SRDT_TAG_SIZE 1
1556
1557 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1558
1559 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1560 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1561 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1562 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1563
1564 /**
1565 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1566 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1567 *
1568 * Returns the extracted Large Resource Data Type length.
1569 */
1570 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1571 {
1572 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1573 }
1574
1575 /**
1576 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1577 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1578 *
1579 * Returns the extracted Small Resource Data Type length.
1580 */
1581 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1582 {
1583 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1584 }
1585
1586 /**
1587 * pci_vpd_info_field_size - Extracts the information field length
1588 * @lrdt: Pointer to the beginning of an information field header
1589 *
1590 * Returns the extracted information field length.
1591 */
1592 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1593 {
1594 return info_field[2];
1595 }
1596
1597 /**
1598 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1599 * @buf: Pointer to buffered vpd data
1600 * @off: The offset into the buffer at which to begin the search
1601 * @len: The length of the vpd buffer
1602 * @rdt: The Resource Data Type to search for
1603 *
1604 * Returns the index where the Resource Data Type was found or
1605 * -ENOENT otherwise.
1606 */
1607 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1608
1609 /**
1610 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1611 * @buf: Pointer to buffered vpd data
1612 * @off: The offset into the buffer at which to begin the search
1613 * @len: The length of the buffer area, relative to off, in which to search
1614 * @kw: The keyword to search for
1615 *
1616 * Returns the index where the information field keyword was found or
1617 * -ENOENT otherwise.
1618 */
1619 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1620 unsigned int len, const char *kw);
1621
1622 /* PCI <-> OF binding helpers */
1623 #ifdef CONFIG_OF
1624 struct device_node;
1625 extern void pci_set_of_node(struct pci_dev *dev);
1626 extern void pci_release_of_node(struct pci_dev *dev);
1627 extern void pci_set_bus_of_node(struct pci_bus *bus);
1628 extern void pci_release_bus_of_node(struct pci_bus *bus);
1629
1630 /* Arch may override this (weak) */
1631 extern struct device_node * __weak pcibios_get_phb_of_node(struct pci_bus *bus);
1632
1633 static inline struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
1634 {
1635 return pdev ? pdev->dev.of_node : NULL;
1636 }
1637
1638 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1639 {
1640 return bus ? bus->dev.of_node : NULL;
1641 }
1642
1643 #else /* CONFIG_OF */
1644 static inline void pci_set_of_node(struct pci_dev *dev) { }
1645 static inline void pci_release_of_node(struct pci_dev *dev) { }
1646 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1647 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1648 #endif /* CONFIG_OF */
1649
1650 /**
1651 * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device
1652 * @pdev: the PCI device
1653 *
1654 * if the device is PCIE, return NULL
1655 * if the device isn't connected to a PCIe bridge (that is its parent is a
1656 * legacy PCI bridge and the bridge is directly connected to bus 0), return its
1657 * parent
1658 */
1659 struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
1660
1661 #endif /* __KERNEL__ */
1662 #endif /* LINUX_PCI_H */