Staging: hv: mousevsc: Change the allocation flags to reflect interrupt context
[zen-stable.git] / arch / sparc / include / asm / asm.h
blobe8e1d94b4cc9ee9760b2a97ce5da16ab54474a31
1 #ifndef _SPARC_ASM_H
2 #define _SPARC_ASM_H
4 /* Macros to assist the sharing of assembler code between 32-bit and
5 * 64-bit sparc.
6 */
8 #ifdef CONFIG_SPARC64
9 #define BRANCH32(TYPE, PREDICT, DEST) \
10 TYPE,PREDICT %icc, DEST
11 #define BRANCH32_ANNUL(TYPE, PREDICT, DEST) \
12 TYPE,a,PREDICT %icc, DEST
13 #define BRANCH_REG_ZERO(PREDICT, REG, DEST) \
14 brz,PREDICT REG, DEST
15 #define BRANCH_REG_ZERO_ANNUL(PREDICT, REG, DEST) \
16 brz,a,PREDICT REG, DEST
17 #define BRANCH_REG_NOT_ZERO(PREDICT, REG, DEST) \
18 brnz,PREDICT REG, DEST
19 #define BRANCH_REG_NOT_ZERO_ANNUL(PREDICT, REG, DEST) \
20 brnz,a,PREDICT REG, DEST
21 #else
22 #define BRANCH32(TYPE, PREDICT, DEST) \
23 TYPE DEST
24 #define BRANCH32_ANNUL(TYPE, PREDICT, DEST) \
25 TYPE,a DEST
26 #define BRANCH_REG_ZERO(PREDICT, REG, DEST) \
27 cmp REG, 0; \
28 be DEST
29 #define BRANCH_REG_ZERO_ANNUL(PREDICT, REG, DEST) \
30 cmp REG, 0; \
31 be,a DEST
32 #define BRANCH_REG_NOT_ZERO(PREDICT, REG, DEST) \
33 cmp REG, 0; \
34 bne DEST
35 #define BRANCH_REG_NOT_ZERO_ANNUL(PREDICT, REG, DEST) \
36 cmp REG, 0; \
37 bne,a DEST
38 #endif
40 #endif /* _SPARC_ASM_H */