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Staging: hv: mousevsc: Change the allocation flags to reflect interrupt context
[zen-stable.git] / arch / sparc / mm / init_64.c
blob581531dbc8b57ee299b62a13b15f8877891af690
1 /*
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
14 #include <linux/mm.h>
15 #include <linux/hugetlb.h>
16 #include <linux/initrd.h>
17 #include <linux/swap.h>
18 #include <linux/pagemap.h>
19 #include <linux/poison.h>
20 #include <linux/fs.h>
21 #include <linux/seq_file.h>
22 #include <linux/kprobes.h>
23 #include <linux/cache.h>
24 #include <linux/sort.h>
25 #include <linux/percpu.h>
26 #include <linux/memblock.h>
27 #include <linux/mmzone.h>
28 #include <linux/gfp.h>
29
30 #include <asm/head.h>
31 #include <asm/system.h>
32 #include <asm/page.h>
33 #include <asm/pgalloc.h>
34 #include <asm/pgtable.h>
35 #include <asm/oplib.h>
36 #include <asm/iommu.h>
37 #include <asm/io.h>
38 #include <asm/uaccess.h>
39 #include <asm/mmu_context.h>
40 #include <asm/tlbflush.h>
41 #include <asm/dma.h>
42 #include <asm/starfire.h>
43 #include <asm/tlb.h>
44 #include <asm/spitfire.h>
45 #include <asm/sections.h>
46 #include <asm/tsb.h>
47 #include <asm/hypervisor.h>
48 #include <asm/prom.h>
49 #include <asm/mdesc.h>
50 #include <asm/cpudata.h>
51 #include <asm/irq.h>
52
53 #include "init_64.h"
54
55 unsigned long kern_linear_pte_xor[2] __read_mostly;
56
57 /* A bitmap, one bit for every 256MB of physical memory. If the bit
58 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
59 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
60 */
61 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
62
63 #ifndef CONFIG_DEBUG_PAGEALLOC
64 /* A special kernel TSB for 4MB and 256MB linear mappings.
65 * Space is allocated for this right after the trap table
66 * in arch/sparc64/kernel/head.S
67 */
68 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
69 #endif
70
71 #define MAX_BANKS 32
72
73 static struct linux_prom64_registers pavail[MAX_BANKS] __devinitdata;
74 static int pavail_ents __devinitdata;
75
76 static int cmp_p64(const void *a, const void *b)
77 {
78 const struct linux_prom64_registers *x = a, *y = b;
79
80 if (x->phys_addr > y->phys_addr)
81 return 1;
82 if (x->phys_addr < y->phys_addr)
83 return -1;
84 return 0;
85 }
86
87 static void __init read_obp_memory(const char *property,
88 struct linux_prom64_registers *regs,
89 int *num_ents)
90 {
91 phandle node = prom_finddevice("/memory");
92 int prop_size = prom_getproplen(node, property);
93 int ents, ret, i;
94
95 ents = prop_size / sizeof(struct linux_prom64_registers);
96 if (ents > MAX_BANKS) {
97 prom_printf("The machine has more %s property entries than "
98 "this kernel can support (%d).\n",
99 property, MAX_BANKS);
100 prom_halt();
101 }
102
103 ret = prom_getproperty(node, property, (char *) regs, prop_size);
104 if (ret == -1) {
105 prom_printf("Couldn't get %s property from /memory.\n");
106 prom_halt();
107 }
108
109 /* Sanitize what we got from the firmware, by page aligning
110 * everything.
111 */
112 for (i = 0; i < ents; i++) {
113 unsigned long base, size;
114
115 base = regs[i].phys_addr;
116 size = regs[i].reg_size;
117
118 size &= PAGE_MASK;
119 if (base & ~PAGE_MASK) {
120 unsigned long new_base = PAGE_ALIGN(base);
121
122 size -= new_base - base;
123 if ((long) size < 0L)
124 size = 0UL;
125 base = new_base;
126 }
127 if (size == 0UL) {
128 /* If it is empty, simply get rid of it.
129 * This simplifies the logic of the other
130 * functions that process these arrays.
131 */
132 memmove(&regs[i], &regs[i + 1],
133 (ents - i - 1) * sizeof(regs[0]));
134 i--;
135 ents--;
136 continue;
137 }
138 regs[i].phys_addr = base;
139 regs[i].reg_size = size;
140 }
141
142 *num_ents = ents;
143
144 sort(regs, ents, sizeof(struct linux_prom64_registers),
145 cmp_p64, NULL);
146 }
147
148 unsigned long sparc64_valid_addr_bitmap[VALID_ADDR_BITMAP_BYTES /
149 sizeof(unsigned long)];
150 EXPORT_SYMBOL(sparc64_valid_addr_bitmap);
151
152 /* Kernel physical address base and size in bytes. */
153 unsigned long kern_base __read_mostly;
154 unsigned long kern_size __read_mostly;
155
156 /* Initial ramdisk setup */
157 extern unsigned long sparc_ramdisk_image64;
158 extern unsigned int sparc_ramdisk_image;
159 extern unsigned int sparc_ramdisk_size;
160
161 struct page *mem_map_zero __read_mostly;
162 EXPORT_SYMBOL(mem_map_zero);
163
164 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
165
166 unsigned long sparc64_kern_pri_context __read_mostly;
167 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
168 unsigned long sparc64_kern_sec_context __read_mostly;
169
170 int num_kernel_image_mappings;
171
172 #ifdef CONFIG_DEBUG_DCFLUSH
173 atomic_t dcpage_flushes = ATOMIC_INIT(0);
174 #ifdef CONFIG_SMP
175 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
176 #endif
177 #endif
178
179 inline void flush_dcache_page_impl(struct page *page)
180 {
181 BUG_ON(tlb_type == hypervisor);
182 #ifdef CONFIG_DEBUG_DCFLUSH
183 atomic_inc(&dcpage_flushes);
184 #endif
185
186 #ifdef DCACHE_ALIASING_POSSIBLE
187 __flush_dcache_page(page_address(page),
188 ((tlb_type == spitfire) &&
189 page_mapping(page) != NULL));
190 #else
191 if (page_mapping(page) != NULL &&
192 tlb_type == spitfire)
193 __flush_icache_page(__pa(page_address(page)));
194 #endif
195 }
196
197 #define PG_dcache_dirty PG_arch_1
198 #define PG_dcache_cpu_shift 32UL
199 #define PG_dcache_cpu_mask \
200 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
201
202 #define dcache_dirty_cpu(page) \
203 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
204
205 static inline void set_dcache_dirty(struct page *page, int this_cpu)
206 {
207 unsigned long mask = this_cpu;
208 unsigned long non_cpu_bits;
209
210 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
211 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
212
213 __asm__ __volatile__("1:\n\t"
214 "ldx [%2], %%g7\n\t"
215 "and %%g7, %1, %%g1\n\t"
216 "or %%g1, %0, %%g1\n\t"
217 "casx [%2], %%g7, %%g1\n\t"
218 "cmp %%g7, %%g1\n\t"
219 "bne,pn %%xcc, 1b\n\t"
220 " nop"
221 : /* no outputs */
222 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
223 : "g1", "g7");
224 }
225
226 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
227 {
228 unsigned long mask = (1UL << PG_dcache_dirty);
229
230 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
231 "1:\n\t"
232 "ldx [%2], %%g7\n\t"
233 "srlx %%g7, %4, %%g1\n\t"
234 "and %%g1, %3, %%g1\n\t"
235 "cmp %%g1, %0\n\t"
236 "bne,pn %%icc, 2f\n\t"
237 " andn %%g7, %1, %%g1\n\t"
238 "casx [%2], %%g7, %%g1\n\t"
239 "cmp %%g7, %%g1\n\t"
240 "bne,pn %%xcc, 1b\n\t"
241 " nop\n"
242 "2:"
243 : /* no outputs */
244 : "r" (cpu), "r" (mask), "r" (&page->flags),
245 "i" (PG_dcache_cpu_mask),
246 "i" (PG_dcache_cpu_shift)
247 : "g1", "g7");
248 }
249
250 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
251 {
252 unsigned long tsb_addr = (unsigned long) ent;
253
254 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
255 tsb_addr = __pa(tsb_addr);
256
257 __tsb_insert(tsb_addr, tag, pte);
258 }
259
260 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
261 unsigned long _PAGE_SZBITS __read_mostly;
262
263 static void flush_dcache(unsigned long pfn)
264 {
265 struct page *page;
266
267 page = pfn_to_page(pfn);
268 if (page) {
269 unsigned long pg_flags;
270
271 pg_flags = page->flags;
272 if (pg_flags & (1UL << PG_dcache_dirty)) {
273 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
274 PG_dcache_cpu_mask);
275 int this_cpu = get_cpu();
276
277 /* This is just to optimize away some function calls
278 * in the SMP case.
279 */
280 if (cpu == this_cpu)
281 flush_dcache_page_impl(page);
282 else
283 smp_flush_dcache_page_impl(page, cpu);
284
285 clear_dcache_dirty_cpu(page, cpu);
286
287 put_cpu();
288 }
289 }
290 }
291
292 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
293 {
294 struct mm_struct *mm;
295 struct tsb *tsb;
296 unsigned long tag, flags;
297 unsigned long tsb_index, tsb_hash_shift;
298 pte_t pte = *ptep;
299
300 if (tlb_type != hypervisor) {
301 unsigned long pfn = pte_pfn(pte);
302
303 if (pfn_valid(pfn))
304 flush_dcache(pfn);
305 }
306
307 mm = vma->vm_mm;
308
309 tsb_index = MM_TSB_BASE;
310 tsb_hash_shift = PAGE_SHIFT;
311
312 spin_lock_irqsave(&mm->context.lock, flags);
313
314 #ifdef CONFIG_HUGETLB_PAGE
315 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
316 if ((tlb_type == hypervisor &&
317 (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
318 (tlb_type != hypervisor &&
319 (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
320 tsb_index = MM_TSB_HUGE;
321 tsb_hash_shift = HPAGE_SHIFT;
322 }
323 }
324 #endif
325
326 tsb = mm->context.tsb_block[tsb_index].tsb;
327 tsb += ((address >> tsb_hash_shift) &
328 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
329 tag = (address >> 22UL);
330 tsb_insert(tsb, tag, pte_val(pte));
331
332 spin_unlock_irqrestore(&mm->context.lock, flags);
333 }
334
335 void flush_dcache_page(struct page *page)
336 {
337 struct address_space *mapping;
338 int this_cpu;
339
340 if (tlb_type == hypervisor)
341 return;
342
343 /* Do not bother with the expensive D-cache flush if it
344 * is merely the zero page. The 'bigcore' testcase in GDB
345 * causes this case to run millions of times.
346 */
347 if (page == ZERO_PAGE(0))
348 return;
349
350 this_cpu = get_cpu();
351
352 mapping = page_mapping(page);
353 if (mapping && !mapping_mapped(mapping)) {
354 int dirty = test_bit(PG_dcache_dirty, &page->flags);
355 if (dirty) {
356 int dirty_cpu = dcache_dirty_cpu(page);
357
358 if (dirty_cpu == this_cpu)
359 goto out;
360 smp_flush_dcache_page_impl(page, dirty_cpu);
361 }
362 set_dcache_dirty(page, this_cpu);
363 } else {
364 /* We could delay the flush for the !page_mapping
365 * case too. But that case is for exec env/arg
366 * pages and those are %99 certainly going to get
367 * faulted into the tlb (and thus flushed) anyways.
368 */
369 flush_dcache_page_impl(page);
370 }
371
372 out:
373 put_cpu();
374 }
375 EXPORT_SYMBOL(flush_dcache_page);
376
377 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
378 {
379 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
380 if (tlb_type == spitfire) {
381 unsigned long kaddr;
382
383 /* This code only runs on Spitfire cpus so this is
384 * why we can assume _PAGE_PADDR_4U.
385 */
386 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
387 unsigned long paddr, mask = _PAGE_PADDR_4U;
388
389 if (kaddr >= PAGE_OFFSET)
390 paddr = kaddr & mask;
391 else {
392 pgd_t *pgdp = pgd_offset_k(kaddr);
393 pud_t *pudp = pud_offset(pgdp, kaddr);
394 pmd_t *pmdp = pmd_offset(pudp, kaddr);
395 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
396
397 paddr = pte_val(*ptep) & mask;
398 }
399 __flush_icache_page(paddr);
400 }
401 }
402 }
403 EXPORT_SYMBOL(flush_icache_range);
404
405 void mmu_info(struct seq_file *m)
406 {
407 if (tlb_type == cheetah)
408 seq_printf(m, "MMU Type\t: Cheetah\n");
409 else if (tlb_type == cheetah_plus)
410 seq_printf(m, "MMU Type\t: Cheetah+\n");
411 else if (tlb_type == spitfire)
412 seq_printf(m, "MMU Type\t: Spitfire\n");
413 else if (tlb_type == hypervisor)
414 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
415 else
416 seq_printf(m, "MMU Type\t: ???\n");
417
418 #ifdef CONFIG_DEBUG_DCFLUSH
419 seq_printf(m, "DCPageFlushes\t: %d\n",
420 atomic_read(&dcpage_flushes));
421 #ifdef CONFIG_SMP
422 seq_printf(m, "DCPageFlushesXC\t: %d\n",
423 atomic_read(&dcpage_flushes_xcall));
424 #endif /* CONFIG_SMP */
425 #endif /* CONFIG_DEBUG_DCFLUSH */
426 }
427
428 struct linux_prom_translation prom_trans[512] __read_mostly;
429 unsigned int prom_trans_ents __read_mostly;
430
431 unsigned long kern_locked_tte_data;
432
433 /* The obp translations are saved based on 8k pagesize, since obp can
434 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
435 * HI_OBP_ADDRESS range are handled in ktlb.S.
436 */
437 static inline int in_obp_range(unsigned long vaddr)
438 {
439 return (vaddr >= LOW_OBP_ADDRESS &&
440 vaddr < HI_OBP_ADDRESS);
441 }
442
443 static int cmp_ptrans(const void *a, const void *b)
444 {
445 const struct linux_prom_translation *x = a, *y = b;
446
447 if (x->virt > y->virt)
448 return 1;
449 if (x->virt < y->virt)
450 return -1;
451 return 0;
452 }
453
454 /* Read OBP translations property into 'prom_trans[]'. */
455 static void __init read_obp_translations(void)
456 {
457 int n, node, ents, first, last, i;
458
459 node = prom_finddevice("/virtual-memory");
460 n = prom_getproplen(node, "translations");
461 if (unlikely(n == 0 || n == -1)) {
462 prom_printf("prom_mappings: Couldn't get size.\n");
463 prom_halt();
464 }
465 if (unlikely(n > sizeof(prom_trans))) {
466 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
467 prom_halt();
468 }
469
470 if ((n = prom_getproperty(node, "translations",
471 (char *)&prom_trans[0],
472 sizeof(prom_trans))) == -1) {
473 prom_printf("prom_mappings: Couldn't get property.\n");
474 prom_halt();
475 }
476
477 n = n / sizeof(struct linux_prom_translation);
478
479 ents = n;
480
481 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
482 cmp_ptrans, NULL);
483
484 /* Now kick out all the non-OBP entries. */
485 for (i = 0; i < ents; i++) {
486 if (in_obp_range(prom_trans[i].virt))
487 break;
488 }
489 first = i;
490 for (; i < ents; i++) {
491 if (!in_obp_range(prom_trans[i].virt))
492 break;
493 }
494 last = i;
495
496 for (i = 0; i < (last - first); i++) {
497 struct linux_prom_translation *src = &prom_trans[i + first];
498 struct linux_prom_translation *dest = &prom_trans[i];
499
500 *dest = *src;
501 }
502 for (; i < ents; i++) {
503 struct linux_prom_translation *dest = &prom_trans[i];
504 dest->virt = dest->size = dest->data = 0x0UL;
505 }
506
507 prom_trans_ents = last - first;
508
509 if (tlb_type == spitfire) {
510 /* Clear diag TTE bits. */
511 for (i = 0; i < prom_trans_ents; i++)
512 prom_trans[i].data &= ~0x0003fe0000000000UL;
513 }
514 }
515
516 static void __init hypervisor_tlb_lock(unsigned long vaddr,
517 unsigned long pte,
518 unsigned long mmu)
519 {
520 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
521
522 if (ret != 0) {
523 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
524 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
525 prom_halt();
526 }
527 }
528
529 static unsigned long kern_large_tte(unsigned long paddr);
530
531 static void __init remap_kernel(void)
532 {
533 unsigned long phys_page, tte_vaddr, tte_data;
534 int i, tlb_ent = sparc64_highest_locked_tlbent();
535
536 tte_vaddr = (unsigned long) KERNBASE;
537 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
538 tte_data = kern_large_tte(phys_page);
539
540 kern_locked_tte_data = tte_data;
541
542 /* Now lock us into the TLBs via Hypervisor or OBP. */
543 if (tlb_type == hypervisor) {
544 for (i = 0; i < num_kernel_image_mappings; i++) {
545 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
546 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
547 tte_vaddr += 0x400000;
548 tte_data += 0x400000;
549 }
550 } else {
551 for (i = 0; i < num_kernel_image_mappings; i++) {
552 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
553 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
554 tte_vaddr += 0x400000;
555 tte_data += 0x400000;
556 }
557 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
558 }
559 if (tlb_type == cheetah_plus) {
560 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
561 CTX_CHEETAH_PLUS_NUC);
562 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
563 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
564 }
565 }
566
567
568 static void __init inherit_prom_mappings(void)
569 {
570 /* Now fixup OBP's idea about where we really are mapped. */
571 printk("Remapping the kernel... ");
572 remap_kernel();
573 printk("done.\n");
574 }
575
576 void prom_world(int enter)
577 {
578 if (!enter)
579 set_fs((mm_segment_t) { get_thread_current_ds() });
580
581 __asm__ __volatile__("flushw");
582 }
583
584 void __flush_dcache_range(unsigned long start, unsigned long end)
585 {
586 unsigned long va;
587
588 if (tlb_type == spitfire) {
589 int n = 0;
590
591 for (va = start; va < end; va += 32) {
592 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
593 if (++n >= 512)
594 break;
595 }
596 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
597 start = __pa(start);
598 end = __pa(end);
599 for (va = start; va < end; va += 32)
600 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
601 "membar #Sync"
602 : /* no outputs */
603 : "r" (va),
604 "i" (ASI_DCACHE_INVALIDATE));
605 }
606 }
607 EXPORT_SYMBOL(__flush_dcache_range);
608
609 /* get_new_mmu_context() uses "cache + 1". */
610 DEFINE_SPINLOCK(ctx_alloc_lock);
611 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
612 #define MAX_CTX_NR (1UL << CTX_NR_BITS)
613 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
614 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
615
616 /* Caller does TLB context flushing on local CPU if necessary.
617 * The caller also ensures that CTX_VALID(mm->context) is false.
618 *
619 * We must be careful about boundary cases so that we never
620 * let the user have CTX 0 (nucleus) or we ever use a CTX
621 * version of zero (and thus NO_CONTEXT would not be caught
622 * by version mis-match tests in mmu_context.h).
623 *
624 * Always invoked with interrupts disabled.
625 */
626 void get_new_mmu_context(struct mm_struct *mm)
627 {
628 unsigned long ctx, new_ctx;
629 unsigned long orig_pgsz_bits;
630 unsigned long flags;
631 int new_version;
632
633 spin_lock_irqsave(&ctx_alloc_lock, flags);
634 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
635 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
636 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
637 new_version = 0;
638 if (new_ctx >= (1 << CTX_NR_BITS)) {
639 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
640 if (new_ctx >= ctx) {
641 int i;
642 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
643 CTX_FIRST_VERSION;
644 if (new_ctx == 1)
645 new_ctx = CTX_FIRST_VERSION;
646
647 /* Don't call memset, for 16 entries that's just
648 * plain silly...
649 */
650 mmu_context_bmap[0] = 3;
651 mmu_context_bmap[1] = 0;
652 mmu_context_bmap[2] = 0;
653 mmu_context_bmap[3] = 0;
654 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
655 mmu_context_bmap[i + 0] = 0;
656 mmu_context_bmap[i + 1] = 0;
657 mmu_context_bmap[i + 2] = 0;
658 mmu_context_bmap[i + 3] = 0;
659 }
660 new_version = 1;
661 goto out;
662 }
663 }
664 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
665 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
666 out:
667 tlb_context_cache = new_ctx;
668 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
669 spin_unlock_irqrestore(&ctx_alloc_lock, flags);
670
671 if (unlikely(new_version))
672 smp_new_mmu_context_version();
673 }
674
675 static int numa_enabled = 1;
676 static int numa_debug;
677
678 static int __init early_numa(char *p)
679 {
680 if (!p)
681 return 0;
682
683 if (strstr(p, "off"))
684 numa_enabled = 0;
685
686 if (strstr(p, "debug"))
687 numa_debug = 1;
688
689 return 0;
690 }
691 early_param("numa", early_numa);
692
693 #define numadbg(f, a...) \
694 do { if (numa_debug) \
695 printk(KERN_INFO f, ## a); \
696 } while (0)
697
698 static void __init find_ramdisk(unsigned long phys_base)
699 {
700 #ifdef CONFIG_BLK_DEV_INITRD
701 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
702 unsigned long ramdisk_image;
703
704 /* Older versions of the bootloader only supported a
705 * 32-bit physical address for the ramdisk image
706 * location, stored at sparc_ramdisk_image. Newer
707 * SILO versions set sparc_ramdisk_image to zero and
708 * provide a full 64-bit physical address at
709 * sparc_ramdisk_image64.
710 */
711 ramdisk_image = sparc_ramdisk_image;
712 if (!ramdisk_image)
713 ramdisk_image = sparc_ramdisk_image64;
714
715 /* Another bootloader quirk. The bootloader normalizes
716 * the physical address to KERNBASE, so we have to
717 * factor that back out and add in the lowest valid
718 * physical page address to get the true physical address.
719 */
720 ramdisk_image -= KERNBASE;
721 ramdisk_image += phys_base;
722
723 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
724 ramdisk_image, sparc_ramdisk_size);
725
726 initrd_start = ramdisk_image;
727 initrd_end = ramdisk_image + sparc_ramdisk_size;
728
729 memblock_reserve(initrd_start, sparc_ramdisk_size);
730
731 initrd_start += PAGE_OFFSET;
732 initrd_end += PAGE_OFFSET;
733 }
734 #endif
735 }
736
737 struct node_mem_mask {
738 unsigned long mask;
739 unsigned long val;
740 unsigned long bootmem_paddr;
741 };
742 static struct node_mem_mask node_masks[MAX_NUMNODES];
743 static int num_node_masks;
744
745 int numa_cpu_lookup_table[NR_CPUS];
746 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
747
748 #ifdef CONFIG_NEED_MULTIPLE_NODES
749
750 struct mdesc_mblock {
751 u64 base;
752 u64 size;
753 u64 offset; /* RA-to-PA */
754 };
755 static struct mdesc_mblock *mblocks;
756 static int num_mblocks;
757
758 static unsigned long ra_to_pa(unsigned long addr)
759 {
760 int i;
761
762 for (i = 0; i < num_mblocks; i++) {
763 struct mdesc_mblock *m = &mblocks[i];
764
765 if (addr >= m->base &&
766 addr < (m->base + m->size)) {
767 addr += m->offset;
768 break;
769 }
770 }
771 return addr;
772 }
773
774 static int find_node(unsigned long addr)
775 {
776 int i;
777
778 addr = ra_to_pa(addr);
779 for (i = 0; i < num_node_masks; i++) {
780 struct node_mem_mask *p = &node_masks[i];
781
782 if ((addr & p->mask) == p->val)
783 return i;
784 }
785 return -1;
786 }
787
788 u64 memblock_nid_range(u64 start, u64 end, int *nid)
789 {
790 *nid = find_node(start);
791 start += PAGE_SIZE;
792 while (start < end) {
793 int n = find_node(start);
794
795 if (n != *nid)
796 break;
797 start += PAGE_SIZE;
798 }
799
800 if (start > end)
801 start = end;
802
803 return start;
804 }
805 #else
806 u64 memblock_nid_range(u64 start, u64 end, int *nid)
807 {
808 *nid = 0;
809 return end;
810 }
811 #endif
812
813 /* This must be invoked after performing all of the necessary
814 * add_active_range() calls for 'nid'. We need to be able to get
815 * correct data from get_pfn_range_for_nid().
816 */
817 static void __init allocate_node_data(int nid)
818 {
819 unsigned long paddr, num_pages, start_pfn, end_pfn;
820 struct pglist_data *p;
821
822 #ifdef CONFIG_NEED_MULTIPLE_NODES
823 paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid);
824 if (!paddr) {
825 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
826 prom_halt();
827 }
828 NODE_DATA(nid) = __va(paddr);
829 memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
830
831 NODE_DATA(nid)->bdata = &bootmem_node_data[nid];
832 #endif
833
834 p = NODE_DATA(nid);
835
836 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
837 p->node_start_pfn = start_pfn;
838 p->node_spanned_pages = end_pfn - start_pfn;
839
840 if (p->node_spanned_pages) {
841 num_pages = bootmem_bootmap_pages(p->node_spanned_pages);
842
843 paddr = memblock_alloc_try_nid(num_pages << PAGE_SHIFT, PAGE_SIZE, nid);
844 if (!paddr) {
845 prom_printf("Cannot allocate bootmap for nid[%d]\n",
846 nid);
847 prom_halt();
848 }
849 node_masks[nid].bootmem_paddr = paddr;
850 }
851 }
852
853 static void init_node_masks_nonnuma(void)
854 {
855 int i;
856
857 numadbg("Initializing tables for non-numa.\n");
858
859 node_masks[0].mask = node_masks[0].val = 0;
860 num_node_masks = 1;
861
862 for (i = 0; i < NR_CPUS; i++)
863 numa_cpu_lookup_table[i] = 0;
864
865 cpumask_setall(&numa_cpumask_lookup_table[0]);
866 }
867
868 #ifdef CONFIG_NEED_MULTIPLE_NODES
869 struct pglist_data *node_data[MAX_NUMNODES];
870
871 EXPORT_SYMBOL(numa_cpu_lookup_table);
872 EXPORT_SYMBOL(numa_cpumask_lookup_table);
873 EXPORT_SYMBOL(node_data);
874
875 struct mdesc_mlgroup {
876 u64 node;
877 u64 latency;
878 u64 match;
879 u64 mask;
880 };
881 static struct mdesc_mlgroup *mlgroups;
882 static int num_mlgroups;
883
884 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
885 u32 cfg_handle)
886 {
887 u64 arc;
888
889 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
890 u64 target = mdesc_arc_target(md, arc);
891 const u64 *val;
892
893 val = mdesc_get_property(md, target,
894 "cfg-handle", NULL);
895 if (val && *val == cfg_handle)
896 return 0;
897 }
898 return -ENODEV;
899 }
900
901 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
902 u32 cfg_handle)
903 {
904 u64 arc, candidate, best_latency = ~(u64)0;
905
906 candidate = MDESC_NODE_NULL;
907 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
908 u64 target = mdesc_arc_target(md, arc);
909 const char *name = mdesc_node_name(md, target);
910 const u64 *val;
911
912 if (strcmp(name, "pio-latency-group"))
913 continue;
914
915 val = mdesc_get_property(md, target, "latency", NULL);
916 if (!val)
917 continue;
918
919 if (*val < best_latency) {
920 candidate = target;
921 best_latency = *val;
922 }
923 }
924
925 if (candidate == MDESC_NODE_NULL)
926 return -ENODEV;
927
928 return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
929 }
930
931 int of_node_to_nid(struct device_node *dp)
932 {
933 const struct linux_prom64_registers *regs;
934 struct mdesc_handle *md;
935 u32 cfg_handle;
936 int count, nid;
937 u64 grp;
938
939 /* This is the right thing to do on currently supported
940 * SUN4U NUMA platforms as well, as the PCI controller does
941 * not sit behind any particular memory controller.
942 */
943 if (!mlgroups)
944 return -1;
945
946 regs = of_get_property(dp, "reg", NULL);
947 if (!regs)
948 return -1;
949
950 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
951
952 md = mdesc_grab();
953
954 count = 0;
955 nid = -1;
956 mdesc_for_each_node_by_name(md, grp, "group") {
957 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
958 nid = count;
959 break;
960 }
961 count++;
962 }
963
964 mdesc_release(md);
965
966 return nid;
967 }
968
969 static void __init add_node_ranges(void)
970 {
971 struct memblock_region *reg;
972
973 for_each_memblock(memory, reg) {
974 unsigned long size = reg->size;
975 unsigned long start, end;
976
977 start = reg->base;
978 end = start + size;
979 while (start < end) {
980 unsigned long this_end;
981 int nid;
982
983 this_end = memblock_nid_range(start, end, &nid);
984
985 numadbg("Adding active range nid[%d] "
986 "start[%lx] end[%lx]\n",
987 nid, start, this_end);
988
989 add_active_range(nid,
990 start >> PAGE_SHIFT,
991 this_end >> PAGE_SHIFT);
992
993 start = this_end;
994 }
995 }
996 }
997
998 static int __init grab_mlgroups(struct mdesc_handle *md)
999 {
1000 unsigned long paddr;
1001 int count = 0;
1002 u64 node;
1003
1004 mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1005 count++;
1006 if (!count)
1007 return -ENOENT;
1008
1009 paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup),
1010 SMP_CACHE_BYTES);
1011 if (!paddr)
1012 return -ENOMEM;
1013
1014 mlgroups = __va(paddr);
1015 num_mlgroups = count;
1016
1017 count = 0;
1018 mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1019 struct mdesc_mlgroup *m = &mlgroups[count++];
1020 const u64 *val;
1021
1022 m->node = node;
1023
1024 val = mdesc_get_property(md, node, "latency", NULL);
1025 m->latency = *val;
1026 val = mdesc_get_property(md, node, "address-match", NULL);
1027 m->match = *val;
1028 val = mdesc_get_property(md, node, "address-mask", NULL);
1029 m->mask = *val;
1030
1031 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1032 "match[%llx] mask[%llx]\n",
1033 count - 1, m->node, m->latency, m->match, m->mask);
1034 }
1035
1036 return 0;
1037 }
1038
1039 static int __init grab_mblocks(struct mdesc_handle *md)
1040 {
1041 unsigned long paddr;
1042 int count = 0;
1043 u64 node;
1044
1045 mdesc_for_each_node_by_name(md, node, "mblock")
1046 count++;
1047 if (!count)
1048 return -ENOENT;
1049
1050 paddr = memblock_alloc(count * sizeof(struct mdesc_mblock),
1051 SMP_CACHE_BYTES);
1052 if (!paddr)
1053 return -ENOMEM;
1054
1055 mblocks = __va(paddr);
1056 num_mblocks = count;
1057
1058 count = 0;
1059 mdesc_for_each_node_by_name(md, node, "mblock") {
1060 struct mdesc_mblock *m = &mblocks[count++];
1061 const u64 *val;
1062
1063 val = mdesc_get_property(md, node, "base", NULL);
1064 m->base = *val;
1065 val = mdesc_get_property(md, node, "size", NULL);
1066 m->size = *val;
1067 val = mdesc_get_property(md, node,
1068 "address-congruence-offset", NULL);
1069 m->offset = *val;
1070
1071 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1072 count - 1, m->base, m->size, m->offset);
1073 }
1074
1075 return 0;
1076 }
1077
1078 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1079 u64 grp, cpumask_t *mask)
1080 {
1081 u64 arc;
1082
1083 cpumask_clear(mask);
1084
1085 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1086 u64 target = mdesc_arc_target(md, arc);
1087 const char *name = mdesc_node_name(md, target);
1088 const u64 *id;
1089
1090 if (strcmp(name, "cpu"))
1091 continue;
1092 id = mdesc_get_property(md, target, "id", NULL);
1093 if (*id < nr_cpu_ids)
1094 cpumask_set_cpu(*id, mask);
1095 }
1096 }
1097
1098 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1099 {
1100 int i;
1101
1102 for (i = 0; i < num_mlgroups; i++) {
1103 struct mdesc_mlgroup *m = &mlgroups[i];
1104 if (m->node == node)
1105 return m;
1106 }
1107 return NULL;
1108 }
1109
1110 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1111 int index)
1112 {
1113 struct mdesc_mlgroup *candidate = NULL;
1114 u64 arc, best_latency = ~(u64)0;
1115 struct node_mem_mask *n;
1116
1117 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1118 u64 target = mdesc_arc_target(md, arc);
1119 struct mdesc_mlgroup *m = find_mlgroup(target);
1120 if (!m)
1121 continue;
1122 if (m->latency < best_latency) {
1123 candidate = m;
1124 best_latency = m->latency;
1125 }
1126 }
1127 if (!candidate)
1128 return -ENOENT;
1129
1130 if (num_node_masks != index) {
1131 printk(KERN_ERR "Inconsistent NUMA state, "
1132 "index[%d] != num_node_masks[%d]\n",
1133 index, num_node_masks);
1134 return -EINVAL;
1135 }
1136
1137 n = &node_masks[num_node_masks++];
1138
1139 n->mask = candidate->mask;
1140 n->val = candidate->match;
1141
1142 numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n",
1143 index, n->mask, n->val, candidate->latency);
1144
1145 return 0;
1146 }
1147
1148 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1149 int index)
1150 {
1151 cpumask_t mask;
1152 int cpu;
1153
1154 numa_parse_mdesc_group_cpus(md, grp, &mask);
1155
1156 for_each_cpu(cpu, &mask)
1157 numa_cpu_lookup_table[cpu] = index;
1158 cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
1159
1160 if (numa_debug) {
1161 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1162 for_each_cpu(cpu, &mask)
1163 printk("%d ", cpu);
1164 printk("]\n");
1165 }
1166
1167 return numa_attach_mlgroup(md, grp, index);
1168 }
1169
1170 static int __init numa_parse_mdesc(void)
1171 {
1172 struct mdesc_handle *md = mdesc_grab();
1173 int i, err, count;
1174 u64 node;
1175
1176 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1177 if (node == MDESC_NODE_NULL) {
1178 mdesc_release(md);
1179 return -ENOENT;
1180 }
1181
1182 err = grab_mblocks(md);
1183 if (err < 0)
1184 goto out;
1185
1186 err = grab_mlgroups(md);
1187 if (err < 0)
1188 goto out;
1189
1190 count = 0;
1191 mdesc_for_each_node_by_name(md, node, "group") {
1192 err = numa_parse_mdesc_group(md, node, count);
1193 if (err < 0)
1194 break;
1195 count++;
1196 }
1197
1198 add_node_ranges();
1199
1200 for (i = 0; i < num_node_masks; i++) {
1201 allocate_node_data(i);
1202 node_set_online(i);
1203 }
1204
1205 err = 0;
1206 out:
1207 mdesc_release(md);
1208 return err;
1209 }
1210
1211 static int __init numa_parse_jbus(void)
1212 {
1213 unsigned long cpu, index;
1214
1215 /* NUMA node id is encoded in bits 36 and higher, and there is
1216 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1217 */
1218 index = 0;
1219 for_each_present_cpu(cpu) {
1220 numa_cpu_lookup_table[cpu] = index;
1221 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1222 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1223 node_masks[index].val = cpu << 36UL;
1224
1225 index++;
1226 }
1227 num_node_masks = index;
1228
1229 add_node_ranges();
1230
1231 for (index = 0; index < num_node_masks; index++) {
1232 allocate_node_data(index);
1233 node_set_online(index);
1234 }
1235
1236 return 0;
1237 }
1238
1239 static int __init numa_parse_sun4u(void)
1240 {
1241 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1242 unsigned long ver;
1243
1244 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1245 if ((ver >> 32UL) == __JALAPENO_ID ||
1246 (ver >> 32UL) == __SERRANO_ID)
1247 return numa_parse_jbus();
1248 }
1249 return -1;
1250 }
1251
1252 static int __init bootmem_init_numa(void)
1253 {
1254 int err = -1;
1255
1256 numadbg("bootmem_init_numa()\n");
1257
1258 if (numa_enabled) {
1259 if (tlb_type == hypervisor)
1260 err = numa_parse_mdesc();
1261 else
1262 err = numa_parse_sun4u();
1263 }
1264 return err;
1265 }
1266
1267 #else
1268
1269 static int bootmem_init_numa(void)
1270 {
1271 return -1;
1272 }
1273
1274 #endif
1275
1276 static void __init bootmem_init_nonnuma(void)
1277 {
1278 unsigned long top_of_ram = memblock_end_of_DRAM();
1279 unsigned long total_ram = memblock_phys_mem_size();
1280 struct memblock_region *reg;
1281
1282 numadbg("bootmem_init_nonnuma()\n");
1283
1284 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1285 top_of_ram, total_ram);
1286 printk(KERN_INFO "Memory hole size: %ldMB\n",
1287 (top_of_ram - total_ram) >> 20);
1288
1289 init_node_masks_nonnuma();
1290
1291 for_each_memblock(memory, reg) {
1292 unsigned long start_pfn, end_pfn;
1293
1294 if (!reg->size)
1295 continue;
1296
1297 start_pfn = memblock_region_memory_base_pfn(reg);
1298 end_pfn = memblock_region_memory_end_pfn(reg);
1299 add_active_range(0, start_pfn, end_pfn);
1300 }
1301
1302 allocate_node_data(0);
1303
1304 node_set_online(0);
1305 }
1306
1307 static void __init reserve_range_in_node(int nid, unsigned long start,
1308 unsigned long end)
1309 {
1310 numadbg(" reserve_range_in_node(nid[%d],start[%lx],end[%lx]\n",
1311 nid, start, end);
1312 while (start < end) {
1313 unsigned long this_end;
1314 int n;
1315
1316 this_end = memblock_nid_range(start, end, &n);
1317 if (n == nid) {
1318 numadbg(" MATCH reserving range [%lx:%lx]\n",
1319 start, this_end);
1320 reserve_bootmem_node(NODE_DATA(nid), start,
1321 (this_end - start), BOOTMEM_DEFAULT);
1322 } else
1323 numadbg(" NO MATCH, advancing start to %lx\n",
1324 this_end);
1325
1326 start = this_end;
1327 }
1328 }
1329
1330 static void __init trim_reserved_in_node(int nid)
1331 {
1332 struct memblock_region *reg;
1333
1334 numadbg(" trim_reserved_in_node(%d)\n", nid);
1335
1336 for_each_memblock(reserved, reg)
1337 reserve_range_in_node(nid, reg->base, reg->base + reg->size);
1338 }
1339
1340 static void __init bootmem_init_one_node(int nid)
1341 {
1342 struct pglist_data *p;
1343
1344 numadbg("bootmem_init_one_node(%d)\n", nid);
1345
1346 p = NODE_DATA(nid);
1347
1348 if (p->node_spanned_pages) {
1349 unsigned long paddr = node_masks[nid].bootmem_paddr;
1350 unsigned long end_pfn;
1351
1352 end_pfn = p->node_start_pfn + p->node_spanned_pages;
1353
1354 numadbg(" init_bootmem_node(%d, %lx, %lx, %lx)\n",
1355 nid, paddr >> PAGE_SHIFT, p->node_start_pfn, end_pfn);
1356
1357 init_bootmem_node(p, paddr >> PAGE_SHIFT,
1358 p->node_start_pfn, end_pfn);
1359
1360 numadbg(" free_bootmem_with_active_regions(%d, %lx)\n",
1361 nid, end_pfn);
1362 free_bootmem_with_active_regions(nid, end_pfn);
1363
1364 trim_reserved_in_node(nid);
1365
1366 numadbg(" sparse_memory_present_with_active_regions(%d)\n",
1367 nid);
1368 sparse_memory_present_with_active_regions(nid);
1369 }
1370 }
1371
1372 static unsigned long __init bootmem_init(unsigned long phys_base)
1373 {
1374 unsigned long end_pfn;
1375 int nid;
1376
1377 end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
1378 max_pfn = max_low_pfn = end_pfn;
1379 min_low_pfn = (phys_base >> PAGE_SHIFT);
1380
1381 if (bootmem_init_numa() < 0)
1382 bootmem_init_nonnuma();
1383
1384 /* XXX cpu notifier XXX */
1385
1386 for_each_online_node(nid)
1387 bootmem_init_one_node(nid);
1388
1389 sparse_init();
1390
1391 return end_pfn;
1392 }
1393
1394 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1395 static int pall_ents __initdata;
1396
1397 #ifdef CONFIG_DEBUG_PAGEALLOC
1398 static unsigned long __ref kernel_map_range(unsigned long pstart,
1399 unsigned long pend, pgprot_t prot)
1400 {
1401 unsigned long vstart = PAGE_OFFSET + pstart;
1402 unsigned long vend = PAGE_OFFSET + pend;
1403 unsigned long alloc_bytes = 0UL;
1404
1405 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1406 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1407 vstart, vend);
1408 prom_halt();
1409 }
1410
1411 while (vstart < vend) {
1412 unsigned long this_end, paddr = __pa(vstart);
1413 pgd_t *pgd = pgd_offset_k(vstart);
1414 pud_t *pud;
1415 pmd_t *pmd;
1416 pte_t *pte;
1417
1418 pud = pud_offset(pgd, vstart);
1419 if (pud_none(*pud)) {
1420 pmd_t *new;
1421
1422 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1423 alloc_bytes += PAGE_SIZE;
1424 pud_populate(&init_mm, pud, new);
1425 }
1426
1427 pmd = pmd_offset(pud, vstart);
1428 if (!pmd_present(*pmd)) {
1429 pte_t *new;
1430
1431 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1432 alloc_bytes += PAGE_SIZE;
1433 pmd_populate_kernel(&init_mm, pmd, new);
1434 }
1435
1436 pte = pte_offset_kernel(pmd, vstart);
1437 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1438 if (this_end > vend)
1439 this_end = vend;
1440
1441 while (vstart < this_end) {
1442 pte_val(*pte) = (paddr | pgprot_val(prot));
1443
1444 vstart += PAGE_SIZE;
1445 paddr += PAGE_SIZE;
1446 pte++;
1447 }
1448 }
1449
1450 return alloc_bytes;
1451 }
1452
1453 extern unsigned int kvmap_linear_patch[1];
1454 #endif /* CONFIG_DEBUG_PAGEALLOC */
1455
1456 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1457 {
1458 const unsigned long shift_256MB = 28;
1459 const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
1460 const unsigned long size_256MB = (1UL << shift_256MB);
1461
1462 while (start < end) {
1463 long remains;
1464
1465 remains = end - start;
1466 if (remains < size_256MB)
1467 break;
1468
1469 if (start & mask_256MB) {
1470 start = (start + size_256MB) & ~mask_256MB;
1471 continue;
1472 }
1473
1474 while (remains >= size_256MB) {
1475 unsigned long index = start >> shift_256MB;
1476
1477 __set_bit(index, kpte_linear_bitmap);
1478
1479 start += size_256MB;
1480 remains -= size_256MB;
1481 }
1482 }
1483 }
1484
1485 static void __init init_kpte_bitmap(void)
1486 {
1487 unsigned long i;
1488
1489 for (i = 0; i < pall_ents; i++) {
1490 unsigned long phys_start, phys_end;
1491
1492 phys_start = pall[i].phys_addr;
1493 phys_end = phys_start + pall[i].reg_size;
1494
1495 mark_kpte_bitmap(phys_start, phys_end);
1496 }
1497 }
1498
1499 static void __init kernel_physical_mapping_init(void)
1500 {
1501 #ifdef CONFIG_DEBUG_PAGEALLOC
1502 unsigned long i, mem_alloced = 0UL;
1503
1504 for (i = 0; i < pall_ents; i++) {
1505 unsigned long phys_start, phys_end;
1506
1507 phys_start = pall[i].phys_addr;
1508 phys_end = phys_start + pall[i].reg_size;
1509
1510 mem_alloced += kernel_map_range(phys_start, phys_end,
1511 PAGE_KERNEL);
1512 }
1513
1514 printk("Allocated %ld bytes for kernel page tables.\n",
1515 mem_alloced);
1516
1517 kvmap_linear_patch[0] = 0x01000000; /* nop */
1518 flushi(&kvmap_linear_patch[0]);
1519
1520 __flush_tlb_all();
1521 #endif
1522 }
1523
1524 #ifdef CONFIG_DEBUG_PAGEALLOC
1525 void kernel_map_pages(struct page *page, int numpages, int enable)
1526 {
1527 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1528 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1529
1530 kernel_map_range(phys_start, phys_end,
1531 (enable ? PAGE_KERNEL : __pgprot(0)));
1532
1533 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1534 PAGE_OFFSET + phys_end);
1535
1536 /* we should perform an IPI and flush all tlbs,
1537 * but that can deadlock->flush only current cpu.
1538 */
1539 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1540 PAGE_OFFSET + phys_end);
1541 }
1542 #endif
1543
1544 unsigned long __init find_ecache_flush_span(unsigned long size)
1545 {
1546 int i;
1547
1548 for (i = 0; i < pavail_ents; i++) {
1549 if (pavail[i].reg_size >= size)
1550 return pavail[i].phys_addr;
1551 }
1552
1553 return ~0UL;
1554 }
1555
1556 static void __init tsb_phys_patch(void)
1557 {
1558 struct tsb_ldquad_phys_patch_entry *pquad;
1559 struct tsb_phys_patch_entry *p;
1560
1561 pquad = &__tsb_ldquad_phys_patch;
1562 while (pquad < &__tsb_ldquad_phys_patch_end) {
1563 unsigned long addr = pquad->addr;
1564
1565 if (tlb_type == hypervisor)
1566 *(unsigned int *) addr = pquad->sun4v_insn;
1567 else
1568 *(unsigned int *) addr = pquad->sun4u_insn;
1569 wmb();
1570 __asm__ __volatile__("flush %0"
1571 : /* no outputs */
1572 : "r" (addr));
1573
1574 pquad++;
1575 }
1576
1577 p = &__tsb_phys_patch;
1578 while (p < &__tsb_phys_patch_end) {
1579 unsigned long addr = p->addr;
1580
1581 *(unsigned int *) addr = p->insn;
1582 wmb();
1583 __asm__ __volatile__("flush %0"
1584 : /* no outputs */
1585 : "r" (addr));
1586
1587 p++;
1588 }
1589 }
1590
1591 /* Don't mark as init, we give this to the Hypervisor. */
1592 #ifndef CONFIG_DEBUG_PAGEALLOC
1593 #define NUM_KTSB_DESCR 2
1594 #else
1595 #define NUM_KTSB_DESCR 1
1596 #endif
1597 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1598 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1599
1600 static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
1601 {
1602 pa >>= KTSB_PHYS_SHIFT;
1603
1604 while (start < end) {
1605 unsigned int *ia = (unsigned int *)(unsigned long)*start;
1606
1607 ia[0] = (ia[0] & ~0x3fffff) | (pa >> 10);
1608 __asm__ __volatile__("flush %0" : : "r" (ia));
1609
1610 ia[1] = (ia[1] & ~0x3ff) | (pa & 0x3ff);
1611 __asm__ __volatile__("flush %0" : : "r" (ia + 1));
1612
1613 start++;
1614 }
1615 }
1616
1617 static void ktsb_phys_patch(void)
1618 {
1619 extern unsigned int __swapper_tsb_phys_patch;
1620 extern unsigned int __swapper_tsb_phys_patch_end;
1621 unsigned long ktsb_pa;
1622
1623 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1624 patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
1625 &__swapper_tsb_phys_patch_end, ktsb_pa);
1626 #ifndef CONFIG_DEBUG_PAGEALLOC
1627 {
1628 extern unsigned int __swapper_4m_tsb_phys_patch;
1629 extern unsigned int __swapper_4m_tsb_phys_patch_end;
1630 ktsb_pa = (kern_base +
1631 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1632 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
1633 &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
1634 }
1635 #endif
1636 }
1637
1638 static void __init sun4v_ktsb_init(void)
1639 {
1640 unsigned long ktsb_pa;
1641
1642 /* First KTSB for PAGE_SIZE mappings. */
1643 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1644
1645 switch (PAGE_SIZE) {
1646 case 8 * 1024:
1647 default:
1648 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1649 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1650 break;
1651
1652 case 64 * 1024:
1653 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1654 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1655 break;
1656
1657 case 512 * 1024:
1658 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1659 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1660 break;
1661
1662 case 4 * 1024 * 1024:
1663 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1664 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1665 break;
1666 }
1667
1668 ktsb_descr[0].assoc = 1;
1669 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1670 ktsb_descr[0].ctx_idx = 0;
1671 ktsb_descr[0].tsb_base = ktsb_pa;
1672 ktsb_descr[0].resv = 0;
1673
1674 #ifndef CONFIG_DEBUG_PAGEALLOC
1675 /* Second KTSB for 4MB/256MB mappings. */
1676 ktsb_pa = (kern_base +
1677 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1678
1679 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1680 ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1681 HV_PGSZ_MASK_256MB);
1682 ktsb_descr[1].assoc = 1;
1683 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1684 ktsb_descr[1].ctx_idx = 0;
1685 ktsb_descr[1].tsb_base = ktsb_pa;
1686 ktsb_descr[1].resv = 0;
1687 #endif
1688 }
1689
1690 void __cpuinit sun4v_ktsb_register(void)
1691 {
1692 unsigned long pa, ret;
1693
1694 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1695
1696 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1697 if (ret != 0) {
1698 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1699 "errors with %lx\n", pa, ret);
1700 prom_halt();
1701 }
1702 }
1703
1704 /* paging_init() sets up the page tables */
1705
1706 static unsigned long last_valid_pfn;
1707 pgd_t swapper_pg_dir[2048];
1708
1709 static void sun4u_pgprot_init(void);
1710 static void sun4v_pgprot_init(void);
1711
1712 void __init paging_init(void)
1713 {
1714 unsigned long end_pfn, shift, phys_base;
1715 unsigned long real_end, i;
1716
1717 /* These build time checkes make sure that the dcache_dirty_cpu()
1718 * page->flags usage will work.
1719 *
1720 * When a page gets marked as dcache-dirty, we store the
1721 * cpu number starting at bit 32 in the page->flags. Also,
1722 * functions like clear_dcache_dirty_cpu use the cpu mask
1723 * in 13-bit signed-immediate instruction fields.
1724 */
1725
1726 /*
1727 * Page flags must not reach into upper 32 bits that are used
1728 * for the cpu number
1729 */
1730 BUILD_BUG_ON(NR_PAGEFLAGS > 32);
1731
1732 /*
1733 * The bit fields placed in the high range must not reach below
1734 * the 32 bit boundary. Otherwise we cannot place the cpu field
1735 * at the 32 bit boundary.
1736 */
1737 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
1738 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
1739
1740 BUILD_BUG_ON(NR_CPUS > 4096);
1741
1742 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1743 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1744
1745 /* Invalidate both kernel TSBs. */
1746 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1747 #ifndef CONFIG_DEBUG_PAGEALLOC
1748 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1749 #endif
1750
1751 if (tlb_type == hypervisor)
1752 sun4v_pgprot_init();
1753 else
1754 sun4u_pgprot_init();
1755
1756 if (tlb_type == cheetah_plus ||
1757 tlb_type == hypervisor) {
1758 tsb_phys_patch();
1759 ktsb_phys_patch();
1760 }
1761
1762 if (tlb_type == hypervisor) {
1763 sun4v_patch_tlb_handlers();
1764 sun4v_ktsb_init();
1765 }
1766
1767 memblock_init();
1768
1769 /* Find available physical memory...
1770 *
1771 * Read it twice in order to work around a bug in openfirmware.
1772 * The call to grab this table itself can cause openfirmware to
1773 * allocate memory, which in turn can take away some space from
1774 * the list of available memory. Reading it twice makes sure
1775 * we really do get the final value.
1776 */
1777 read_obp_translations();
1778 read_obp_memory("reg", &pall[0], &pall_ents);
1779 read_obp_memory("available", &pavail[0], &pavail_ents);
1780 read_obp_memory("available", &pavail[0], &pavail_ents);
1781
1782 phys_base = 0xffffffffffffffffUL;
1783 for (i = 0; i < pavail_ents; i++) {
1784 phys_base = min(phys_base, pavail[i].phys_addr);
1785 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
1786 }
1787
1788 memblock_reserve(kern_base, kern_size);
1789
1790 find_ramdisk(phys_base);
1791
1792 memblock_enforce_memory_limit(cmdline_memory_size);
1793
1794 memblock_analyze();
1795 memblock_dump_all();
1796
1797 set_bit(0, mmu_context_bmap);
1798
1799 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1800
1801 real_end = (unsigned long)_end;
1802 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << 22);
1803 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
1804 num_kernel_image_mappings);
1805
1806 /* Set kernel pgd to upper alias so physical page computations
1807 * work.
1808 */
1809 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1810
1811 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1812
1813 /* Now can init the kernel/bad page tables. */
1814 pud_set(pud_offset(&swapper_pg_dir[0], 0),
1815 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1816
1817 inherit_prom_mappings();
1818
1819 init_kpte_bitmap();
1820
1821 /* Ok, we can use our TLB miss and window trap handlers safely. */
1822 setup_tba();
1823
1824 __flush_tlb_all();
1825
1826 if (tlb_type == hypervisor)
1827 sun4v_ktsb_register();
1828
1829 prom_build_devicetree();
1830 of_populate_present_mask();
1831 #ifndef CONFIG_SMP
1832 of_fill_in_cpu_data();
1833 #endif
1834
1835 if (tlb_type == hypervisor) {
1836 sun4v_mdesc_init();
1837 mdesc_populate_present_mask(cpu_all_mask);
1838 #ifndef CONFIG_SMP
1839 mdesc_fill_in_cpu_data(cpu_all_mask);
1840 #endif
1841 }
1842
1843 /* Once the OF device tree and MDESC have been setup, we know
1844 * the list of possible cpus. Therefore we can allocate the
1845 * IRQ stacks.
1846 */
1847 for_each_possible_cpu(i) {
1848 /* XXX Use node local allocations... XXX */
1849 softirq_stack[i] = __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
1850 hardirq_stack[i] = __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
1851 }
1852
1853 /* Setup bootmem... */
1854 last_valid_pfn = end_pfn = bootmem_init(phys_base);
1855
1856 #ifndef CONFIG_NEED_MULTIPLE_NODES
1857 max_mapnr = last_valid_pfn;
1858 #endif
1859 kernel_physical_mapping_init();
1860
1861 {
1862 unsigned long max_zone_pfns[MAX_NR_ZONES];
1863
1864 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
1865
1866 max_zone_pfns[ZONE_NORMAL] = end_pfn;
1867
1868 free_area_init_nodes(max_zone_pfns);
1869 }
1870
1871 printk("Booting Linux...\n");
1872 }
1873
1874 int __devinit page_in_phys_avail(unsigned long paddr)
1875 {
1876 int i;
1877
1878 paddr &= PAGE_MASK;
1879
1880 for (i = 0; i < pavail_ents; i++) {
1881 unsigned long start, end;
1882
1883 start = pavail[i].phys_addr;
1884 end = start + pavail[i].reg_size;
1885
1886 if (paddr >= start && paddr < end)
1887 return 1;
1888 }
1889 if (paddr >= kern_base && paddr < (kern_base + kern_size))
1890 return 1;
1891 #ifdef CONFIG_BLK_DEV_INITRD
1892 if (paddr >= __pa(initrd_start) &&
1893 paddr < __pa(PAGE_ALIGN(initrd_end)))
1894 return 1;
1895 #endif
1896
1897 return 0;
1898 }
1899
1900 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
1901 static int pavail_rescan_ents __initdata;
1902
1903 /* Certain OBP calls, such as fetching "available" properties, can
1904 * claim physical memory. So, along with initializing the valid
1905 * address bitmap, what we do here is refetch the physical available
1906 * memory list again, and make sure it provides at least as much
1907 * memory as 'pavail' does.
1908 */
1909 static void __init setup_valid_addr_bitmap_from_pavail(unsigned long *bitmap)
1910 {
1911 int i;
1912
1913 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1914
1915 for (i = 0; i < pavail_ents; i++) {
1916 unsigned long old_start, old_end;
1917
1918 old_start = pavail[i].phys_addr;
1919 old_end = old_start + pavail[i].reg_size;
1920 while (old_start < old_end) {
1921 int n;
1922
1923 for (n = 0; n < pavail_rescan_ents; n++) {
1924 unsigned long new_start, new_end;
1925
1926 new_start = pavail_rescan[n].phys_addr;
1927 new_end = new_start +
1928 pavail_rescan[n].reg_size;
1929
1930 if (new_start <= old_start &&
1931 new_end >= (old_start + PAGE_SIZE)) {
1932 set_bit(old_start >> 22, bitmap);
1933 goto do_next_page;
1934 }
1935 }
1936
1937 prom_printf("mem_init: Lost memory in pavail\n");
1938 prom_printf("mem_init: OLD start[%lx] size[%lx]\n",
1939 pavail[i].phys_addr,
1940 pavail[i].reg_size);
1941 prom_printf("mem_init: NEW start[%lx] size[%lx]\n",
1942 pavail_rescan[i].phys_addr,
1943 pavail_rescan[i].reg_size);
1944 prom_printf("mem_init: Cannot continue, aborting.\n");
1945 prom_halt();
1946
1947 do_next_page:
1948 old_start += PAGE_SIZE;
1949 }
1950 }
1951 }
1952
1953 static void __init patch_tlb_miss_handler_bitmap(void)
1954 {
1955 extern unsigned int valid_addr_bitmap_insn[];
1956 extern unsigned int valid_addr_bitmap_patch[];
1957
1958 valid_addr_bitmap_insn[1] = valid_addr_bitmap_patch[1];
1959 mb();
1960 valid_addr_bitmap_insn[0] = valid_addr_bitmap_patch[0];
1961 flushi(&valid_addr_bitmap_insn[0]);
1962 }
1963
1964 void __init mem_init(void)
1965 {
1966 unsigned long codepages, datapages, initpages;
1967 unsigned long addr, last;
1968
1969 addr = PAGE_OFFSET + kern_base;
1970 last = PAGE_ALIGN(kern_size) + addr;
1971 while (addr < last) {
1972 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1973 addr += PAGE_SIZE;
1974 }
1975
1976 setup_valid_addr_bitmap_from_pavail(sparc64_valid_addr_bitmap);
1977 patch_tlb_miss_handler_bitmap();
1978
1979 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1980
1981 #ifdef CONFIG_NEED_MULTIPLE_NODES
1982 {
1983 int i;
1984 for_each_online_node(i) {
1985 if (NODE_DATA(i)->node_spanned_pages != 0) {
1986 totalram_pages +=
1987 free_all_bootmem_node(NODE_DATA(i));
1988 }
1989 }
1990 }
1991 #else
1992 totalram_pages = free_all_bootmem();
1993 #endif
1994
1995 /* We subtract one to account for the mem_map_zero page
1996 * allocated below.
1997 */
1998 totalram_pages -= 1;
1999 num_physpages = totalram_pages;
2000
2001 /*
2002 * Set up the zero page, mark it reserved, so that page count
2003 * is not manipulated when freeing the page from user ptes.
2004 */
2005 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2006 if (mem_map_zero == NULL) {
2007 prom_printf("paging_init: Cannot alloc zero page.\n");
2008 prom_halt();
2009 }
2010 SetPageReserved(mem_map_zero);
2011
2012 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
2013 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
2014 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
2015 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
2016 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
2017 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
2018
2019 printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
2020 nr_free_pages() << (PAGE_SHIFT-10),
2021 codepages << (PAGE_SHIFT-10),
2022 datapages << (PAGE_SHIFT-10),
2023 initpages << (PAGE_SHIFT-10),
2024 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
2025
2026 if (tlb_type == cheetah || tlb_type == cheetah_plus)
2027 cheetah_ecache_flush_init();
2028 }
2029
2030 void free_initmem(void)
2031 {
2032 unsigned long addr, initend;
2033 int do_free = 1;
2034
2035 /* If the physical memory maps were trimmed by kernel command
2036 * line options, don't even try freeing this initmem stuff up.
2037 * The kernel image could have been in the trimmed out region
2038 * and if so the freeing below will free invalid page structs.
2039 */
2040 if (cmdline_memory_size)
2041 do_free = 0;
2042
2043 /*
2044 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2045 */
2046 addr = PAGE_ALIGN((unsigned long)(__init_begin));
2047 initend = (unsigned long)(__init_end) & PAGE_MASK;
2048 for (; addr < initend; addr += PAGE_SIZE) {
2049 unsigned long page;
2050 struct page *p;
2051
2052 page = (addr +
2053 ((unsigned long) __va(kern_base)) -
2054 ((unsigned long) KERNBASE));
2055 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2056
2057 if (do_free) {
2058 p = virt_to_page(page);
2059
2060 ClearPageReserved(p);
2061 init_page_count(p);
2062 __free_page(p);
2063 num_physpages++;
2064 totalram_pages++;
2065 }
2066 }
2067 }
2068
2069 #ifdef CONFIG_BLK_DEV_INITRD
2070 void free_initrd_mem(unsigned long start, unsigned long end)
2071 {
2072 if (start < end)
2073 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
2074 for (; start < end; start += PAGE_SIZE) {
2075 struct page *p = virt_to_page(start);
2076
2077 ClearPageReserved(p);
2078 init_page_count(p);
2079 __free_page(p);
2080 num_physpages++;
2081 totalram_pages++;
2082 }
2083 }
2084 #endif
2085
2086 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
2087 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
2088 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2089 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2090 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2091 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2092
2093 pgprot_t PAGE_KERNEL __read_mostly;
2094 EXPORT_SYMBOL(PAGE_KERNEL);
2095
2096 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2097 pgprot_t PAGE_COPY __read_mostly;
2098
2099 pgprot_t PAGE_SHARED __read_mostly;
2100 EXPORT_SYMBOL(PAGE_SHARED);
2101
2102 unsigned long pg_iobits __read_mostly;
2103
2104 unsigned long _PAGE_IE __read_mostly;
2105 EXPORT_SYMBOL(_PAGE_IE);
2106
2107 unsigned long _PAGE_E __read_mostly;
2108 EXPORT_SYMBOL(_PAGE_E);
2109
2110 unsigned long _PAGE_CACHE __read_mostly;
2111 EXPORT_SYMBOL(_PAGE_CACHE);
2112
2113 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2114 unsigned long vmemmap_table[VMEMMAP_SIZE];
2115
2116 int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node)
2117 {
2118 unsigned long vstart = (unsigned long) start;
2119 unsigned long vend = (unsigned long) (start + nr);
2120 unsigned long phys_start = (vstart - VMEMMAP_BASE);
2121 unsigned long phys_end = (vend - VMEMMAP_BASE);
2122 unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK;
2123 unsigned long end = VMEMMAP_ALIGN(phys_end);
2124 unsigned long pte_base;
2125
2126 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2127 _PAGE_CP_4U | _PAGE_CV_4U |
2128 _PAGE_P_4U | _PAGE_W_4U);
2129 if (tlb_type == hypervisor)
2130 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2131 _PAGE_CP_4V | _PAGE_CV_4V |
2132 _PAGE_P_4V | _PAGE_W_4V);
2133
2134 for (; addr < end; addr += VMEMMAP_CHUNK) {
2135 unsigned long *vmem_pp =
2136 vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT);
2137 void *block;
2138
2139 if (!(*vmem_pp & _PAGE_VALID)) {
2140 block = vmemmap_alloc_block(1UL << 22, node);
2141 if (!block)
2142 return -ENOMEM;
2143
2144 *vmem_pp = pte_base | __pa(block);
2145
2146 printk(KERN_INFO "[%p-%p] page_structs=%lu "
2147 "node=%d entry=%lu/%lu\n", start, block, nr,
2148 node,
2149 addr >> VMEMMAP_CHUNK_SHIFT,
2150 VMEMMAP_SIZE);
2151 }
2152 }
2153 return 0;
2154 }
2155 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2156
2157 static void prot_init_common(unsigned long page_none,
2158 unsigned long page_shared,
2159 unsigned long page_copy,
2160 unsigned long page_readonly,
2161 unsigned long page_exec_bit)
2162 {
2163 PAGE_COPY = __pgprot(page_copy);
2164 PAGE_SHARED = __pgprot(page_shared);
2165
2166 protection_map[0x0] = __pgprot(page_none);
2167 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2168 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2169 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2170 protection_map[0x4] = __pgprot(page_readonly);
2171 protection_map[0x5] = __pgprot(page_readonly);
2172 protection_map[0x6] = __pgprot(page_copy);
2173 protection_map[0x7] = __pgprot(page_copy);
2174 protection_map[0x8] = __pgprot(page_none);
2175 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2176 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2177 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2178 protection_map[0xc] = __pgprot(page_readonly);
2179 protection_map[0xd] = __pgprot(page_readonly);
2180 protection_map[0xe] = __pgprot(page_shared);
2181 protection_map[0xf] = __pgprot(page_shared);
2182 }
2183
2184 static void __init sun4u_pgprot_init(void)
2185 {
2186 unsigned long page_none, page_shared, page_copy, page_readonly;
2187 unsigned long page_exec_bit;
2188
2189 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2190 _PAGE_CACHE_4U | _PAGE_P_4U |
2191 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2192 _PAGE_EXEC_4U);
2193 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2194 _PAGE_CACHE_4U | _PAGE_P_4U |
2195 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2196 _PAGE_EXEC_4U | _PAGE_L_4U);
2197
2198 _PAGE_IE = _PAGE_IE_4U;
2199 _PAGE_E = _PAGE_E_4U;
2200 _PAGE_CACHE = _PAGE_CACHE_4U;
2201
2202 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2203 __ACCESS_BITS_4U | _PAGE_E_4U);
2204
2205 #ifdef CONFIG_DEBUG_PAGEALLOC
2206 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^
2207 0xfffff80000000000UL;
2208 #else
2209 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2210 0xfffff80000000000UL;
2211 #endif
2212 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2213 _PAGE_P_4U | _PAGE_W_4U);
2214
2215 /* XXX Should use 256MB on Panther. XXX */
2216 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
2217
2218 _PAGE_SZBITS = _PAGE_SZBITS_4U;
2219 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2220 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2221 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2222
2223
2224 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2225 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2226 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2227 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2228 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2229 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2230 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2231
2232 page_exec_bit = _PAGE_EXEC_4U;
2233
2234 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2235 page_exec_bit);
2236 }
2237
2238 static void __init sun4v_pgprot_init(void)
2239 {
2240 unsigned long page_none, page_shared, page_copy, page_readonly;
2241 unsigned long page_exec_bit;
2242
2243 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2244 _PAGE_CACHE_4V | _PAGE_P_4V |
2245 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2246 _PAGE_EXEC_4V);
2247 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2248
2249 _PAGE_IE = _PAGE_IE_4V;
2250 _PAGE_E = _PAGE_E_4V;
2251 _PAGE_CACHE = _PAGE_CACHE_4V;
2252
2253 #ifdef CONFIG_DEBUG_PAGEALLOC
2254 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
2255 0xfffff80000000000UL;
2256 #else
2257 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2258 0xfffff80000000000UL;
2259 #endif
2260 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2261 _PAGE_P_4V | _PAGE_W_4V);
2262
2263 #ifdef CONFIG_DEBUG_PAGEALLOC
2264 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
2265 0xfffff80000000000UL;
2266 #else
2267 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
2268 0xfffff80000000000UL;
2269 #endif
2270 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2271 _PAGE_P_4V | _PAGE_W_4V);
2272
2273 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2274 __ACCESS_BITS_4V | _PAGE_E_4V);
2275
2276 _PAGE_SZBITS = _PAGE_SZBITS_4V;
2277 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2278 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2279 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2280 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2281
2282 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
2283 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2284 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2285 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2286 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2287 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2288 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2289
2290 page_exec_bit = _PAGE_EXEC_4V;
2291
2292 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2293 page_exec_bit);
2294 }
2295
2296 unsigned long pte_sz_bits(unsigned long sz)
2297 {
2298 if (tlb_type == hypervisor) {
2299 switch (sz) {
2300 case 8 * 1024:
2301 default:
2302 return _PAGE_SZ8K_4V;
2303 case 64 * 1024:
2304 return _PAGE_SZ64K_4V;
2305 case 512 * 1024:
2306 return _PAGE_SZ512K_4V;
2307 case 4 * 1024 * 1024:
2308 return _PAGE_SZ4MB_4V;
2309 }
2310 } else {
2311 switch (sz) {
2312 case 8 * 1024:
2313 default:
2314 return _PAGE_SZ8K_4U;
2315 case 64 * 1024:
2316 return _PAGE_SZ64K_4U;
2317 case 512 * 1024:
2318 return _PAGE_SZ512K_4U;
2319 case 4 * 1024 * 1024:
2320 return _PAGE_SZ4MB_4U;
2321 }
2322 }
2323 }
2324
2325 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2326 {
2327 pte_t pte;
2328
2329 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
2330 pte_val(pte) |= (((unsigned long)space) << 32);
2331 pte_val(pte) |= pte_sz_bits(page_size);
2332
2333 return pte;
2334 }
2335
2336 static unsigned long kern_large_tte(unsigned long paddr)
2337 {
2338 unsigned long val;
2339
2340 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2341 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2342 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2343 if (tlb_type == hypervisor)
2344 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2345 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
2346 _PAGE_EXEC_4V | _PAGE_W_4V);
2347
2348 return val | paddr;
2349 }
2350
2351 /* If not locked, zap it. */
2352 void __flush_tlb_all(void)
2353 {
2354 unsigned long pstate;
2355 int i;
2356
2357 __asm__ __volatile__("flushw\n\t"
2358 "rdpr %%pstate, %0\n\t"
2359 "wrpr %0, %1, %%pstate"
2360 : "=r" (pstate)
2361 : "i" (PSTATE_IE));
2362 if (tlb_type == hypervisor) {
2363 sun4v_mmu_demap_all();
2364 } else if (tlb_type == spitfire) {
2365 for (i = 0; i < 64; i++) {
2366 /* Spitfire Errata #32 workaround */
2367 /* NOTE: Always runs on spitfire, so no
2368 * cheetah+ page size encodings.
2369 */
2370 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2371 "flush %%g6"
2372 : /* No outputs */
2373 : "r" (0),
2374 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2375
2376 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2377 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2378 "membar #Sync"
2379 : /* no outputs */
2380 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2381 spitfire_put_dtlb_data(i, 0x0UL);
2382 }
2383
2384 /* Spitfire Errata #32 workaround */
2385 /* NOTE: Always runs on spitfire, so no
2386 * cheetah+ page size encodings.
2387 */
2388 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2389 "flush %%g6"
2390 : /* No outputs */
2391 : "r" (0),
2392 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2393
2394 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2395 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2396 "membar #Sync"
2397 : /* no outputs */
2398 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2399 spitfire_put_itlb_data(i, 0x0UL);
2400 }
2401 }
2402 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2403 cheetah_flush_dtlb_all();
2404 cheetah_flush_itlb_all();
2405 }
2406 __asm__ __volatile__("wrpr %0, 0, %%pstate"
2407 : : "r" (pstate));
2408 }