Staging: hv: mousevsc: Change the allocation flags to reflect interrupt context
[zen-stable.git] / arch / xtensa / include / asm / tlb.h
blob0d766f9c1083a59cd4a073cb5da0dfc640a06415
1 /*
2 * include/asm-xtensa/tlb.h
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
11 #ifndef _XTENSA_TLB_H
12 #define _XTENSA_TLB_H
14 #include <asm/cache.h>
15 #include <asm/page.h>
17 #if (DCACHE_WAY_SIZE <= PAGE_SIZE)
19 /* Note, read http://lkml.org/lkml/2004/1/15/6 */
21 # define tlb_start_vma(tlb,vma) do { } while (0)
22 # define tlb_end_vma(tlb,vma) do { } while (0)
24 #else
26 # define tlb_start_vma(tlb, vma) \
27 do { \
28 if (!tlb->fullmm) \
29 flush_cache_range(vma, vma->vm_start, vma->vm_end); \
30 } while(0)
32 # define tlb_end_vma(tlb, vma) \
33 do { \
34 if (!tlb->fullmm) \
35 flush_tlb_range(vma, vma->vm_start, vma->vm_end); \
36 } while(0)
38 #endif
40 #define __tlb_remove_tlb_entry(tlb,pte,addr) do { } while (0)
41 #define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
43 #include <asm-generic/tlb.h>
45 #define __pte_free_tlb(tlb, pte, address) pte_free((tlb)->mm, pte)
47 #endif /* _XTENSA_TLB_H */