drivers/staging/et131x/et1310_phy.h

   1 /*
   2  * Agere Systems Inc.
   3  * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
   4  *
   5  * Copyright © 2005 Agere Systems Inc.
   6  * All rights reserved.
   7  *   http://www.agere.com
   8  *
   9  * Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
  10  *
  11  *------------------------------------------------------------------------------
  12  *
  13  * et1310_phy.h - Defines, structs, enums, prototypes, etc. pertaining to the
  14  *                PHY.
  15  *
  16  *------------------------------------------------------------------------------
  17  *
  18  * SOFTWARE LICENSE
  19  *
  20  * This software is provided subject to the following terms and conditions,
  21  * which you should read carefully before using the software.  Using this
  22  * software indicates your acceptance of these terms and conditions.  If you do
  23  * not agree with these terms and conditions, do not use the software.
  24  *
  25  * Copyright © 2005 Agere Systems Inc.
  26  * All rights reserved.
  27  *
  28  * Redistribution and use in source or binary forms, with or without
  29  * modifications, are permitted provided that the following conditions are met:
  30  *
  31  * . Redistributions of source code must retain the above copyright notice, this
  32  *    list of conditions and the following Disclaimer as comments in the code as
  33  *    well as in the documentation and/or other materials provided with the
  34  *    distribution.
  35  *
  36  * . Redistributions in binary form must reproduce the above copyright notice,
  37  *    this list of conditions and the following Disclaimer in the documentation
  38  *    and/or other materials provided with the distribution.
  39  *
  40  * . Neither the name of Agere Systems Inc. nor the names of the contributors
  41  *    may be used to endorse or promote products derived from this software
  42  *    without specific prior written permission.
  43  *
  44  * Disclaimer
  45  *
  46  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
  47  * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
  48  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
  49  * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
  50  * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
  51  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  52  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  53  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  54  * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
  55  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  56  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  57  * DAMAGE.
  58  *
  59  */
  60
  61 #ifndef _ET1310_PHY_H_
  62 #define _ET1310_PHY_H_
  63
  64 /*
  65  * Defines for generic MII registers 0x00 -> 0x0F can be found in
  66  * include/linux/mii.h
  67  */
  68
  69 /* some defines for modem registers that seem to be 'reserved' */
  70 #define PHY_INDEX_REG              0x10
  71 #define PHY_DATA_REG               0x11
  72 #define PHY_MPHY_CONTROL_REG       0x12
  73
  74 /* defines for specified registers */
  75 #define PHY_LOOPBACK_CONTROL       0x13 /* TRU_VMI_LOOPBACK_CONTROL_1_REG 19 */
  76                                         /* TRU_VMI_LOOPBACK_CONTROL_2_REG 20 */
  77 #define PHY_REGISTER_MGMT_CONTROL  0x15 /* TRU_VMI_MI_SEQ_CONTROL_REG     21 */
  78 #define PHY_CONFIG                 0x16 /* TRU_VMI_CONFIGURATION_REG      22 */
  79 #define PHY_PHY_CONTROL            0x17 /* TRU_VMI_PHY_CONTROL_REG        23 */
  80 #define PHY_INTERRUPT_MASK         0x18 /* TRU_VMI_INTERRUPT_MASK_REG     24 */
  81 #define PHY_INTERRUPT_STATUS       0x19 /* TRU_VMI_INTERRUPT_STATUS_REG   25 */
  82 #define PHY_PHY_STATUS             0x1A /* TRU_VMI_PHY_STATUS_REG         26 */
  83 #define PHY_LED_1                  0x1B /* TRU_VMI_LED_CONTROL_1_REG      27 */
  84 #define PHY_LED_2                  0x1C /* TRU_VMI_LED_CONTROL_2_REG      28 */
  85                                         /* TRU_VMI_LINK_CONTROL_REG       29 */
  86                                         /* TRU_VMI_TIMING_CONTROL_REG        */
  87
  88 /* MI Register 10: Gigabit basic mode status reg(Reg 0x0A) */
  89 #define ET_1000BT_MSTR_SLV 0x4000
  90
  91 /* MI Register 16 - 18: Reserved Reg(0x10-0x12) */
  92
  93 /* MI Register 19: Loopback Control Reg(0x13)
  94  *      15:     mii_en
  95  *      14:     pcs_en
  96  *      13:     pmd_en
  97  *      12:     all_digital_en
  98  *      11:     replica_en
  99  *      10:     line_driver_en
 100  *      9-0:    reserved
 101  */
 102
 103 /* MI Register 20: Reserved Reg(0x14) */
 104
 105 /* MI Register 21: Management Interface Control Reg(0x15)
 106  *      15-11:  reserved
 107  *      10-4:   mi_error_count
 108  *      3:      reserved
 109  *      2:      ignore_10g_fr
 110  *      1:      reserved
 111  *      0:      preamble_supress_en
 112  */
 113
 114 /* MI Register 22: PHY Configuration Reg(0x16)
 115  *      15:     crs_tx_en
 116  *      14:     reserved
 117  *      13-12:  tx_fifo_depth
 118  *      11-10:  speed_downshift
 119  *      9:      pbi_detect
 120  *      8:      tbi_rate
 121  *      7:      alternate_np
 122  *      6:      group_mdio_en
 123  *      5:      tx_clock_en
 124  *      4:      sys_clock_en
 125  *      3:      reserved
 126  *      2-0:    mac_if_mode
 127  */
 128
 129 #define ET_PHY_CONFIG_TX_FIFO_DEPTH     0x3000
 130
 131 #define ET_PHY_CONFIG_FIFO_DEPTH_8      0x0000
 132 #define ET_PHY_CONFIG_FIFO_DEPTH_16     0x1000
 133 #define ET_PHY_CONFIG_FIFO_DEPTH_32     0x2000
 134 #define ET_PHY_CONFIG_FIFO_DEPTH_64     0x3000
 135
 136 /* MI Register 23: PHY CONTROL Reg(0x17)
 137  *      15:     reserved
 138  *      14:     tdr_en
 139  *      13:     reserved
 140  *      12-11:  downshift_attempts
 141  *      10-6:   reserved
 142  *      5:      jabber_10baseT
 143  *      4:      sqe_10baseT
 144  *      3:      tp_loopback_10baseT
 145  *      2:      preamble_gen_en
 146  *      1:      reserved
 147  *      0:      force_int
 148  */
 149
 150 /* MI Register 24: Interrupt Mask Reg(0x18)
 151  *      15-10:  reserved
 152  *      9:      mdio_sync_lost
 153  *      8:      autoneg_status
 154  *      7:      hi_bit_err
 155  *      6:      np_rx
 156  *      5:      err_counter_full
 157  *      4:      fifo_over_underflow
 158  *      3:      rx_status
 159  *      2:      link_status
 160  *      1:      automatic_speed
 161  *      0:      int_en
 162  */
 163
 164 #define ET_PHY_INT_MASK_AUTONEGSTAT     0x0100
 165 #define ET_PHY_INT_MASK_LINKSTAT        0x0004
 166 #define ET_PHY_INT_MASK_ENABLE          0x0001
 167
 168 /* MI Register 25: Interrupt Status Reg(0x19)
 169  *      15-10:  reserved
 170  *      9:      mdio_sync_lost
 171  *      8:      autoneg_status
 172  *      7:      hi_bit_err
 173  *      6:      np_rx
 174  *      5:      err_counter_full
 175  *      4:      fifo_over_underflow
 176  *      3:      rx_status
 177  *      2:      link_status
 178  *      1:      automatic_speed
 179  *      0:      int_en
 180  */
 181
 182 /* MI Register 26: PHY Status Reg(0x1A)
 183  *      15:     reserved
 184  *      14-13:  autoneg_fault
 185  *      12:     autoneg_status
 186  *      11:     mdi_x_status
 187  *      10:     polarity_status
 188  *      9-8:    speed_status
 189  *      7:      duplex_status
 190  *      6:      link_status
 191  *      5:      tx_status
 192  *      4:      rx_status
 193  *      3:      collision_status
 194  *      2:      autoneg_en
 195  *      1:      pause_en
 196  *      0:      asymmetric_dir
 197  */
 198 #define ET_PHY_AUTONEG_STATUS   0x1000
 199 #define ET_PHY_POLARITY_STATUS  0x0400
 200 #define ET_PHY_SPEED_STATUS     0x0300
 201 #define ET_PHY_DUPLEX_STATUS    0x0080
 202 #define ET_PHY_LSTATUS          0x0040
 203 #define ET_PHY_AUTONEG_ENABLE   0x0020
 204
 205 /* MI Register 27: LED Control Reg 1(0x1B)
 206  *      15-14:  reserved
 207  *      13-12:  led_dup_indicate
 208  *      11-10:  led_10baseT
 209  *      9-8:    led_collision
 210  *      7-4:    reserved
 211  *      3-2:    pulse_dur
 212  *      1:      pulse_stretch1
 213  *      0:      pulse_stretch0
 214  */
 215
 216 /* MI Register 28: LED Control Reg 2(0x1C)
 217  *      15-12:  led_link
 218  *      11-8:   led_tx_rx
 219  *      7-4:    led_100BaseTX
 220  *      3-0:    led_1000BaseT
 221  */
 222 #define ET_LED2_LED_LINK        0xF000
 223 #define ET_LED2_LED_TXRX        0x0F00
 224 #define ET_LED2_LED_100TX       0x00F0
 225 #define ET_LED2_LED_1000T       0x000F
 226
 227 /* defines for LED control reg 2 values */
 228 #define LED_VAL_1000BT                  0x0
 229 #define LED_VAL_100BTX                  0x1
 230 #define LED_VAL_10BT                    0x2
 231 #define LED_VAL_1000BT_100BTX           0x3 /* 1000BT on, 100BTX blink */
 232 #define LED_VAL_LINKON                  0x4
 233 #define LED_VAL_TX                      0x5
 234 #define LED_VAL_RX                      0x6
 235 #define LED_VAL_TXRX                    0x7 /* TX or RX */
 236 #define LED_VAL_DUPLEXFULL              0x8
 237 #define LED_VAL_COLLISION               0x9
 238 #define LED_VAL_LINKON_ACTIVE           0xA /* Link on, activity blink */
 239 #define LED_VAL_LINKON_RECV             0xB /* Link on, receive blink */
 240 #define LED_VAL_DUPLEXFULL_COLLISION    0xC /* Duplex on, collision blink */
 241 #define LED_VAL_BLINK                   0xD
 242 #define LED_VAL_ON                      0xE
 243 #define LED_VAL_OFF                     0xF
 244
 245 #define LED_LINK_SHIFT                  12
 246 #define LED_TXRX_SHIFT                  8
 247 #define LED_100TX_SHIFT                 4
 248
 249 /* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */
 250
 251 /* Defines for PHY access routines */
 252
 253 /* Define bit operation flags */
 254 #define TRUEPHY_BIT_CLEAR               0
 255 #define TRUEPHY_BIT_SET                 1
 256 #define TRUEPHY_BIT_READ                2
 257
 258 /* Define read/write operation flags */
 259 #ifndef TRUEPHY_READ
 260 #define TRUEPHY_READ                    0
 261 #define TRUEPHY_WRITE                   1
 262 #define TRUEPHY_MASK                    2
 263 #endif
 264
 265 /* Define master/slave configuration values */
 266 #define TRUEPHY_CFG_SLAVE               0
 267 #define TRUEPHY_CFG_MASTER              1
 268
 269 /* Define MDI/MDI-X settings */
 270 #define TRUEPHY_MDI                     0
 271 #define TRUEPHY_MDIX                    1
 272 #define TRUEPHY_AUTO_MDI_MDIX           2
 273
 274 /* Define 10Base-T link polarities */
 275 #define TRUEPHY_POLARITY_NORMAL         0
 276 #define TRUEPHY_POLARITY_INVERTED       1
 277
 278 /* Define auto-negotiation results */
 279 #define TRUEPHY_ANEG_NOT_COMPLETE       0
 280 #define TRUEPHY_ANEG_COMPLETE           1
 281 #define TRUEPHY_ANEG_DISABLED           2
 282
 283 /* Define duplex advertisement flags */
 284 #define TRUEPHY_ADV_DUPLEX_NONE         0x00
 285 #define TRUEPHY_ADV_DUPLEX_FULL         0x01
 286 #define TRUEPHY_ADV_DUPLEX_HALF         0x02
 287 #define TRUEPHY_ADV_DUPLEX_BOTH     \
 288         (TRUEPHY_ADV_DUPLEX_FULL | TRUEPHY_ADV_DUPLEX_HALF)
 289
 290 #endif /* _ET1310_PHY_H_ */