drivers/infiniband/hw/cxgb4/iw_cxgb4.h

   1 /*
   2  * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *      - Redistributions in binary form must reproduce the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer in the documentation and/or other materials
  20  *        provided with the distribution.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  23  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  24  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  25  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  26  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  27  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  28  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  29  * SOFTWARE.
  30  */
  31 #ifndef __IW_CXGB4_H__
  32 #define __IW_CXGB4_H__
  33
  34 #include <linux/mutex.h>
  35 #include <linux/list.h>
  36 #include <linux/spinlock.h>
  37 #include <linux/idr.h>
  38 #include <linux/workqueue.h>
  39 #include <linux/netdevice.h>
  40 #include <linux/sched.h>
  41 #include <linux/pci.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/inet.h>
  44 #include <linux/wait.h>
  45 #include <linux/kref.h>
  46 #include <linux/timer.h>
  47 #include <linux/io.h>
  48 #include <linux/kfifo.h>
  49 #include <linux/mutex.h>
  50
  51 #include <asm/byteorder.h>
  52
  53 #include <net/net_namespace.h>
  54
  55 #include <rdma/ib_verbs.h>
  56 #include <rdma/iw_cm.h>
  57
  58 #include "cxgb4.h"
  59 #include "cxgb4_uld.h"
  60 #include "l2t.h"
  61 #include "user.h"
  62
  63 #define DRV_NAME "iw_cxgb4"
  64 #define MOD DRV_NAME ":"
  65
  66 extern int c4iw_debug;
  67 #define PDBG(fmt, args...) \
  68 do { \
  69         if (c4iw_debug) \
  70                 printk(MOD fmt, ## args); \
  71 } while (0)
  72
  73 #include "t4.h"
  74
  75 #define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->pbl.start)
  76 #define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->rq.start)
  77
  78 static inline void *cplhdr(struct sk_buff *skb)
  79 {
  80         return skb->data;
  81 }
  82
  83 struct c4iw_resource {
  84         struct kfifo tpt_fifo;
  85         spinlock_t tpt_fifo_lock;
  86         struct kfifo qid_fifo;
  87         spinlock_t qid_fifo_lock;
  88         struct kfifo pdid_fifo;
  89         spinlock_t pdid_fifo_lock;
  90 };
  91
  92 struct c4iw_qid_list {
  93         struct list_head entry;
  94         u32 qid;
  95 };
  96
  97 struct c4iw_dev_ucontext {
  98         struct list_head qpids;
  99         struct list_head cqids;
 100         struct mutex lock;
 101 };
 102
 103 enum c4iw_rdev_flags {
 104         T4_FATAL_ERROR = (1<<0),
 105 };
 106
 107 struct c4iw_rdev {
 108         struct c4iw_resource resource;
 109         unsigned long qpshift;
 110         u32 qpmask;
 111         unsigned long cqshift;
 112         u32 cqmask;
 113         struct c4iw_dev_ucontext uctx;
 114         struct gen_pool *pbl_pool;
 115         struct gen_pool *rqt_pool;
 116         struct gen_pool *ocqp_pool;
 117         u32 flags;
 118         struct cxgb4_lld_info lldi;
 119         unsigned long oc_mw_pa;
 120         void __iomem *oc_mw_kva;
 121 };
 122
 123 static inline int c4iw_fatal_error(struct c4iw_rdev *rdev)
 124 {
 125         return rdev->flags & T4_FATAL_ERROR;
 126 }
 127
 128 static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
 129 {
 130         return min((int)T4_MAX_NUM_STAG, (int)(rdev->lldi.vr->stag.size >> 5));
 131 }
 132
 133 #define C4IW_WR_TO (10*HZ)
 134
 135 struct c4iw_wr_wait {
 136         wait_queue_head_t wait;
 137         int done;
 138         int ret;
 139 };
 140
 141 static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
 142 {
 143         wr_waitp->ret = 0;
 144         wr_waitp->done = 0;
 145         init_waitqueue_head(&wr_waitp->wait);
 146 }
 147
 148 static inline int c4iw_wait_for_reply(struct c4iw_rdev *rdev,
 149                                  struct c4iw_wr_wait *wr_waitp,
 150                                  u32 hwtid, u32 qpid,
 151                                  const char *func)
 152 {
 153         unsigned to = C4IW_WR_TO;
 154         do {
 155
 156                 wait_event_timeout(wr_waitp->wait, wr_waitp->done, to);
 157                 if (!wr_waitp->done) {
 158                         printk(KERN_ERR MOD "%s - Device %s not responding - "
 159                                "tid %u qpid %u\n", func,
 160                                pci_name(rdev->lldi.pdev), hwtid, qpid);
 161                         to = to << 2;
 162                 }
 163         } while (!wr_waitp->done);
 164         if (wr_waitp->ret)
 165                 printk(KERN_WARNING MOD "%s: FW reply %d tid %u qpid %u\n",
 166                        pci_name(rdev->lldi.pdev), wr_waitp->ret, hwtid, qpid);
 167         return wr_waitp->ret;
 168 }
 169
 170
 171 struct c4iw_dev {
 172         struct ib_device ibdev;
 173         struct c4iw_rdev rdev;
 174         u32 device_cap_flags;
 175         struct idr cqidr;
 176         struct idr qpidr;
 177         struct idr mmidr;
 178         spinlock_t lock;
 179         struct list_head entry;
 180         struct delayed_work db_drop_task;
 181         struct dentry *debugfs_root;
 182         u8 registered;
 183 };
 184
 185 static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
 186 {
 187         return container_of(ibdev, struct c4iw_dev, ibdev);
 188 }
 189
 190 static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev)
 191 {
 192         return container_of(rdev, struct c4iw_dev, rdev);
 193 }
 194
 195 static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid)
 196 {
 197         return idr_find(&rhp->cqidr, cqid);
 198 }
 199
 200 static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid)
 201 {
 202         return idr_find(&rhp->qpidr, qpid);
 203 }
 204
 205 static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid)
 206 {
 207         return idr_find(&rhp->mmidr, mmid);
 208 }
 209
 210 static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr,
 211                                 void *handle, u32 id)
 212 {
 213         int ret;
 214         int newid;
 215
 216         do {
 217                 if (!idr_pre_get(idr, GFP_KERNEL))
 218                         return -ENOMEM;
 219                 spin_lock_irq(&rhp->lock);
 220                 ret = idr_get_new_above(idr, handle, id, &newid);
 221                 BUG_ON(newid != id);
 222                 spin_unlock_irq(&rhp->lock);
 223         } while (ret == -EAGAIN);
 224
 225         return ret;
 226 }
 227
 228 static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id)
 229 {
 230         spin_lock_irq(&rhp->lock);
 231         idr_remove(idr, id);
 232         spin_unlock_irq(&rhp->lock);
 233 }
 234
 235 struct c4iw_pd {
 236         struct ib_pd ibpd;
 237         u32 pdid;
 238         struct c4iw_dev *rhp;
 239 };
 240
 241 static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd)
 242 {
 243         return container_of(ibpd, struct c4iw_pd, ibpd);
 244 }
 245
 246 struct tpt_attributes {
 247         u64 len;
 248         u64 va_fbo;
 249         enum fw_ri_mem_perms perms;
 250         u32 stag;
 251         u32 pdid;
 252         u32 qpid;
 253         u32 pbl_addr;
 254         u32 pbl_size;
 255         u32 state:1;
 256         u32 type:2;
 257         u32 rsvd:1;
 258         u32 remote_invaliate_disable:1;
 259         u32 zbva:1;
 260         u32 mw_bind_enable:1;
 261         u32 page_size:5;
 262 };
 263
 264 struct c4iw_mr {
 265         struct ib_mr ibmr;
 266         struct ib_umem *umem;
 267         struct c4iw_dev *rhp;
 268         u64 kva;
 269         struct tpt_attributes attr;
 270 };
 271
 272 static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
 273 {
 274         return container_of(ibmr, struct c4iw_mr, ibmr);
 275 }
 276
 277 struct c4iw_mw {
 278         struct ib_mw ibmw;
 279         struct c4iw_dev *rhp;
 280         u64 kva;
 281         struct tpt_attributes attr;
 282 };
 283
 284 static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
 285 {
 286         return container_of(ibmw, struct c4iw_mw, ibmw);
 287 }
 288
 289 struct c4iw_fr_page_list {
 290         struct ib_fast_reg_page_list ibpl;
 291         DEFINE_DMA_UNMAP_ADDR(mapping);
 292         dma_addr_t dma_addr;
 293         struct c4iw_dev *dev;
 294         int size;
 295 };
 296
 297 static inline struct c4iw_fr_page_list *to_c4iw_fr_page_list(
 298                                         struct ib_fast_reg_page_list *ibpl)
 299 {
 300         return container_of(ibpl, struct c4iw_fr_page_list, ibpl);
 301 }
 302
 303 struct c4iw_cq {
 304         struct ib_cq ibcq;
 305         struct c4iw_dev *rhp;
 306         struct t4_cq cq;
 307         spinlock_t lock;
 308         atomic_t refcnt;
 309         wait_queue_head_t wait;
 310 };
 311
 312 static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
 313 {
 314         return container_of(ibcq, struct c4iw_cq, ibcq);
 315 }
 316
 317 struct c4iw_mpa_attributes {
 318         u8 initiator;
 319         u8 recv_marker_enabled;
 320         u8 xmit_marker_enabled;
 321         u8 crc_enabled;
 322         u8 version;
 323         u8 p2p_type;
 324 };
 325
 326 struct c4iw_qp_attributes {
 327         u32 scq;
 328         u32 rcq;
 329         u32 sq_num_entries;
 330         u32 rq_num_entries;
 331         u32 sq_max_sges;
 332         u32 sq_max_sges_rdma_write;
 333         u32 rq_max_sges;
 334         u32 state;
 335         u8 enable_rdma_read;
 336         u8 enable_rdma_write;
 337         u8 enable_bind;
 338         u8 enable_mmid0_fastreg;
 339         u32 max_ord;
 340         u32 max_ird;
 341         u32 pd;
 342         u32 next_state;
 343         char terminate_buffer[52];
 344         u32 terminate_msg_len;
 345         u8 is_terminate_local;
 346         struct c4iw_mpa_attributes mpa_attr;
 347         struct c4iw_ep *llp_stream_handle;
 348 };
 349
 350 struct c4iw_qp {
 351         struct ib_qp ibqp;
 352         struct c4iw_dev *rhp;
 353         struct c4iw_ep *ep;
 354         struct c4iw_qp_attributes attr;
 355         struct t4_wq wq;
 356         spinlock_t lock;
 357         struct mutex mutex;
 358         atomic_t refcnt;
 359         wait_queue_head_t wait;
 360         struct timer_list timer;
 361 };
 362
 363 static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
 364 {
 365         return container_of(ibqp, struct c4iw_qp, ibqp);
 366 }
 367
 368 struct c4iw_ucontext {
 369         struct ib_ucontext ibucontext;
 370         struct c4iw_dev_ucontext uctx;
 371         u32 key;
 372         spinlock_t mmap_lock;
 373         struct list_head mmaps;
 374 };
 375
 376 static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c)
 377 {
 378         return container_of(c, struct c4iw_ucontext, ibucontext);
 379 }
 380
 381 struct c4iw_mm_entry {
 382         struct list_head entry;
 383         u64 addr;
 384         u32 key;
 385         unsigned len;
 386 };
 387
 388 static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
 389                                                 u32 key, unsigned len)
 390 {
 391         struct list_head *pos, *nxt;
 392         struct c4iw_mm_entry *mm;
 393
 394         spin_lock(&ucontext->mmap_lock);
 395         list_for_each_safe(pos, nxt, &ucontext->mmaps) {
 396
 397                 mm = list_entry(pos, struct c4iw_mm_entry, entry);
 398                 if (mm->key == key && mm->len == len) {
 399                         list_del_init(&mm->entry);
 400                         spin_unlock(&ucontext->mmap_lock);
 401                         PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
 402                              key, (unsigned long long) mm->addr, mm->len);
 403                         return mm;
 404                 }
 405         }
 406         spin_unlock(&ucontext->mmap_lock);
 407         return NULL;
 408 }
 409
 410 static inline void insert_mmap(struct c4iw_ucontext *ucontext,
 411                                struct c4iw_mm_entry *mm)
 412 {
 413         spin_lock(&ucontext->mmap_lock);
 414         PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
 415              mm->key, (unsigned long long) mm->addr, mm->len);
 416         list_add_tail(&mm->entry, &ucontext->mmaps);
 417         spin_unlock(&ucontext->mmap_lock);
 418 }
 419
 420 enum c4iw_qp_attr_mask {
 421         C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
 422         C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
 423         C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
 424         C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
 425         C4IW_QP_ATTR_MAX_ORD = 1 << 11,
 426         C4IW_QP_ATTR_MAX_IRD = 1 << 12,
 427         C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
 428         C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
 429         C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
 430         C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
 431         C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ |
 432                                      C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
 433                                      C4IW_QP_ATTR_MAX_ORD |
 434                                      C4IW_QP_ATTR_MAX_IRD |
 435                                      C4IW_QP_ATTR_LLP_STREAM_HANDLE |
 436                                      C4IW_QP_ATTR_STREAM_MSG_BUFFER |
 437                                      C4IW_QP_ATTR_MPA_ATTR |
 438                                      C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
 439 };
 440
 441 int c4iw_modify_qp(struct c4iw_dev *rhp,
 442                                 struct c4iw_qp *qhp,
 443                                 enum c4iw_qp_attr_mask mask,
 444                                 struct c4iw_qp_attributes *attrs,
 445                                 int internal);
 446
 447 enum c4iw_qp_state {
 448         C4IW_QP_STATE_IDLE,
 449         C4IW_QP_STATE_RTS,
 450         C4IW_QP_STATE_ERROR,
 451         C4IW_QP_STATE_TERMINATE,
 452         C4IW_QP_STATE_CLOSING,
 453         C4IW_QP_STATE_TOT
 454 };
 455
 456 static inline int c4iw_convert_state(enum ib_qp_state ib_state)
 457 {
 458         switch (ib_state) {
 459         case IB_QPS_RESET:
 460         case IB_QPS_INIT:
 461                 return C4IW_QP_STATE_IDLE;
 462         case IB_QPS_RTS:
 463                 return C4IW_QP_STATE_RTS;
 464         case IB_QPS_SQD:
 465                 return C4IW_QP_STATE_CLOSING;
 466         case IB_QPS_SQE:
 467                 return C4IW_QP_STATE_TERMINATE;
 468         case IB_QPS_ERR:
 469                 return C4IW_QP_STATE_ERROR;
 470         default:
 471                 return -1;
 472         }
 473 }
 474
 475 static inline u32 c4iw_ib_to_tpt_access(int a)
 476 {
 477         return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
 478                (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) |
 479                (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) |
 480                FW_RI_MEM_ACCESS_LOCAL_READ;
 481 }
 482
 483 static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
 484 {
 485         return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
 486                (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
 487 }
 488
 489 enum c4iw_mmid_state {
 490         C4IW_STAG_STATE_VALID,
 491         C4IW_STAG_STATE_INVALID
 492 };
 493
 494 #define C4IW_NODE_DESC "cxgb4 Chelsio Communications"
 495
 496 #define MPA_KEY_REQ "MPA ID Req Frame"
 497 #define MPA_KEY_REP "MPA ID Rep Frame"
 498
 499 #define MPA_MAX_PRIVATE_DATA    256
 500 #define MPA_REJECT              0x20
 501 #define MPA_CRC                 0x40
 502 #define MPA_MARKERS             0x80
 503 #define MPA_FLAGS_MASK          0xE0
 504
 505 #define c4iw_put_ep(ep) { \
 506         PDBG("put_ep (via %s:%u) ep %p refcnt %d\n", __func__, __LINE__,  \
 507              ep, atomic_read(&((ep)->kref.refcount))); \
 508         WARN_ON(atomic_read(&((ep)->kref.refcount)) < 1); \
 509         kref_put(&((ep)->kref), _c4iw_free_ep); \
 510 }
 511
 512 #define c4iw_get_ep(ep) { \
 513         PDBG("get_ep (via %s:%u) ep %p, refcnt %d\n", __func__, __LINE__, \
 514              ep, atomic_read(&((ep)->kref.refcount))); \
 515         kref_get(&((ep)->kref));  \
 516 }
 517 void _c4iw_free_ep(struct kref *kref);
 518
 519 struct mpa_message {
 520         u8 key[16];
 521         u8 flags;
 522         u8 revision;
 523         __be16 private_data_size;
 524         u8 private_data[0];
 525 };
 526
 527 struct terminate_message {
 528         u8 layer_etype;
 529         u8 ecode;
 530         __be16 hdrct_rsvd;
 531         u8 len_hdrs[0];
 532 };
 533
 534 #define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)
 535
 536 enum c4iw_layers_types {
 537         LAYER_RDMAP             = 0x00,
 538         LAYER_DDP               = 0x10,
 539         LAYER_MPA               = 0x20,
 540         RDMAP_LOCAL_CATA        = 0x00,
 541         RDMAP_REMOTE_PROT       = 0x01,
 542         RDMAP_REMOTE_OP         = 0x02,
 543         DDP_LOCAL_CATA          = 0x00,
 544         DDP_TAGGED_ERR          = 0x01,
 545         DDP_UNTAGGED_ERR        = 0x02,
 546         DDP_LLP                 = 0x03
 547 };
 548
 549 enum c4iw_rdma_ecodes {
 550         RDMAP_INV_STAG          = 0x00,
 551         RDMAP_BASE_BOUNDS       = 0x01,
 552         RDMAP_ACC_VIOL          = 0x02,
 553         RDMAP_STAG_NOT_ASSOC    = 0x03,
 554         RDMAP_TO_WRAP           = 0x04,
 555         RDMAP_INV_VERS          = 0x05,
 556         RDMAP_INV_OPCODE        = 0x06,
 557         RDMAP_STREAM_CATA       = 0x07,
 558         RDMAP_GLOBAL_CATA       = 0x08,
 559         RDMAP_CANT_INV_STAG     = 0x09,
 560         RDMAP_UNSPECIFIED       = 0xff
 561 };
 562
 563 enum c4iw_ddp_ecodes {
 564         DDPT_INV_STAG           = 0x00,
 565         DDPT_BASE_BOUNDS        = 0x01,
 566         DDPT_STAG_NOT_ASSOC     = 0x02,
 567         DDPT_TO_WRAP            = 0x03,
 568         DDPT_INV_VERS           = 0x04,
 569         DDPU_INV_QN             = 0x01,
 570         DDPU_INV_MSN_NOBUF      = 0x02,
 571         DDPU_INV_MSN_RANGE      = 0x03,
 572         DDPU_INV_MO             = 0x04,
 573         DDPU_MSG_TOOBIG         = 0x05,
 574         DDPU_INV_VERS           = 0x06
 575 };
 576
 577 enum c4iw_mpa_ecodes {
 578         MPA_CRC_ERR             = 0x02,
 579         MPA_MARKER_ERR          = 0x03
 580 };
 581
 582 enum c4iw_ep_state {
 583         IDLE = 0,
 584         LISTEN,
 585         CONNECTING,
 586         MPA_REQ_WAIT,
 587         MPA_REQ_SENT,
 588         MPA_REQ_RCVD,
 589         MPA_REP_SENT,
 590         FPDU_MODE,
 591         ABORTING,
 592         CLOSING,
 593         MORIBUND,
 594         DEAD,
 595 };
 596
 597 enum c4iw_ep_flags {
 598         PEER_ABORT_IN_PROGRESS  = 0,
 599         ABORT_REQ_IN_PROGRESS   = 1,
 600         RELEASE_RESOURCES       = 2,
 601         CLOSE_SENT              = 3,
 602 };
 603
 604 struct c4iw_ep_common {
 605         struct iw_cm_id *cm_id;
 606         struct c4iw_qp *qp;
 607         struct c4iw_dev *dev;
 608         enum c4iw_ep_state state;
 609         struct kref kref;
 610         struct mutex mutex;
 611         struct sockaddr_in local_addr;
 612         struct sockaddr_in remote_addr;
 613         struct c4iw_wr_wait wr_wait;
 614         unsigned long flags;
 615 };
 616
 617 struct c4iw_listen_ep {
 618         struct c4iw_ep_common com;
 619         unsigned int stid;
 620         int backlog;
 621 };
 622
 623 struct c4iw_ep {
 624         struct c4iw_ep_common com;
 625         struct c4iw_ep *parent_ep;
 626         struct timer_list timer;
 627         struct list_head entry;
 628         unsigned int atid;
 629         u32 hwtid;
 630         u32 snd_seq;
 631         u32 rcv_seq;
 632         struct l2t_entry *l2t;
 633         struct dst_entry *dst;
 634         struct sk_buff *mpa_skb;
 635         struct c4iw_mpa_attributes mpa_attr;
 636         u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
 637         unsigned int mpa_pkt_len;
 638         u32 ird;
 639         u32 ord;
 640         u32 smac_idx;
 641         u32 tx_chan;
 642         u32 mtu;
 643         u16 mss;
 644         u16 emss;
 645         u16 plen;
 646         u16 rss_qid;
 647         u16 txq_idx;
 648         u16 ctrlq_idx;
 649         u8 tos;
 650 };
 651
 652 static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id)
 653 {
 654         return cm_id->provider_data;
 655 }
 656
 657 static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id)
 658 {
 659         return cm_id->provider_data;
 660 }
 661
 662 static inline int compute_wscale(int win)
 663 {
 664         int wscale = 0;
 665
 666         while (wscale < 14 && (65535<<wscale) < win)
 667                 wscale++;
 668         return wscale;
 669 }
 670
 671 typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct sk_buff *skb);
 672
 673 int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
 674                      struct l2t_entry *l2t);
 675 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qpid,
 676                    struct c4iw_dev_ucontext *uctx);
 677 u32 c4iw_get_resource(struct kfifo *fifo, spinlock_t *lock);
 678 void c4iw_put_resource(struct kfifo *fifo, u32 entry, spinlock_t *lock);
 679 int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
 680 int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
 681 int c4iw_pblpool_create(struct c4iw_rdev *rdev);
 682 int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
 683 int c4iw_ocqp_pool_create(struct c4iw_rdev *rdev);
 684 void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
 685 void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
 686 void c4iw_ocqp_pool_destroy(struct c4iw_rdev *rdev);
 687 void c4iw_destroy_resource(struct c4iw_resource *rscp);
 688 int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
 689 int c4iw_register_device(struct c4iw_dev *dev);
 690 void c4iw_unregister_device(struct c4iw_dev *dev);
 691 int __init c4iw_cm_init(void);
 692 void __exit c4iw_cm_term(void);
 693 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
 694                                struct c4iw_dev_ucontext *uctx);
 695 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
 696                             struct c4iw_dev_ucontext *uctx);
 697 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
 698 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
 699                       struct ib_send_wr **bad_wr);
 700 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
 701                       struct ib_recv_wr **bad_wr);
 702 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw,
 703                  struct ib_mw_bind *mw_bind);
 704 int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
 705 int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog);
 706 int c4iw_destroy_listen(struct iw_cm_id *cm_id);
 707 int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
 708 int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
 709 void c4iw_qp_add_ref(struct ib_qp *qp);
 710 void c4iw_qp_rem_ref(struct ib_qp *qp);
 711 void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *page_list);
 712 struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl(
 713                                         struct ib_device *device,
 714                                         int page_list_len);
 715 struct ib_mr *c4iw_alloc_fast_reg_mr(struct ib_pd *pd, int pbl_depth);
 716 int c4iw_dealloc_mw(struct ib_mw *mw);
 717 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd);
 718 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start,
 719                                            u64 length, u64 virt, int acc,
 720                                            struct ib_udata *udata);
 721 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc);
 722 struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd,
 723                                         struct ib_phys_buf *buffer_list,
 724                                         int num_phys_buf,
 725                                         int acc,
 726                                         u64 *iova_start);
 727 int c4iw_reregister_phys_mem(struct ib_mr *mr,
 728                                      int mr_rereg_mask,
 729                                      struct ib_pd *pd,
 730                                      struct ib_phys_buf *buffer_list,
 731                                      int num_phys_buf,
 732                                      int acc, u64 *iova_start);
 733 int c4iw_dereg_mr(struct ib_mr *ib_mr);
 734 int c4iw_destroy_cq(struct ib_cq *ib_cq);
 735 struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, int entries,
 736                                         int vector,
 737                                         struct ib_ucontext *ib_context,
 738                                         struct ib_udata *udata);
 739 int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
 740 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
 741 int c4iw_destroy_qp(struct ib_qp *ib_qp);
 742 struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
 743                              struct ib_qp_init_attr *attrs,
 744                              struct ib_udata *udata);
 745 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
 746                                  int attr_mask, struct ib_udata *udata);
 747 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn);
 748 u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
 749 void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
 750 u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
 751 void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
 752 u32 c4iw_ocqp_pool_alloc(struct c4iw_rdev *rdev, int size);
 753 void c4iw_ocqp_pool_free(struct c4iw_rdev *rdev, u32 addr, int size);
 754 int c4iw_ofld_send(struct c4iw_rdev *rdev, struct sk_buff *skb);
 755 void c4iw_flush_hw_cq(struct t4_cq *cq);
 756 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
 757 void c4iw_count_scqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
 758 int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
 759 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
 760 int c4iw_flush_sq(struct t4_wq *wq, struct t4_cq *cq, int count);
 761 int c4iw_ev_handler(struct c4iw_dev *rnicp, u32 qid);
 762 u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
 763 int c4iw_post_zb_read(struct c4iw_qp *qhp);
 764 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
 765 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
 766 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
 767                 struct c4iw_dev_ucontext *uctx);
 768 u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
 769 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
 770                 struct c4iw_dev_ucontext *uctx);
 771 void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe);
 772
 773 extern struct cxgb4_client t4c_client;
 774 extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS];
 775 extern int c4iw_max_read_depth;
 776
 777 #endif