| blob | 8f44d0cf38330b8e743424af8084c142b26280c0 |
1 /*
2 * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
34 #ifndef _IPATH_REGISTERS_H
35 #define _IPATH_REGISTERS_H
37 /*
38 * This file should only be included by kernel source, and by the diags. It
39 * defines the registers, and their contents, for InfiniPath chips.
40 */
42 /*
43 * These are the InfiniPath register and buffer bit definitions,
44 * that are visible to software, and needed only by the kernel
45 * and diag code. A few, that are visible to protocol and user
46 * code are in ipath_common.h. Some bits are specific
47 * to a given chip implementation, and have been moved to the
48 * chip-specific source file
49 */
51 /* kr_revision bits */
52 #define INFINIPATH_R_CHIPREVMINOR_MASK 0xFF
53 #define INFINIPATH_R_CHIPREVMINOR_SHIFT 0
54 #define INFINIPATH_R_CHIPREVMAJOR_MASK 0xFF
55 #define INFINIPATH_R_CHIPREVMAJOR_SHIFT 8
56 #define INFINIPATH_R_ARCH_MASK 0xFF
57 #define INFINIPATH_R_ARCH_SHIFT 16
58 #define INFINIPATH_R_SOFTWARE_MASK 0xFF
59 #define INFINIPATH_R_SOFTWARE_SHIFT 24
60 #define INFINIPATH_R_BOARDID_MASK 0xFF
61 #define INFINIPATH_R_BOARDID_SHIFT 32
63 /* kr_control bits */
64 #define INFINIPATH_C_FREEZEMODE 0x00000002
65 #define INFINIPATH_C_LINKENABLE 0x00000004
67 /* kr_sendctrl bits */
68 #define INFINIPATH_S_DISARMPIOBUF_SHIFT 16
69 #define INFINIPATH_S_UPDTHRESH_SHIFT 24
70 #define INFINIPATH_S_UPDTHRESH_MASK 0x1f
72 #define IPATH_S_ABORT 0
73 #define IPATH_S_PIOINTBUFAVAIL 1
74 #define IPATH_S_PIOBUFAVAILUPD 2
75 #define IPATH_S_PIOENABLE 3
76 #define IPATH_S_SDMAINTENABLE 9
77 #define IPATH_S_SDMASINGLEDESCRIPTOR 10
78 #define IPATH_S_SDMAENABLE 11
79 #define IPATH_S_SDMAHALT 12
80 #define IPATH_S_DISARM 31
82 #define INFINIPATH_S_ABORT (1U << IPATH_S_ABORT)
83 #define INFINIPATH_S_PIOINTBUFAVAIL (1U << IPATH_S_PIOINTBUFAVAIL)
84 #define INFINIPATH_S_PIOBUFAVAILUPD (1U << IPATH_S_PIOBUFAVAILUPD)
85 #define INFINIPATH_S_PIOENABLE (1U << IPATH_S_PIOENABLE)
86 #define INFINIPATH_S_SDMAINTENABLE (1U << IPATH_S_SDMAINTENABLE)
87 #define INFINIPATH_S_SDMASINGLEDESCRIPTOR \
88 (1U << IPATH_S_SDMASINGLEDESCRIPTOR)
89 #define INFINIPATH_S_SDMAENABLE (1U << IPATH_S_SDMAENABLE)
90 #define INFINIPATH_S_SDMAHALT (1U << IPATH_S_SDMAHALT)
91 #define INFINIPATH_S_DISARM (1U << IPATH_S_DISARM)
93 /* kr_rcvctrl bits that are the same on multiple chips */
94 #define INFINIPATH_R_PORTENABLE_SHIFT 0
95 #define INFINIPATH_R_QPMAP_ENABLE (1ULL << 38)
97 /* kr_intstatus, kr_intclear, kr_intmask bits */
98 #define INFINIPATH_I_SDMAINT 0x8000000000000000ULL
99 #define INFINIPATH_I_SDMADISABLED 0x4000000000000000ULL
100 #define INFINIPATH_I_ERROR 0x0000000080000000ULL
101 #define INFINIPATH_I_SPIOSENT 0x0000000040000000ULL
102 #define INFINIPATH_I_SPIOBUFAVAIL 0x0000000020000000ULL
103 #define INFINIPATH_I_GPIO 0x0000000010000000ULL
104 #define INFINIPATH_I_JINT 0x0000000004000000ULL
106 /* kr_errorstatus, kr_errorclear, kr_errormask bits */
107 #define INFINIPATH_E_RFORMATERR 0x0000000000000001ULL
108 #define INFINIPATH_E_RVCRC 0x0000000000000002ULL
109 #define INFINIPATH_E_RICRC 0x0000000000000004ULL
110 #define INFINIPATH_E_RMINPKTLEN 0x0000000000000008ULL
111 #define INFINIPATH_E_RMAXPKTLEN 0x0000000000000010ULL
112 #define INFINIPATH_E_RLONGPKTLEN 0x0000000000000020ULL
113 #define INFINIPATH_E_RSHORTPKTLEN 0x0000000000000040ULL
114 #define INFINIPATH_E_RUNEXPCHAR 0x0000000000000080ULL
115 #define INFINIPATH_E_RUNSUPVL 0x0000000000000100ULL
116 #define INFINIPATH_E_REBP 0x0000000000000200ULL
117 #define INFINIPATH_E_RIBFLOW 0x0000000000000400ULL
118 #define INFINIPATH_E_RBADVERSION 0x0000000000000800ULL
119 #define INFINIPATH_E_RRCVEGRFULL 0x0000000000001000ULL
120 #define INFINIPATH_E_RRCVHDRFULL 0x0000000000002000ULL
121 #define INFINIPATH_E_RBADTID 0x0000000000004000ULL
122 #define INFINIPATH_E_RHDRLEN 0x0000000000008000ULL
123 #define INFINIPATH_E_RHDR 0x0000000000010000ULL
124 #define INFINIPATH_E_RIBLOSTLINK 0x0000000000020000ULL
125 #define INFINIPATH_E_SENDSPECIALTRIGGER 0x0000000008000000ULL
126 #define INFINIPATH_E_SDMADISABLED 0x0000000010000000ULL
127 #define INFINIPATH_E_SMINPKTLEN 0x0000000020000000ULL
128 #define INFINIPATH_E_SMAXPKTLEN 0x0000000040000000ULL
129 #define INFINIPATH_E_SUNDERRUN 0x0000000080000000ULL
130 #define INFINIPATH_E_SPKTLEN 0x0000000100000000ULL
131 #define INFINIPATH_E_SDROPPEDSMPPKT 0x0000000200000000ULL
132 #define INFINIPATH_E_SDROPPEDDATAPKT 0x0000000400000000ULL
133 #define INFINIPATH_E_SPIOARMLAUNCH 0x0000000800000000ULL
134 #define INFINIPATH_E_SUNEXPERRPKTNUM 0x0000001000000000ULL
135 #define INFINIPATH_E_SUNSUPVL 0x0000002000000000ULL
136 #define INFINIPATH_E_SENDBUFMISUSE 0x0000004000000000ULL
137 #define INFINIPATH_E_SDMAGENMISMATCH 0x0000008000000000ULL
138 #define INFINIPATH_E_SDMAOUTOFBOUND 0x0000010000000000ULL
139 #define INFINIPATH_E_SDMATAILOUTOFBOUND 0x0000020000000000ULL
140 #define INFINIPATH_E_SDMABASE 0x0000040000000000ULL
141 #define INFINIPATH_E_SDMA1STDESC 0x0000080000000000ULL
142 #define INFINIPATH_E_SDMARPYTAG 0x0000100000000000ULL
143 #define INFINIPATH_E_SDMADWEN 0x0000200000000000ULL
144 #define INFINIPATH_E_SDMAMISSINGDW 0x0000400000000000ULL
145 #define INFINIPATH_E_SDMAUNEXPDATA 0x0000800000000000ULL
146 #define INFINIPATH_E_IBSTATUSCHANGED 0x0001000000000000ULL
147 #define INFINIPATH_E_INVALIDADDR 0x0002000000000000ULL
148 #define INFINIPATH_E_RESET 0x0004000000000000ULL
149 #define INFINIPATH_E_HARDWARE 0x0008000000000000ULL
150 #define INFINIPATH_E_SDMADESCADDRMISALIGN 0x0010000000000000ULL
151 #define INFINIPATH_E_INVALIDEEPCMD 0x0020000000000000ULL
153 /*
154 * this is used to print "common" packet errors only when the
155 * __IPATH_ERRPKTDBG bit is set in ipath_debug.
156 */
157 #define INFINIPATH_E_PKTERRS ( INFINIPATH_E_SPKTLEN \
158 | INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_RVCRC \
159 | INFINIPATH_E_RICRC | INFINIPATH_E_RSHORTPKTLEN \
160 | INFINIPATH_E_REBP )
162 /* Convenience for decoding Send DMA errors */
163 #define INFINIPATH_E_SDMAERRS ( \
164 INFINIPATH_E_SDMAGENMISMATCH | INFINIPATH_E_SDMAOUTOFBOUND | \
165 INFINIPATH_E_SDMATAILOUTOFBOUND | INFINIPATH_E_SDMABASE | \
166 INFINIPATH_E_SDMA1STDESC | INFINIPATH_E_SDMARPYTAG | \
167 INFINIPATH_E_SDMADWEN | INFINIPATH_E_SDMAMISSINGDW | \
168 INFINIPATH_E_SDMAUNEXPDATA | \
169 INFINIPATH_E_SDMADESCADDRMISALIGN | \
170 INFINIPATH_E_SDMADISABLED | \
171 INFINIPATH_E_SENDBUFMISUSE)
173 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
174 /* TXEMEMPARITYERR bit 0: PIObuf, 1: PIOpbc, 2: launchfifo
175 * RXEMEMPARITYERR bit 0: rcvbuf, 1: lookupq, 2: expTID, 3: eagerTID
176 * bit 4: flag buffer, 5: datainfo, 6: header info */
177 #define INFINIPATH_HWE_TXEMEMPARITYERR_MASK 0xFULL
178 #define INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT 40
179 #define INFINIPATH_HWE_RXEMEMPARITYERR_MASK 0x7FULL
180 #define INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT 44
181 #define INFINIPATH_HWE_IBCBUSTOSPCPARITYERR 0x4000000000000000ULL
182 #define INFINIPATH_HWE_IBCBUSFRSPCPARITYERR 0x8000000000000000ULL
183 /* txe mem parity errors (shift by INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) */
184 #define INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF 0x1ULL
185 #define INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC 0x2ULL
186 #define INFINIPATH_HWE_TXEMEMPARITYERR_PIOLAUNCHFIFO 0x4ULL
187 /* rxe mem parity errors (shift by INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) */
188 #define INFINIPATH_HWE_RXEMEMPARITYERR_RCVBUF 0x01ULL
189 #define INFINIPATH_HWE_RXEMEMPARITYERR_LOOKUPQ 0x02ULL
190 #define INFINIPATH_HWE_RXEMEMPARITYERR_EXPTID 0x04ULL
191 #define INFINIPATH_HWE_RXEMEMPARITYERR_EAGERTID 0x08ULL
192 #define INFINIPATH_HWE_RXEMEMPARITYERR_FLAGBUF 0x10ULL
193 #define INFINIPATH_HWE_RXEMEMPARITYERR_DATAINFO 0x20ULL
194 #define INFINIPATH_HWE_RXEMEMPARITYERR_HDRINFO 0x40ULL
195 /* waldo specific -- find the rest in ipath_6110.c */
196 #define INFINIPATH_HWE_RXDSYNCMEMPARITYERR 0x0000000400000000ULL
197 /* 6120/7220 specific -- find the rest in ipath_6120.c and ipath_7220.c */
198 #define INFINIPATH_HWE_MEMBISTFAILED 0x0040000000000000ULL
200 /* kr_hwdiagctrl bits */
201 #define INFINIPATH_DC_FORCETXEMEMPARITYERR_MASK 0xFULL
202 #define INFINIPATH_DC_FORCETXEMEMPARITYERR_SHIFT 40
203 #define INFINIPATH_DC_FORCERXEMEMPARITYERR_MASK 0x7FULL
204 #define INFINIPATH_DC_FORCERXEMEMPARITYERR_SHIFT 44
205 #define INFINIPATH_DC_FORCERXDSYNCMEMPARITYERR 0x0000000400000000ULL
206 #define INFINIPATH_DC_COUNTERDISABLE 0x1000000000000000ULL
207 #define INFINIPATH_DC_COUNTERWREN 0x2000000000000000ULL
208 #define INFINIPATH_DC_FORCEIBCBUSTOSPCPARITYERR 0x4000000000000000ULL
209 #define INFINIPATH_DC_FORCEIBCBUSFRSPCPARITYERR 0x8000000000000000ULL
211 /* kr_ibcctrl bits */
212 #define INFINIPATH_IBCC_FLOWCTRLPERIOD_MASK 0xFFULL
213 #define INFINIPATH_IBCC_FLOWCTRLPERIOD_SHIFT 0
214 #define INFINIPATH_IBCC_FLOWCTRLWATERMARK_MASK 0xFFULL
215 #define INFINIPATH_IBCC_FLOWCTRLWATERMARK_SHIFT 8
216 #define INFINIPATH_IBCC_LINKINITCMD_MASK 0x3ULL
217 #define INFINIPATH_IBCC_LINKINITCMD_DISABLE 1
218 /* cycle through TS1/TS2 till OK */
219 #define INFINIPATH_IBCC_LINKINITCMD_POLL 2
220 /* wait for TS1, then go on */
221 #define INFINIPATH_IBCC_LINKINITCMD_SLEEP 3
222 #define INFINIPATH_IBCC_LINKINITCMD_SHIFT 16
223 #define INFINIPATH_IBCC_LINKCMD_MASK 0x3ULL
227 #define INFINIPATH_IBCC_LINKCMD_SHIFT 18
228 #define INFINIPATH_IBCC_MAXPKTLEN_MASK 0x7FFULL
229 #define INFINIPATH_IBCC_MAXPKTLEN_SHIFT 20
230 #define INFINIPATH_IBCC_PHYERRTHRESHOLD_MASK 0xFULL
231 #define INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT 32
232 #define INFINIPATH_IBCC_OVERRUNTHRESHOLD_MASK 0xFULL
233 #define INFINIPATH_IBCC_OVERRUNTHRESHOLD_SHIFT 36
234 #define INFINIPATH_IBCC_CREDITSCALE_MASK 0x7ULL
235 #define INFINIPATH_IBCC_CREDITSCALE_SHIFT 40
236 #define INFINIPATH_IBCC_LOOPBACK 0x8000000000000000ULL
237 #define INFINIPATH_IBCC_LINKDOWNDEFAULTSTATE 0x4000000000000000ULL
239 /* kr_ibcstatus bits */
240 #define INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT 0
241 #define INFINIPATH_IBCS_LINKSTATE_MASK 0x7
243 #define INFINIPATH_IBCS_TXREADY 0x40000000
244 #define INFINIPATH_IBCS_TXCREDITOK 0x80000000
245 /* link training states (shift by
246 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) */
247 #define INFINIPATH_IBCS_LT_STATE_DISABLED 0x00
248 #define INFINIPATH_IBCS_LT_STATE_LINKUP 0x01
249 #define INFINIPATH_IBCS_LT_STATE_POLLACTIVE 0x02
250 #define INFINIPATH_IBCS_LT_STATE_POLLQUIET 0x03
251 #define INFINIPATH_IBCS_LT_STATE_SLEEPDELAY 0x04
252 #define INFINIPATH_IBCS_LT_STATE_SLEEPQUIET 0x05
253 #define INFINIPATH_IBCS_LT_STATE_CFGDEBOUNCE 0x08
254 #define INFINIPATH_IBCS_LT_STATE_CFGRCVFCFG 0x09
255 #define INFINIPATH_IBCS_LT_STATE_CFGWAITRMT 0x0a
256 #define INFINIPATH_IBCS_LT_STATE_CFGIDLE 0x0b
257 #define INFINIPATH_IBCS_LT_STATE_RECOVERRETRAIN 0x0c
258 #define INFINIPATH_IBCS_LT_STATE_RECOVERWAITRMT 0x0e
259 #define INFINIPATH_IBCS_LT_STATE_RECOVERIDLE 0x0f
260 /* link state machine states (shift by ibcs_ls_shift) */
261 #define INFINIPATH_IBCS_L_STATE_DOWN 0x0
262 #define INFINIPATH_IBCS_L_STATE_INIT 0x1
263 #define INFINIPATH_IBCS_L_STATE_ARM 0x2
264 #define INFINIPATH_IBCS_L_STATE_ACTIVE 0x3
265 #define INFINIPATH_IBCS_L_STATE_ACT_DEFER 0x4
268 /* kr_extstatus bits */
269 #define INFINIPATH_EXTS_SERDESPLLLOCK 0x1
270 #define INFINIPATH_EXTS_GPIOIN_MASK 0xFFFFULL
271 #define INFINIPATH_EXTS_GPIOIN_SHIFT 48
273 /* kr_extctrl bits */
274 #define INFINIPATH_EXTC_GPIOINVERT_MASK 0xFFFFULL
275 #define INFINIPATH_EXTC_GPIOINVERT_SHIFT 32
276 #define INFINIPATH_EXTC_GPIOOE_MASK 0xFFFFULL
277 #define INFINIPATH_EXTC_GPIOOE_SHIFT 48
278 #define INFINIPATH_EXTC_SERDESENABLE 0x80000000ULL
279 #define INFINIPATH_EXTC_SERDESCONNECT 0x40000000ULL
280 #define INFINIPATH_EXTC_SERDESENTRUNKING 0x20000000ULL
281 #define INFINIPATH_EXTC_SERDESDISRXFIFO 0x10000000ULL
282 #define INFINIPATH_EXTC_SERDESENPLPBK1 0x08000000ULL
283 #define INFINIPATH_EXTC_SERDESENPLPBK2 0x04000000ULL
284 #define INFINIPATH_EXTC_SERDESENENCDEC 0x02000000ULL
285 #define INFINIPATH_EXTC_LED1SECPORT_ON 0x00000020ULL
286 #define INFINIPATH_EXTC_LED2SECPORT_ON 0x00000010ULL
287 #define INFINIPATH_EXTC_LED1PRIPORT_ON 0x00000008ULL
288 #define INFINIPATH_EXTC_LED2PRIPORT_ON 0x00000004ULL
289 #define INFINIPATH_EXTC_LEDGBLOK_ON 0x00000002ULL
290 #define INFINIPATH_EXTC_LEDGBLERR_OFF 0x00000001ULL
292 /* kr_partitionkey bits */
293 #define INFINIPATH_PKEY_SIZE 16
294 #define INFINIPATH_PKEY_MASK 0xFFFF
295 #define INFINIPATH_PKEY_DEFAULT_PKEY 0xFFFF
297 /* kr_serdesconfig0 bits */
300 /* tx idle enables (per lane) */
301 #define INFINIPATH_SERDC0_TXIDLE 0xF000ULL
302 /* rx detect enables (per lane) */
303 #define INFINIPATH_SERDC0_RXDETECT_EN 0xF0000ULL
304 /* L1 Power down; use with RXDETECT, Otherwise not used on IB side */
305 #define INFINIPATH_SERDC0_L1PWR_DN 0xF0ULL
307 /* common kr_xgxsconfig bits (or safe in all, even if not implemented) */
308 #define INFINIPATH_XGXS_RX_POL_SHIFT 19
309 #define INFINIPATH_XGXS_RX_POL_MASK 0xfULL
312 /*
313 * IPATH_PIO_MAXIBHDR is the max IB header size allowed for in our
314 * PIO send buffers. This is well beyond anything currently
315 * defined in the InfiniBand spec.
316 */
317 #define IPATH_PIO_MAXIBHDR 128
321 /* The following change with the type of device, so
322 * need to be part of the ipath_devdata struct, or
323 * we could have problems plugging in devices of
324 * different types (e.g. one HT, one PCIE)
325 * in one system, to be managed by one driver.
326 * On the other hand, this file is may also be included
327 * by other code, so leave the declarations here
328 * temporarily. Minor footprint issue if common-model
329 * linker used, none if C89+ linker used.
330 */
332 /* mask of defined bits for various registers */
336 /* masks that are different in various chips, or only exist in some chips */
339 /*
340 * These are the infinipath general register numbers (not offsets).
341 * The kernel registers are used directly, those beyond the kernel
342 * registers are calculated from one of the base registers. The use of
343 * an integer type doesn't allow type-checking as thorough as, say,
344 * an enum but allows for better hiding of chip differences.
345 */
350 /*
351 * These are the chip registers common to all infinipath chips, and
352 * used both by the kernel and the diagnostics or other user code.
353 * They are all implemented such that 64 bit accesses work.
354 * Some implement no more than 32 bits. Because 64 bit reads
355 * require 2 HT cmds on opteron, we access those with 32 bit
356 * reads for efficiency (they are written as 64 bits, since
357 * the extra 32 bits are nearly free on writes, and it slightly reduces
358 * complexity). The rest are all accessed as 64 bits.
359 */
361 /* These are the 32 bit group */
362 ipath_kreg kr_control;
363 ipath_kreg kr_counterregbase;
364 ipath_kreg kr_intmask;
365 ipath_kreg kr_intstatus;
366 ipath_kreg kr_pagealign;
367 ipath_kreg kr_portcnt;
368 ipath_kreg kr_rcvtidbase;
369 ipath_kreg kr_rcvtidcnt;
370 ipath_kreg kr_rcvegrbase;
371 ipath_kreg kr_rcvegrcnt;
372 ipath_kreg kr_scratch;
373 ipath_kreg kr_sendctrl;
374 ipath_kreg kr_sendpiobufbase;
375 ipath_kreg kr_sendpiobufcnt;
376 ipath_kreg kr_sendpiosize;
377 ipath_kreg kr_sendregbase;
378 ipath_kreg kr_userregbase;
379 /* These are the 64 bit group */
380 ipath_kreg kr_debugport;
381 ipath_kreg kr_debugportselect;
382 ipath_kreg kr_errorclear;
383 ipath_kreg kr_errormask;
384 ipath_kreg kr_errorstatus;
385 ipath_kreg kr_extctrl;
386 ipath_kreg kr_extstatus;
387 ipath_kreg kr_gpio_clear;
388 ipath_kreg kr_gpio_mask;
389 ipath_kreg kr_gpio_out;
390 ipath_kreg kr_gpio_status;
391 ipath_kreg kr_hwdiagctrl;
392 ipath_kreg kr_hwerrclear;
393 ipath_kreg kr_hwerrmask;
394 ipath_kreg kr_hwerrstatus;
395 ipath_kreg kr_ibcctrl;
396 ipath_kreg kr_ibcstatus;
397 ipath_kreg kr_intblocked;
398 ipath_kreg kr_intclear;
399 ipath_kreg kr_interruptconfig;
400 ipath_kreg kr_mdio;
401 ipath_kreg kr_partitionkey;
402 ipath_kreg kr_rcvbthqp;
403 ipath_kreg kr_rcvbufbase;
404 ipath_kreg kr_rcvbufsize;
405 ipath_kreg kr_rcvctrl;
406 ipath_kreg kr_rcvhdrcnt;
407 ipath_kreg kr_rcvhdrentsize;
408 ipath_kreg kr_rcvhdrsize;
409 ipath_kreg kr_rcvintmembase;
410 ipath_kreg kr_rcvintmemsize;
411 ipath_kreg kr_revision;
412 ipath_kreg kr_sendbuffererror;
413 ipath_kreg kr_sendpioavailaddr;
414 ipath_kreg kr_serdesconfig0;
415 ipath_kreg kr_serdesconfig1;
416 ipath_kreg kr_serdesstatus;
417 ipath_kreg kr_txintmembase;
418 ipath_kreg kr_txintmemsize;
419 ipath_kreg kr_xgxsconfig;
420 ipath_kreg kr_ibpllcfg;
421 /* use these two (and the following N ports) only with
422 * ipath_k*_kreg64_port(); not *kreg64() */
423 ipath_kreg kr_rcvhdraddr;
424 ipath_kreg kr_rcvhdrtailaddr;
426 /* remaining registers are not present on all types of infinipath
427 chips */
428 ipath_kreg kr_rcvpktledcnt;
429 ipath_kreg kr_pcierbuftestreg0;
430 ipath_kreg kr_pcierbuftestreg1;
431 ipath_kreg kr_pcieq0serdesconfig0;
432 ipath_kreg kr_pcieq0serdesconfig1;
433 ipath_kreg kr_pcieq0serdesstatus;
434 ipath_kreg kr_pcieq1serdesconfig0;
435 ipath_kreg kr_pcieq1serdesconfig1;
436 ipath_kreg kr_pcieq1serdesstatus;
437 ipath_kreg kr_hrtbt_guid;
438 ipath_kreg kr_ibcddrctrl;
439 ipath_kreg kr_ibcddrstatus;
440 ipath_kreg kr_jintreload;
442 /* send dma related regs */
443 ipath_kreg kr_senddmabase;
444 ipath_kreg kr_senddmalengen;
445 ipath_kreg kr_senddmatail;
446 ipath_kreg kr_senddmahead;
447 ipath_kreg kr_senddmaheadaddr;
448 ipath_kreg kr_senddmabufmask0;
449 ipath_kreg kr_senddmabufmask1;
450 ipath_kreg kr_senddmabufmask2;
451 ipath_kreg kr_senddmastatus;
453 /* SerDes related regs (IBA7220-only) */
454 ipath_kreg kr_ibserdesctrl;
455 ipath_kreg kr_ib_epbacc;
456 ipath_kreg kr_ib_epbtrans;
457 ipath_kreg kr_pcie_epbacc;
458 ipath_kreg kr_pcie_epbtrans;
459 ipath_kreg kr_ib_ddsrxeq;
460 };
463 ipath_creg cr_badformatcnt;
464 ipath_creg cr_erricrccnt;
465 ipath_creg cr_errlinkcnt;
466 ipath_creg cr_errlpcrccnt;
467 ipath_creg cr_errpkey;
468 ipath_creg cr_errrcvflowctrlcnt;
469 ipath_creg cr_err_rlencnt;
470 ipath_creg cr_errslencnt;
471 ipath_creg cr_errtidfull;
472 ipath_creg cr_errtidvalid;
473 ipath_creg cr_errvcrccnt;
474 ipath_creg cr_ibstatuschange;
475 ipath_creg cr_intcnt;
476 ipath_creg cr_invalidrlencnt;
477 ipath_creg cr_invalidslencnt;
478 ipath_creg cr_lbflowstallcnt;
479 ipath_creg cr_iblinkdowncnt;
480 ipath_creg cr_iblinkerrrecovcnt;
481 ipath_creg cr_ibsymbolerrcnt;
482 ipath_creg cr_pktrcvcnt;
483 ipath_creg cr_pktrcvflowctrlcnt;
484 ipath_creg cr_pktsendcnt;
485 ipath_creg cr_pktsendflowcnt;
486 ipath_creg cr_portovflcnt;
487 ipath_creg cr_rcvebpcnt;
488 ipath_creg cr_rcvovflcnt;
489 ipath_creg cr_rxdroppktcnt;
490 ipath_creg cr_senddropped;
491 ipath_creg cr_sendstallcnt;
492 ipath_creg cr_sendunderruncnt;
493 ipath_creg cr_unsupvlcnt;
494 ipath_creg cr_wordrcvcnt;
495 ipath_creg cr_wordsendcnt;
496 ipath_creg cr_vl15droppedpktcnt;
497 ipath_creg cr_rxotherlocalphyerrcnt;
498 ipath_creg cr_excessbufferovflcnt;
499 ipath_creg cr_locallinkintegrityerrcnt;
500 ipath_creg cr_rxvlerrcnt;
501 ipath_creg cr_rxdlidfltrcnt;
502 ipath_creg cr_psstat;
503 ipath_creg cr_psstart;
504 ipath_creg cr_psinterval;
505 ipath_creg cr_psrcvdatacount;
506 ipath_creg cr_psrcvpktscount;
507 ipath_creg cr_psxmitdatacount;
508 ipath_creg cr_psxmitpktscount;
509 ipath_creg cr_psxmitwaitcount;
510 };