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Staging: zram: fix up some sysfs attribute permissions
[zen-stable.git] / drivers / infiniband / hw / qib / qib_verbs.c
blob9fab404888505be57b9fdbc1f813f3ae28e290c1
1 /*
2 * Copyright (c) 2006, 2007, 2008, 2009, 2010 QLogic Corporation.
3 * All rights reserved.
4 * Copyright (c) 2005, 2006 PathScale, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <rdma/ib_mad.h>
36 #include <rdma/ib_user_verbs.h>
37 #include <linux/io.h>
38 #include <linux/utsname.h>
39 #include <linux/rculist.h>
40 #include <linux/mm.h>
41
42 #include "qib.h"
43 #include "qib_common.h"
44
45 static unsigned int ib_qib_qp_table_size = 251;
46 module_param_named(qp_table_size, ib_qib_qp_table_size, uint, S_IRUGO);
47 MODULE_PARM_DESC(qp_table_size, "QP table size");
48
49 unsigned int ib_qib_lkey_table_size = 16;
50 module_param_named(lkey_table_size, ib_qib_lkey_table_size, uint,
51 S_IRUGO);
52 MODULE_PARM_DESC(lkey_table_size,
53 "LKEY table size in bits (2^n, 1 <= n <= 23)");
54
55 static unsigned int ib_qib_max_pds = 0xFFFF;
56 module_param_named(max_pds, ib_qib_max_pds, uint, S_IRUGO);
57 MODULE_PARM_DESC(max_pds,
58 "Maximum number of protection domains to support");
59
60 static unsigned int ib_qib_max_ahs = 0xFFFF;
61 module_param_named(max_ahs, ib_qib_max_ahs, uint, S_IRUGO);
62 MODULE_PARM_DESC(max_ahs, "Maximum number of address handles to support");
63
64 unsigned int ib_qib_max_cqes = 0x2FFFF;
65 module_param_named(max_cqes, ib_qib_max_cqes, uint, S_IRUGO);
66 MODULE_PARM_DESC(max_cqes,
67 "Maximum number of completion queue entries to support");
68
69 unsigned int ib_qib_max_cqs = 0x1FFFF;
70 module_param_named(max_cqs, ib_qib_max_cqs, uint, S_IRUGO);
71 MODULE_PARM_DESC(max_cqs, "Maximum number of completion queues to support");
72
73 unsigned int ib_qib_max_qp_wrs = 0x3FFF;
74 module_param_named(max_qp_wrs, ib_qib_max_qp_wrs, uint, S_IRUGO);
75 MODULE_PARM_DESC(max_qp_wrs, "Maximum number of QP WRs to support");
76
77 unsigned int ib_qib_max_qps = 16384;
78 module_param_named(max_qps, ib_qib_max_qps, uint, S_IRUGO);
79 MODULE_PARM_DESC(max_qps, "Maximum number of QPs to support");
80
81 unsigned int ib_qib_max_sges = 0x60;
82 module_param_named(max_sges, ib_qib_max_sges, uint, S_IRUGO);
83 MODULE_PARM_DESC(max_sges, "Maximum number of SGEs to support");
84
85 unsigned int ib_qib_max_mcast_grps = 16384;
86 module_param_named(max_mcast_grps, ib_qib_max_mcast_grps, uint, S_IRUGO);
87 MODULE_PARM_DESC(max_mcast_grps,
88 "Maximum number of multicast groups to support");
89
90 unsigned int ib_qib_max_mcast_qp_attached = 16;
91 module_param_named(max_mcast_qp_attached, ib_qib_max_mcast_qp_attached,
92 uint, S_IRUGO);
93 MODULE_PARM_DESC(max_mcast_qp_attached,
94 "Maximum number of attached QPs to support");
95
96 unsigned int ib_qib_max_srqs = 1024;
97 module_param_named(max_srqs, ib_qib_max_srqs, uint, S_IRUGO);
98 MODULE_PARM_DESC(max_srqs, "Maximum number of SRQs to support");
99
100 unsigned int ib_qib_max_srq_sges = 128;
101 module_param_named(max_srq_sges, ib_qib_max_srq_sges, uint, S_IRUGO);
102 MODULE_PARM_DESC(max_srq_sges, "Maximum number of SRQ SGEs to support");
103
104 unsigned int ib_qib_max_srq_wrs = 0x1FFFF;
105 module_param_named(max_srq_wrs, ib_qib_max_srq_wrs, uint, S_IRUGO);
106 MODULE_PARM_DESC(max_srq_wrs, "Maximum number of SRQ WRs support");
107
108 static unsigned int ib_qib_disable_sma;
109 module_param_named(disable_sma, ib_qib_disable_sma, uint, S_IWUSR | S_IRUGO);
110 MODULE_PARM_DESC(disable_sma, "Disable the SMA");
111
112 /*
113 * Note that it is OK to post send work requests in the SQE and ERR
114 * states; qib_do_send() will process them and generate error
115 * completions as per IB 1.2 C10-96.
116 */
117 const int ib_qib_state_ops[IB_QPS_ERR + 1] = {
118 [IB_QPS_RESET] = 0,
119 [IB_QPS_INIT] = QIB_POST_RECV_OK,
120 [IB_QPS_RTR] = QIB_POST_RECV_OK | QIB_PROCESS_RECV_OK,
121 [IB_QPS_RTS] = QIB_POST_RECV_OK | QIB_PROCESS_RECV_OK |
122 QIB_POST_SEND_OK | QIB_PROCESS_SEND_OK |
123 QIB_PROCESS_NEXT_SEND_OK,
124 [IB_QPS_SQD] = QIB_POST_RECV_OK | QIB_PROCESS_RECV_OK |
125 QIB_POST_SEND_OK | QIB_PROCESS_SEND_OK,
126 [IB_QPS_SQE] = QIB_POST_RECV_OK | QIB_PROCESS_RECV_OK |
127 QIB_POST_SEND_OK | QIB_FLUSH_SEND,
128 [IB_QPS_ERR] = QIB_POST_RECV_OK | QIB_FLUSH_RECV |
129 QIB_POST_SEND_OK | QIB_FLUSH_SEND,
130 };
131
132 struct qib_ucontext {
133 struct ib_ucontext ibucontext;
134 };
135
136 static inline struct qib_ucontext *to_iucontext(struct ib_ucontext
137 *ibucontext)
138 {
139 return container_of(ibucontext, struct qib_ucontext, ibucontext);
140 }
141
142 /*
143 * Translate ib_wr_opcode into ib_wc_opcode.
144 */
145 const enum ib_wc_opcode ib_qib_wc_opcode[] = {
146 [IB_WR_RDMA_WRITE] = IB_WC_RDMA_WRITE,
147 [IB_WR_RDMA_WRITE_WITH_IMM] = IB_WC_RDMA_WRITE,
148 [IB_WR_SEND] = IB_WC_SEND,
149 [IB_WR_SEND_WITH_IMM] = IB_WC_SEND,
150 [IB_WR_RDMA_READ] = IB_WC_RDMA_READ,
151 [IB_WR_ATOMIC_CMP_AND_SWP] = IB_WC_COMP_SWAP,
152 [IB_WR_ATOMIC_FETCH_AND_ADD] = IB_WC_FETCH_ADD
153 };
154
155 /*
156 * System image GUID.
157 */
158 __be64 ib_qib_sys_image_guid;
159
160 /**
161 * qib_copy_sge - copy data to SGE memory
162 * @ss: the SGE state
163 * @data: the data to copy
164 * @length: the length of the data
165 */
166 void qib_copy_sge(struct qib_sge_state *ss, void *data, u32 length, int release)
167 {
168 struct qib_sge *sge = &ss->sge;
169
170 while (length) {
171 u32 len = sge->length;
172
173 if (len > length)
174 len = length;
175 if (len > sge->sge_length)
176 len = sge->sge_length;
177 BUG_ON(len == 0);
178 memcpy(sge->vaddr, data, len);
179 sge->vaddr += len;
180 sge->length -= len;
181 sge->sge_length -= len;
182 if (sge->sge_length == 0) {
183 if (release)
184 atomic_dec(&sge->mr->refcount);
185 if (--ss->num_sge)
186 *sge = *ss->sg_list++;
187 } else if (sge->length == 0 && sge->mr->lkey) {
188 if (++sge->n >= QIB_SEGSZ) {
189 if (++sge->m >= sge->mr->mapsz)
190 break;
191 sge->n = 0;
192 }
193 sge->vaddr =
194 sge->mr->map[sge->m]->segs[sge->n].vaddr;
195 sge->length =
196 sge->mr->map[sge->m]->segs[sge->n].length;
197 }
198 data += len;
199 length -= len;
200 }
201 }
202
203 /**
204 * qib_skip_sge - skip over SGE memory - XXX almost dup of prev func
205 * @ss: the SGE state
206 * @length: the number of bytes to skip
207 */
208 void qib_skip_sge(struct qib_sge_state *ss, u32 length, int release)
209 {
210 struct qib_sge *sge = &ss->sge;
211
212 while (length) {
213 u32 len = sge->length;
214
215 if (len > length)
216 len = length;
217 if (len > sge->sge_length)
218 len = sge->sge_length;
219 BUG_ON(len == 0);
220 sge->vaddr += len;
221 sge->length -= len;
222 sge->sge_length -= len;
223 if (sge->sge_length == 0) {
224 if (release)
225 atomic_dec(&sge->mr->refcount);
226 if (--ss->num_sge)
227 *sge = *ss->sg_list++;
228 } else if (sge->length == 0 && sge->mr->lkey) {
229 if (++sge->n >= QIB_SEGSZ) {
230 if (++sge->m >= sge->mr->mapsz)
231 break;
232 sge->n = 0;
233 }
234 sge->vaddr =
235 sge->mr->map[sge->m]->segs[sge->n].vaddr;
236 sge->length =
237 sge->mr->map[sge->m]->segs[sge->n].length;
238 }
239 length -= len;
240 }
241 }
242
243 /*
244 * Count the number of DMA descriptors needed to send length bytes of data.
245 * Don't modify the qib_sge_state to get the count.
246 * Return zero if any of the segments is not aligned.
247 */
248 static u32 qib_count_sge(struct qib_sge_state *ss, u32 length)
249 {
250 struct qib_sge *sg_list = ss->sg_list;
251 struct qib_sge sge = ss->sge;
252 u8 num_sge = ss->num_sge;
253 u32 ndesc = 1; /* count the header */
254
255 while (length) {
256 u32 len = sge.length;
257
258 if (len > length)
259 len = length;
260 if (len > sge.sge_length)
261 len = sge.sge_length;
262 BUG_ON(len == 0);
263 if (((long) sge.vaddr & (sizeof(u32) - 1)) ||
264 (len != length && (len & (sizeof(u32) - 1)))) {
265 ndesc = 0;
266 break;
267 }
268 ndesc++;
269 sge.vaddr += len;
270 sge.length -= len;
271 sge.sge_length -= len;
272 if (sge.sge_length == 0) {
273 if (--num_sge)
274 sge = *sg_list++;
275 } else if (sge.length == 0 && sge.mr->lkey) {
276 if (++sge.n >= QIB_SEGSZ) {
277 if (++sge.m >= sge.mr->mapsz)
278 break;
279 sge.n = 0;
280 }
281 sge.vaddr =
282 sge.mr->map[sge.m]->segs[sge.n].vaddr;
283 sge.length =
284 sge.mr->map[sge.m]->segs[sge.n].length;
285 }
286 length -= len;
287 }
288 return ndesc;
289 }
290
291 /*
292 * Copy from the SGEs to the data buffer.
293 */
294 static void qib_copy_from_sge(void *data, struct qib_sge_state *ss, u32 length)
295 {
296 struct qib_sge *sge = &ss->sge;
297
298 while (length) {
299 u32 len = sge->length;
300
301 if (len > length)
302 len = length;
303 if (len > sge->sge_length)
304 len = sge->sge_length;
305 BUG_ON(len == 0);
306 memcpy(data, sge->vaddr, len);
307 sge->vaddr += len;
308 sge->length -= len;
309 sge->sge_length -= len;
310 if (sge->sge_length == 0) {
311 if (--ss->num_sge)
312 *sge = *ss->sg_list++;
313 } else if (sge->length == 0 && sge->mr->lkey) {
314 if (++sge->n >= QIB_SEGSZ) {
315 if (++sge->m >= sge->mr->mapsz)
316 break;
317 sge->n = 0;
318 }
319 sge->vaddr =
320 sge->mr->map[sge->m]->segs[sge->n].vaddr;
321 sge->length =
322 sge->mr->map[sge->m]->segs[sge->n].length;
323 }
324 data += len;
325 length -= len;
326 }
327 }
328
329 /**
330 * qib_post_one_send - post one RC, UC, or UD send work request
331 * @qp: the QP to post on
332 * @wr: the work request to send
333 */
334 static int qib_post_one_send(struct qib_qp *qp, struct ib_send_wr *wr)
335 {
336 struct qib_swqe *wqe;
337 u32 next;
338 int i;
339 int j;
340 int acc;
341 int ret;
342 unsigned long flags;
343 struct qib_lkey_table *rkt;
344 struct qib_pd *pd;
345
346 spin_lock_irqsave(&qp->s_lock, flags);
347
348 /* Check that state is OK to post send. */
349 if (unlikely(!(ib_qib_state_ops[qp->state] & QIB_POST_SEND_OK)))
350 goto bail_inval;
351
352 /* IB spec says that num_sge == 0 is OK. */
353 if (wr->num_sge > qp->s_max_sge)
354 goto bail_inval;
355
356 /*
357 * Don't allow RDMA reads or atomic operations on UC or
358 * undefined operations.
359 * Make sure buffer is large enough to hold the result for atomics.
360 */
361 if (wr->opcode == IB_WR_FAST_REG_MR) {
362 if (qib_fast_reg_mr(qp, wr))
363 goto bail_inval;
364 } else if (qp->ibqp.qp_type == IB_QPT_UC) {
365 if ((unsigned) wr->opcode >= IB_WR_RDMA_READ)
366 goto bail_inval;
367 } else if (qp->ibqp.qp_type != IB_QPT_RC) {
368 /* Check IB_QPT_SMI, IB_QPT_GSI, IB_QPT_UD opcode */
369 if (wr->opcode != IB_WR_SEND &&
370 wr->opcode != IB_WR_SEND_WITH_IMM)
371 goto bail_inval;
372 /* Check UD destination address PD */
373 if (qp->ibqp.pd != wr->wr.ud.ah->pd)
374 goto bail_inval;
375 } else if ((unsigned) wr->opcode > IB_WR_ATOMIC_FETCH_AND_ADD)
376 goto bail_inval;
377 else if (wr->opcode >= IB_WR_ATOMIC_CMP_AND_SWP &&
378 (wr->num_sge == 0 ||
379 wr->sg_list[0].length < sizeof(u64) ||
380 wr->sg_list[0].addr & (sizeof(u64) - 1)))
381 goto bail_inval;
382 else if (wr->opcode >= IB_WR_RDMA_READ && !qp->s_max_rd_atomic)
383 goto bail_inval;
384
385 next = qp->s_head + 1;
386 if (next >= qp->s_size)
387 next = 0;
388 if (next == qp->s_last) {
389 ret = -ENOMEM;
390 goto bail;
391 }
392
393 rkt = &to_idev(qp->ibqp.device)->lk_table;
394 pd = to_ipd(qp->ibqp.pd);
395 wqe = get_swqe_ptr(qp, qp->s_head);
396 wqe->wr = *wr;
397 wqe->length = 0;
398 j = 0;
399 if (wr->num_sge) {
400 acc = wr->opcode >= IB_WR_RDMA_READ ?
401 IB_ACCESS_LOCAL_WRITE : 0;
402 for (i = 0; i < wr->num_sge; i++) {
403 u32 length = wr->sg_list[i].length;
404 int ok;
405
406 if (length == 0)
407 continue;
408 ok = qib_lkey_ok(rkt, pd, &wqe->sg_list[j],
409 &wr->sg_list[i], acc);
410 if (!ok)
411 goto bail_inval_free;
412 wqe->length += length;
413 j++;
414 }
415 wqe->wr.num_sge = j;
416 }
417 if (qp->ibqp.qp_type == IB_QPT_UC ||
418 qp->ibqp.qp_type == IB_QPT_RC) {
419 if (wqe->length > 0x80000000U)
420 goto bail_inval_free;
421 } else if (wqe->length > (dd_from_ibdev(qp->ibqp.device)->pport +
422 qp->port_num - 1)->ibmtu)
423 goto bail_inval_free;
424 else
425 atomic_inc(&to_iah(wr->wr.ud.ah)->refcount);
426 wqe->ssn = qp->s_ssn++;
427 qp->s_head = next;
428
429 ret = 0;
430 goto bail;
431
432 bail_inval_free:
433 while (j) {
434 struct qib_sge *sge = &wqe->sg_list[--j];
435
436 atomic_dec(&sge->mr->refcount);
437 }
438 bail_inval:
439 ret = -EINVAL;
440 bail:
441 spin_unlock_irqrestore(&qp->s_lock, flags);
442 return ret;
443 }
444
445 /**
446 * qib_post_send - post a send on a QP
447 * @ibqp: the QP to post the send on
448 * @wr: the list of work requests to post
449 * @bad_wr: the first bad WR is put here
450 *
451 * This may be called from interrupt context.
452 */
453 static int qib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
454 struct ib_send_wr **bad_wr)
455 {
456 struct qib_qp *qp = to_iqp(ibqp);
457 int err = 0;
458
459 for (; wr; wr = wr->next) {
460 err = qib_post_one_send(qp, wr);
461 if (err) {
462 *bad_wr = wr;
463 goto bail;
464 }
465 }
466
467 /* Try to do the send work in the caller's context. */
468 qib_do_send(&qp->s_work);
469
470 bail:
471 return err;
472 }
473
474 /**
475 * qib_post_receive - post a receive on a QP
476 * @ibqp: the QP to post the receive on
477 * @wr: the WR to post
478 * @bad_wr: the first bad WR is put here
479 *
480 * This may be called from interrupt context.
481 */
482 static int qib_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
483 struct ib_recv_wr **bad_wr)
484 {
485 struct qib_qp *qp = to_iqp(ibqp);
486 struct qib_rwq *wq = qp->r_rq.wq;
487 unsigned long flags;
488 int ret;
489
490 /* Check that state is OK to post receive. */
491 if (!(ib_qib_state_ops[qp->state] & QIB_POST_RECV_OK) || !wq) {
492 *bad_wr = wr;
493 ret = -EINVAL;
494 goto bail;
495 }
496
497 for (; wr; wr = wr->next) {
498 struct qib_rwqe *wqe;
499 u32 next;
500 int i;
501
502 if ((unsigned) wr->num_sge > qp->r_rq.max_sge) {
503 *bad_wr = wr;
504 ret = -EINVAL;
505 goto bail;
506 }
507
508 spin_lock_irqsave(&qp->r_rq.lock, flags);
509 next = wq->head + 1;
510 if (next >= qp->r_rq.size)
511 next = 0;
512 if (next == wq->tail) {
513 spin_unlock_irqrestore(&qp->r_rq.lock, flags);
514 *bad_wr = wr;
515 ret = -ENOMEM;
516 goto bail;
517 }
518
519 wqe = get_rwqe_ptr(&qp->r_rq, wq->head);
520 wqe->wr_id = wr->wr_id;
521 wqe->num_sge = wr->num_sge;
522 for (i = 0; i < wr->num_sge; i++)
523 wqe->sg_list[i] = wr->sg_list[i];
524 /* Make sure queue entry is written before the head index. */
525 smp_wmb();
526 wq->head = next;
527 spin_unlock_irqrestore(&qp->r_rq.lock, flags);
528 }
529 ret = 0;
530
531 bail:
532 return ret;
533 }
534
535 /**
536 * qib_qp_rcv - processing an incoming packet on a QP
537 * @rcd: the context pointer
538 * @hdr: the packet header
539 * @has_grh: true if the packet has a GRH
540 * @data: the packet data
541 * @tlen: the packet length
542 * @qp: the QP the packet came on
543 *
544 * This is called from qib_ib_rcv() to process an incoming packet
545 * for the given QP.
546 * Called at interrupt level.
547 */
548 static void qib_qp_rcv(struct qib_ctxtdata *rcd, struct qib_ib_header *hdr,
549 int has_grh, void *data, u32 tlen, struct qib_qp *qp)
550 {
551 struct qib_ibport *ibp = &rcd->ppd->ibport_data;
552
553 spin_lock(&qp->r_lock);
554
555 /* Check for valid receive state. */
556 if (!(ib_qib_state_ops[qp->state] & QIB_PROCESS_RECV_OK)) {
557 ibp->n_pkt_drops++;
558 goto unlock;
559 }
560
561 switch (qp->ibqp.qp_type) {
562 case IB_QPT_SMI:
563 case IB_QPT_GSI:
564 if (ib_qib_disable_sma)
565 break;
566 /* FALLTHROUGH */
567 case IB_QPT_UD:
568 qib_ud_rcv(ibp, hdr, has_grh, data, tlen, qp);
569 break;
570
571 case IB_QPT_RC:
572 qib_rc_rcv(rcd, hdr, has_grh, data, tlen, qp);
573 break;
574
575 case IB_QPT_UC:
576 qib_uc_rcv(ibp, hdr, has_grh, data, tlen, qp);
577 break;
578
579 default:
580 break;
581 }
582
583 unlock:
584 spin_unlock(&qp->r_lock);
585 }
586
587 /**
588 * qib_ib_rcv - process an incoming packet
589 * @rcd: the context pointer
590 * @rhdr: the header of the packet
591 * @data: the packet payload
592 * @tlen: the packet length
593 *
594 * This is called from qib_kreceive() to process an incoming packet at
595 * interrupt level. Tlen is the length of the header + data + CRC in bytes.
596 */
597 void qib_ib_rcv(struct qib_ctxtdata *rcd, void *rhdr, void *data, u32 tlen)
598 {
599 struct qib_pportdata *ppd = rcd->ppd;
600 struct qib_ibport *ibp = &ppd->ibport_data;
601 struct qib_ib_header *hdr = rhdr;
602 struct qib_other_headers *ohdr;
603 struct qib_qp *qp;
604 u32 qp_num;
605 int lnh;
606 u8 opcode;
607 u16 lid;
608
609 /* 24 == LRH+BTH+CRC */
610 if (unlikely(tlen < 24))
611 goto drop;
612
613 /* Check for a valid destination LID (see ch. 7.11.1). */
614 lid = be16_to_cpu(hdr->lrh[1]);
615 if (lid < QIB_MULTICAST_LID_BASE) {
616 lid &= ~((1 << ppd->lmc) - 1);
617 if (unlikely(lid != ppd->lid))
618 goto drop;
619 }
620
621 /* Check for GRH */
622 lnh = be16_to_cpu(hdr->lrh[0]) & 3;
623 if (lnh == QIB_LRH_BTH)
624 ohdr = &hdr->u.oth;
625 else if (lnh == QIB_LRH_GRH) {
626 u32 vtf;
627
628 ohdr = &hdr->u.l.oth;
629 if (hdr->u.l.grh.next_hdr != IB_GRH_NEXT_HDR)
630 goto drop;
631 vtf = be32_to_cpu(hdr->u.l.grh.version_tclass_flow);
632 if ((vtf >> IB_GRH_VERSION_SHIFT) != IB_GRH_VERSION)
633 goto drop;
634 } else
635 goto drop;
636
637 opcode = be32_to_cpu(ohdr->bth[0]) >> 24;
638 ibp->opstats[opcode & 0x7f].n_bytes += tlen;
639 ibp->opstats[opcode & 0x7f].n_packets++;
640
641 /* Get the destination QP number. */
642 qp_num = be32_to_cpu(ohdr->bth[1]) & QIB_QPN_MASK;
643 if (qp_num == QIB_MULTICAST_QPN) {
644 struct qib_mcast *mcast;
645 struct qib_mcast_qp *p;
646
647 if (lnh != QIB_LRH_GRH)
648 goto drop;
649 mcast = qib_mcast_find(ibp, &hdr->u.l.grh.dgid);
650 if (mcast == NULL)
651 goto drop;
652 ibp->n_multicast_rcv++;
653 list_for_each_entry_rcu(p, &mcast->qp_list, list)
654 qib_qp_rcv(rcd, hdr, 1, data, tlen, p->qp);
655 /*
656 * Notify qib_multicast_detach() if it is waiting for us
657 * to finish.
658 */
659 if (atomic_dec_return(&mcast->refcount) <= 1)
660 wake_up(&mcast->wait);
661 } else {
662 qp = qib_lookup_qpn(ibp, qp_num);
663 if (!qp)
664 goto drop;
665 ibp->n_unicast_rcv++;
666 qib_qp_rcv(rcd, hdr, lnh == QIB_LRH_GRH, data, tlen, qp);
667 /*
668 * Notify qib_destroy_qp() if it is waiting
669 * for us to finish.
670 */
671 if (atomic_dec_and_test(&qp->refcount))
672 wake_up(&qp->wait);
673 }
674 return;
675
676 drop:
677 ibp->n_pkt_drops++;
678 }
679
680 /*
681 * This is called from a timer to check for QPs
682 * which need kernel memory in order to send a packet.
683 */
684 static void mem_timer(unsigned long data)
685 {
686 struct qib_ibdev *dev = (struct qib_ibdev *) data;
687 struct list_head *list = &dev->memwait;
688 struct qib_qp *qp = NULL;
689 unsigned long flags;
690
691 spin_lock_irqsave(&dev->pending_lock, flags);
692 if (!list_empty(list)) {
693 qp = list_entry(list->next, struct qib_qp, iowait);
694 list_del_init(&qp->iowait);
695 atomic_inc(&qp->refcount);
696 if (!list_empty(list))
697 mod_timer(&dev->mem_timer, jiffies + 1);
698 }
699 spin_unlock_irqrestore(&dev->pending_lock, flags);
700
701 if (qp) {
702 spin_lock_irqsave(&qp->s_lock, flags);
703 if (qp->s_flags & QIB_S_WAIT_KMEM) {
704 qp->s_flags &= ~QIB_S_WAIT_KMEM;
705 qib_schedule_send(qp);
706 }
707 spin_unlock_irqrestore(&qp->s_lock, flags);
708 if (atomic_dec_and_test(&qp->refcount))
709 wake_up(&qp->wait);
710 }
711 }
712
713 static void update_sge(struct qib_sge_state *ss, u32 length)
714 {
715 struct qib_sge *sge = &ss->sge;
716
717 sge->vaddr += length;
718 sge->length -= length;
719 sge->sge_length -= length;
720 if (sge->sge_length == 0) {
721 if (--ss->num_sge)
722 *sge = *ss->sg_list++;
723 } else if (sge->length == 0 && sge->mr->lkey) {
724 if (++sge->n >= QIB_SEGSZ) {
725 if (++sge->m >= sge->mr->mapsz)
726 return;
727 sge->n = 0;
728 }
729 sge->vaddr = sge->mr->map[sge->m]->segs[sge->n].vaddr;
730 sge->length = sge->mr->map[sge->m]->segs[sge->n].length;
731 }
732 }
733
734 #ifdef __LITTLE_ENDIAN
735 static inline u32 get_upper_bits(u32 data, u32 shift)
736 {
737 return data >> shift;
738 }
739
740 static inline u32 set_upper_bits(u32 data, u32 shift)
741 {
742 return data << shift;
743 }
744
745 static inline u32 clear_upper_bytes(u32 data, u32 n, u32 off)
746 {
747 data <<= ((sizeof(u32) - n) * BITS_PER_BYTE);
748 data >>= ((sizeof(u32) - n - off) * BITS_PER_BYTE);
749 return data;
750 }
751 #else
752 static inline u32 get_upper_bits(u32 data, u32 shift)
753 {
754 return data << shift;
755 }
756
757 static inline u32 set_upper_bits(u32 data, u32 shift)
758 {
759 return data >> shift;
760 }
761
762 static inline u32 clear_upper_bytes(u32 data, u32 n, u32 off)
763 {
764 data >>= ((sizeof(u32) - n) * BITS_PER_BYTE);
765 data <<= ((sizeof(u32) - n - off) * BITS_PER_BYTE);
766 return data;
767 }
768 #endif
769
770 static void copy_io(u32 __iomem *piobuf, struct qib_sge_state *ss,
771 u32 length, unsigned flush_wc)
772 {
773 u32 extra = 0;
774 u32 data = 0;
775 u32 last;
776
777 while (1) {
778 u32 len = ss->sge.length;
779 u32 off;
780
781 if (len > length)
782 len = length;
783 if (len > ss->sge.sge_length)
784 len = ss->sge.sge_length;
785 BUG_ON(len == 0);
786 /* If the source address is not aligned, try to align it. */
787 off = (unsigned long)ss->sge.vaddr & (sizeof(u32) - 1);
788 if (off) {
789 u32 *addr = (u32 *)((unsigned long)ss->sge.vaddr &
790 ~(sizeof(u32) - 1));
791 u32 v = get_upper_bits(*addr, off * BITS_PER_BYTE);
792 u32 y;
793
794 y = sizeof(u32) - off;
795 if (len > y)
796 len = y;
797 if (len + extra >= sizeof(u32)) {
798 data |= set_upper_bits(v, extra *
799 BITS_PER_BYTE);
800 len = sizeof(u32) - extra;
801 if (len == length) {
802 last = data;
803 break;
804 }
805 __raw_writel(data, piobuf);
806 piobuf++;
807 extra = 0;
808 data = 0;
809 } else {
810 /* Clear unused upper bytes */
811 data |= clear_upper_bytes(v, len, extra);
812 if (len == length) {
813 last = data;
814 break;
815 }
816 extra += len;
817 }
818 } else if (extra) {
819 /* Source address is aligned. */
820 u32 *addr = (u32 *) ss->sge.vaddr;
821 int shift = extra * BITS_PER_BYTE;
822 int ushift = 32 - shift;
823 u32 l = len;
824
825 while (l >= sizeof(u32)) {
826 u32 v = *addr;
827
828 data |= set_upper_bits(v, shift);
829 __raw_writel(data, piobuf);
830 data = get_upper_bits(v, ushift);
831 piobuf++;
832 addr++;
833 l -= sizeof(u32);
834 }
835 /*
836 * We still have 'extra' number of bytes leftover.
837 */
838 if (l) {
839 u32 v = *addr;
840
841 if (l + extra >= sizeof(u32)) {
842 data |= set_upper_bits(v, shift);
843 len -= l + extra - sizeof(u32);
844 if (len == length) {
845 last = data;
846 break;
847 }
848 __raw_writel(data, piobuf);
849 piobuf++;
850 extra = 0;
851 data = 0;
852 } else {
853 /* Clear unused upper bytes */
854 data |= clear_upper_bytes(v, l, extra);
855 if (len == length) {
856 last = data;
857 break;
858 }
859 extra += l;
860 }
861 } else if (len == length) {
862 last = data;
863 break;
864 }
865 } else if (len == length) {
866 u32 w;
867
868 /*
869 * Need to round up for the last dword in the
870 * packet.
871 */
872 w = (len + 3) >> 2;
873 qib_pio_copy(piobuf, ss->sge.vaddr, w - 1);
874 piobuf += w - 1;
875 last = ((u32 *) ss->sge.vaddr)[w - 1];
876 break;
877 } else {
878 u32 w = len >> 2;
879
880 qib_pio_copy(piobuf, ss->sge.vaddr, w);
881 piobuf += w;
882
883 extra = len & (sizeof(u32) - 1);
884 if (extra) {
885 u32 v = ((u32 *) ss->sge.vaddr)[w];
886
887 /* Clear unused upper bytes */
888 data = clear_upper_bytes(v, extra, 0);
889 }
890 }
891 update_sge(ss, len);
892 length -= len;
893 }
894 /* Update address before sending packet. */
895 update_sge(ss, length);
896 if (flush_wc) {
897 /* must flush early everything before trigger word */
898 qib_flush_wc();
899 __raw_writel(last, piobuf);
900 /* be sure trigger word is written */
901 qib_flush_wc();
902 } else
903 __raw_writel(last, piobuf);
904 }
905
906 static struct qib_verbs_txreq *get_txreq(struct qib_ibdev *dev,
907 struct qib_qp *qp, int *retp)
908 {
909 struct qib_verbs_txreq *tx;
910 unsigned long flags;
911
912 spin_lock_irqsave(&qp->s_lock, flags);
913 spin_lock(&dev->pending_lock);
914
915 if (!list_empty(&dev->txreq_free)) {
916 struct list_head *l = dev->txreq_free.next;
917
918 list_del(l);
919 tx = list_entry(l, struct qib_verbs_txreq, txreq.list);
920 *retp = 0;
921 } else {
922 if (ib_qib_state_ops[qp->state] & QIB_PROCESS_RECV_OK &&
923 list_empty(&qp->iowait)) {
924 dev->n_txwait++;
925 qp->s_flags |= QIB_S_WAIT_TX;
926 list_add_tail(&qp->iowait, &dev->txwait);
927 }
928 tx = NULL;
929 qp->s_flags &= ~QIB_S_BUSY;
930 *retp = -EBUSY;
931 }
932
933 spin_unlock(&dev->pending_lock);
934 spin_unlock_irqrestore(&qp->s_lock, flags);
935
936 return tx;
937 }
938
939 void qib_put_txreq(struct qib_verbs_txreq *tx)
940 {
941 struct qib_ibdev *dev;
942 struct qib_qp *qp;
943 unsigned long flags;
944
945 qp = tx->qp;
946 dev = to_idev(qp->ibqp.device);
947
948 if (atomic_dec_and_test(&qp->refcount))
949 wake_up(&qp->wait);
950 if (tx->mr) {
951 atomic_dec(&tx->mr->refcount);
952 tx->mr = NULL;
953 }
954 if (tx->txreq.flags & QIB_SDMA_TXREQ_F_FREEBUF) {
955 tx->txreq.flags &= ~QIB_SDMA_TXREQ_F_FREEBUF;
956 dma_unmap_single(&dd_from_dev(dev)->pcidev->dev,
957 tx->txreq.addr, tx->hdr_dwords << 2,
958 DMA_TO_DEVICE);
959 kfree(tx->align_buf);
960 }
961
962 spin_lock_irqsave(&dev->pending_lock, flags);
963
964 /* Put struct back on free list */
965 list_add(&tx->txreq.list, &dev->txreq_free);
966
967 if (!list_empty(&dev->txwait)) {
968 /* Wake up first QP wanting a free struct */
969 qp = list_entry(dev->txwait.next, struct qib_qp, iowait);
970 list_del_init(&qp->iowait);
971 atomic_inc(&qp->refcount);
972 spin_unlock_irqrestore(&dev->pending_lock, flags);
973
974 spin_lock_irqsave(&qp->s_lock, flags);
975 if (qp->s_flags & QIB_S_WAIT_TX) {
976 qp->s_flags &= ~QIB_S_WAIT_TX;
977 qib_schedule_send(qp);
978 }
979 spin_unlock_irqrestore(&qp->s_lock, flags);
980
981 if (atomic_dec_and_test(&qp->refcount))
982 wake_up(&qp->wait);
983 } else
984 spin_unlock_irqrestore(&dev->pending_lock, flags);
985 }
986
987 /*
988 * This is called when there are send DMA descriptors that might be
989 * available.
990 *
991 * This is called with ppd->sdma_lock held.
992 */
993 void qib_verbs_sdma_desc_avail(struct qib_pportdata *ppd, unsigned avail)
994 {
995 struct qib_qp *qp, *nqp;
996 struct qib_qp *qps[20];
997 struct qib_ibdev *dev;
998 unsigned i, n;
999
1000 n = 0;
1001 dev = &ppd->dd->verbs_dev;
1002 spin_lock(&dev->pending_lock);
1003
1004 /* Search wait list for first QP wanting DMA descriptors. */
1005 list_for_each_entry_safe(qp, nqp, &dev->dmawait, iowait) {
1006 if (qp->port_num != ppd->port)
1007 continue;
1008 if (n == ARRAY_SIZE(qps))
1009 break;
1010 if (qp->s_tx->txreq.sg_count > avail)
1011 break;
1012 avail -= qp->s_tx->txreq.sg_count;
1013 list_del_init(&qp->iowait);
1014 atomic_inc(&qp->refcount);
1015 qps[n++] = qp;
1016 }
1017
1018 spin_unlock(&dev->pending_lock);
1019
1020 for (i = 0; i < n; i++) {
1021 qp = qps[i];
1022 spin_lock(&qp->s_lock);
1023 if (qp->s_flags & QIB_S_WAIT_DMA_DESC) {
1024 qp->s_flags &= ~QIB_S_WAIT_DMA_DESC;
1025 qib_schedule_send(qp);
1026 }
1027 spin_unlock(&qp->s_lock);
1028 if (atomic_dec_and_test(&qp->refcount))
1029 wake_up(&qp->wait);
1030 }
1031 }
1032
1033 /*
1034 * This is called with ppd->sdma_lock held.
1035 */
1036 static void sdma_complete(struct qib_sdma_txreq *cookie, int status)
1037 {
1038 struct qib_verbs_txreq *tx =
1039 container_of(cookie, struct qib_verbs_txreq, txreq);
1040 struct qib_qp *qp = tx->qp;
1041
1042 spin_lock(&qp->s_lock);
1043 if (tx->wqe)
1044 qib_send_complete(qp, tx->wqe, IB_WC_SUCCESS);
1045 else if (qp->ibqp.qp_type == IB_QPT_RC) {
1046 struct qib_ib_header *hdr;
1047
1048 if (tx->txreq.flags & QIB_SDMA_TXREQ_F_FREEBUF)
1049 hdr = &tx->align_buf->hdr;
1050 else {
1051 struct qib_ibdev *dev = to_idev(qp->ibqp.device);
1052
1053 hdr = &dev->pio_hdrs[tx->hdr_inx].hdr;
1054 }
1055 qib_rc_send_complete(qp, hdr);
1056 }
1057 if (atomic_dec_and_test(&qp->s_dma_busy)) {
1058 if (qp->state == IB_QPS_RESET)
1059 wake_up(&qp->wait_dma);
1060 else if (qp->s_flags & QIB_S_WAIT_DMA) {
1061 qp->s_flags &= ~QIB_S_WAIT_DMA;
1062 qib_schedule_send(qp);
1063 }
1064 }
1065 spin_unlock(&qp->s_lock);
1066
1067 qib_put_txreq(tx);
1068 }
1069
1070 static int wait_kmem(struct qib_ibdev *dev, struct qib_qp *qp)
1071 {
1072 unsigned long flags;
1073 int ret = 0;
1074
1075 spin_lock_irqsave(&qp->s_lock, flags);
1076 if (ib_qib_state_ops[qp->state] & QIB_PROCESS_RECV_OK) {
1077 spin_lock(&dev->pending_lock);
1078 if (list_empty(&qp->iowait)) {
1079 if (list_empty(&dev->memwait))
1080 mod_timer(&dev->mem_timer, jiffies + 1);
1081 qp->s_flags |= QIB_S_WAIT_KMEM;
1082 list_add_tail(&qp->iowait, &dev->memwait);
1083 }
1084 spin_unlock(&dev->pending_lock);
1085 qp->s_flags &= ~QIB_S_BUSY;
1086 ret = -EBUSY;
1087 }
1088 spin_unlock_irqrestore(&qp->s_lock, flags);
1089
1090 return ret;
1091 }
1092
1093 static int qib_verbs_send_dma(struct qib_qp *qp, struct qib_ib_header *hdr,
1094 u32 hdrwords, struct qib_sge_state *ss, u32 len,
1095 u32 plen, u32 dwords)
1096 {
1097 struct qib_ibdev *dev = to_idev(qp->ibqp.device);
1098 struct qib_devdata *dd = dd_from_dev(dev);
1099 struct qib_ibport *ibp = to_iport(qp->ibqp.device, qp->port_num);
1100 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1101 struct qib_verbs_txreq *tx;
1102 struct qib_pio_header *phdr;
1103 u32 control;
1104 u32 ndesc;
1105 int ret;
1106
1107 tx = qp->s_tx;
1108 if (tx) {
1109 qp->s_tx = NULL;
1110 /* resend previously constructed packet */
1111 ret = qib_sdma_verbs_send(ppd, tx->ss, tx->dwords, tx);
1112 goto bail;
1113 }
1114
1115 tx = get_txreq(dev, qp, &ret);
1116 if (!tx)
1117 goto bail;
1118
1119 control = dd->f_setpbc_control(ppd, plen, qp->s_srate,
1120 be16_to_cpu(hdr->lrh[0]) >> 12);
1121 tx->qp = qp;
1122 atomic_inc(&qp->refcount);
1123 tx->wqe = qp->s_wqe;
1124 tx->mr = qp->s_rdma_mr;
1125 if (qp->s_rdma_mr)
1126 qp->s_rdma_mr = NULL;
1127 tx->txreq.callback = sdma_complete;
1128 if (dd->flags & QIB_HAS_SDMA_TIMEOUT)
1129 tx->txreq.flags = QIB_SDMA_TXREQ_F_HEADTOHOST;
1130 else
1131 tx->txreq.flags = QIB_SDMA_TXREQ_F_INTREQ;
1132 if (plen + 1 > dd->piosize2kmax_dwords)
1133 tx->txreq.flags |= QIB_SDMA_TXREQ_F_USELARGEBUF;
1134
1135 if (len) {
1136 /*
1137 * Don't try to DMA if it takes more descriptors than
1138 * the queue holds.
1139 */
1140 ndesc = qib_count_sge(ss, len);
1141 if (ndesc >= ppd->sdma_descq_cnt)
1142 ndesc = 0;
1143 } else
1144 ndesc = 1;
1145 if (ndesc) {
1146 phdr = &dev->pio_hdrs[tx->hdr_inx];
1147 phdr->pbc[0] = cpu_to_le32(plen);
1148 phdr->pbc[1] = cpu_to_le32(control);
1149 memcpy(&phdr->hdr, hdr, hdrwords << 2);
1150 tx->txreq.flags |= QIB_SDMA_TXREQ_F_FREEDESC;
1151 tx->txreq.sg_count = ndesc;
1152 tx->txreq.addr = dev->pio_hdrs_phys +
1153 tx->hdr_inx * sizeof(struct qib_pio_header);
1154 tx->hdr_dwords = hdrwords + 2; /* add PBC length */
1155 ret = qib_sdma_verbs_send(ppd, ss, dwords, tx);
1156 goto bail;
1157 }
1158
1159 /* Allocate a buffer and copy the header and payload to it. */
1160 tx->hdr_dwords = plen + 1;
1161 phdr = kmalloc(tx->hdr_dwords << 2, GFP_ATOMIC);
1162 if (!phdr)
1163 goto err_tx;
1164 phdr->pbc[0] = cpu_to_le32(plen);
1165 phdr->pbc[1] = cpu_to_le32(control);
1166 memcpy(&phdr->hdr, hdr, hdrwords << 2);
1167 qib_copy_from_sge((u32 *) &phdr->hdr + hdrwords, ss, len);
1168
1169 tx->txreq.addr = dma_map_single(&dd->pcidev->dev, phdr,
1170 tx->hdr_dwords << 2, DMA_TO_DEVICE);
1171 if (dma_mapping_error(&dd->pcidev->dev, tx->txreq.addr))
1172 goto map_err;
1173 tx->align_buf = phdr;
1174 tx->txreq.flags |= QIB_SDMA_TXREQ_F_FREEBUF;
1175 tx->txreq.sg_count = 1;
1176 ret = qib_sdma_verbs_send(ppd, NULL, 0, tx);
1177 goto unaligned;
1178
1179 map_err:
1180 kfree(phdr);
1181 err_tx:
1182 qib_put_txreq(tx);
1183 ret = wait_kmem(dev, qp);
1184 unaligned:
1185 ibp->n_unaligned++;
1186 bail:
1187 return ret;
1188 }
1189
1190 /*
1191 * If we are now in the error state, return zero to flush the
1192 * send work request.
1193 */
1194 static int no_bufs_available(struct qib_qp *qp)
1195 {
1196 struct qib_ibdev *dev = to_idev(qp->ibqp.device);
1197 struct qib_devdata *dd;
1198 unsigned long flags;
1199 int ret = 0;
1200
1201 /*
1202 * Note that as soon as want_buffer() is called and
1203 * possibly before it returns, qib_ib_piobufavail()
1204 * could be called. Therefore, put QP on the I/O wait list before
1205 * enabling the PIO avail interrupt.
1206 */
1207 spin_lock_irqsave(&qp->s_lock, flags);
1208 if (ib_qib_state_ops[qp->state] & QIB_PROCESS_RECV_OK) {
1209 spin_lock(&dev->pending_lock);
1210 if (list_empty(&qp->iowait)) {
1211 dev->n_piowait++;
1212 qp->s_flags |= QIB_S_WAIT_PIO;
1213 list_add_tail(&qp->iowait, &dev->piowait);
1214 dd = dd_from_dev(dev);
1215 dd->f_wantpiobuf_intr(dd, 1);
1216 }
1217 spin_unlock(&dev->pending_lock);
1218 qp->s_flags &= ~QIB_S_BUSY;
1219 ret = -EBUSY;
1220 }
1221 spin_unlock_irqrestore(&qp->s_lock, flags);
1222 return ret;
1223 }
1224
1225 static int qib_verbs_send_pio(struct qib_qp *qp, struct qib_ib_header *ibhdr,
1226 u32 hdrwords, struct qib_sge_state *ss, u32 len,
1227 u32 plen, u32 dwords)
1228 {
1229 struct qib_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1230 struct qib_pportdata *ppd = dd->pport + qp->port_num - 1;
1231 u32 *hdr = (u32 *) ibhdr;
1232 u32 __iomem *piobuf_orig;
1233 u32 __iomem *piobuf;
1234 u64 pbc;
1235 unsigned long flags;
1236 unsigned flush_wc;
1237 u32 control;
1238 u32 pbufn;
1239
1240 control = dd->f_setpbc_control(ppd, plen, qp->s_srate,
1241 be16_to_cpu(ibhdr->lrh[0]) >> 12);
1242 pbc = ((u64) control << 32) | plen;
1243 piobuf = dd->f_getsendbuf(ppd, pbc, &pbufn);
1244 if (unlikely(piobuf == NULL))
1245 return no_bufs_available(qp);
1246
1247 /*
1248 * Write the pbc.
1249 * We have to flush after the PBC for correctness on some cpus
1250 * or WC buffer can be written out of order.
1251 */
1252 writeq(pbc, piobuf);
1253 piobuf_orig = piobuf;
1254 piobuf += 2;
1255
1256 flush_wc = dd->flags & QIB_PIO_FLUSH_WC;
1257 if (len == 0) {
1258 /*
1259 * If there is just the header portion, must flush before
1260 * writing last word of header for correctness, and after
1261 * the last header word (trigger word).
1262 */
1263 if (flush_wc) {
1264 qib_flush_wc();
1265 qib_pio_copy(piobuf, hdr, hdrwords - 1);
1266 qib_flush_wc();
1267 __raw_writel(hdr[hdrwords - 1], piobuf + hdrwords - 1);
1268 qib_flush_wc();
1269 } else
1270 qib_pio_copy(piobuf, hdr, hdrwords);
1271 goto done;
1272 }
1273
1274 if (flush_wc)
1275 qib_flush_wc();
1276 qib_pio_copy(piobuf, hdr, hdrwords);
1277 piobuf += hdrwords;
1278
1279 /* The common case is aligned and contained in one segment. */
1280 if (likely(ss->num_sge == 1 && len <= ss->sge.length &&
1281 !((unsigned long)ss->sge.vaddr & (sizeof(u32) - 1)))) {
1282 u32 *addr = (u32 *) ss->sge.vaddr;
1283
1284 /* Update address before sending packet. */
1285 update_sge(ss, len);
1286 if (flush_wc) {
1287 qib_pio_copy(piobuf, addr, dwords - 1);
1288 /* must flush early everything before trigger word */
1289 qib_flush_wc();
1290 __raw_writel(addr[dwords - 1], piobuf + dwords - 1);
1291 /* be sure trigger word is written */
1292 qib_flush_wc();
1293 } else
1294 qib_pio_copy(piobuf, addr, dwords);
1295 goto done;
1296 }
1297 copy_io(piobuf, ss, len, flush_wc);
1298 done:
1299 if (dd->flags & QIB_USE_SPCL_TRIG) {
1300 u32 spcl_off = (pbufn >= dd->piobcnt2k) ? 2047 : 1023;
1301 qib_flush_wc();
1302 __raw_writel(0xaebecede, piobuf_orig + spcl_off);
1303 }
1304 qib_sendbuf_done(dd, pbufn);
1305 if (qp->s_rdma_mr) {
1306 atomic_dec(&qp->s_rdma_mr->refcount);
1307 qp->s_rdma_mr = NULL;
1308 }
1309 if (qp->s_wqe) {
1310 spin_lock_irqsave(&qp->s_lock, flags);
1311 qib_send_complete(qp, qp->s_wqe, IB_WC_SUCCESS);
1312 spin_unlock_irqrestore(&qp->s_lock, flags);
1313 } else if (qp->ibqp.qp_type == IB_QPT_RC) {
1314 spin_lock_irqsave(&qp->s_lock, flags);
1315 qib_rc_send_complete(qp, ibhdr);
1316 spin_unlock_irqrestore(&qp->s_lock, flags);
1317 }
1318 return 0;
1319 }
1320
1321 /**
1322 * qib_verbs_send - send a packet
1323 * @qp: the QP to send on
1324 * @hdr: the packet header
1325 * @hdrwords: the number of 32-bit words in the header
1326 * @ss: the SGE to send
1327 * @len: the length of the packet in bytes
1328 *
1329 * Return zero if packet is sent or queued OK.
1330 * Return non-zero and clear qp->s_flags QIB_S_BUSY otherwise.
1331 */
1332 int qib_verbs_send(struct qib_qp *qp, struct qib_ib_header *hdr,
1333 u32 hdrwords, struct qib_sge_state *ss, u32 len)
1334 {
1335 struct qib_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1336 u32 plen;
1337 int ret;
1338 u32 dwords = (len + 3) >> 2;
1339
1340 /*
1341 * Calculate the send buffer trigger address.
1342 * The +1 counts for the pbc control dword following the pbc length.
1343 */
1344 plen = hdrwords + dwords + 1;
1345
1346 /*
1347 * VL15 packets (IB_QPT_SMI) will always use PIO, so we
1348 * can defer SDMA restart until link goes ACTIVE without
1349 * worrying about just how we got there.
1350 */
1351 if (qp->ibqp.qp_type == IB_QPT_SMI ||
1352 !(dd->flags & QIB_HAS_SEND_DMA))
1353 ret = qib_verbs_send_pio(qp, hdr, hdrwords, ss, len,
1354 plen, dwords);
1355 else
1356 ret = qib_verbs_send_dma(qp, hdr, hdrwords, ss, len,
1357 plen, dwords);
1358
1359 return ret;
1360 }
1361
1362 int qib_snapshot_counters(struct qib_pportdata *ppd, u64 *swords,
1363 u64 *rwords, u64 *spkts, u64 *rpkts,
1364 u64 *xmit_wait)
1365 {
1366 int ret;
1367 struct qib_devdata *dd = ppd->dd;
1368
1369 if (!(dd->flags & QIB_PRESENT)) {
1370 /* no hardware, freeze, etc. */
1371 ret = -EINVAL;
1372 goto bail;
1373 }
1374 *swords = dd->f_portcntr(ppd, QIBPORTCNTR_WORDSEND);
1375 *rwords = dd->f_portcntr(ppd, QIBPORTCNTR_WORDRCV);
1376 *spkts = dd->f_portcntr(ppd, QIBPORTCNTR_PKTSEND);
1377 *rpkts = dd->f_portcntr(ppd, QIBPORTCNTR_PKTRCV);
1378 *xmit_wait = dd->f_portcntr(ppd, QIBPORTCNTR_SENDSTALL);
1379
1380 ret = 0;
1381
1382 bail:
1383 return ret;
1384 }
1385
1386 /**
1387 * qib_get_counters - get various chip counters
1388 * @dd: the qlogic_ib device
1389 * @cntrs: counters are placed here
1390 *
1391 * Return the counters needed by recv_pma_get_portcounters().
1392 */
1393 int qib_get_counters(struct qib_pportdata *ppd,
1394 struct qib_verbs_counters *cntrs)
1395 {
1396 int ret;
1397
1398 if (!(ppd->dd->flags & QIB_PRESENT)) {
1399 /* no hardware, freeze, etc. */
1400 ret = -EINVAL;
1401 goto bail;
1402 }
1403 cntrs->symbol_error_counter =
1404 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_IBSYMBOLERR);
1405 cntrs->link_error_recovery_counter =
1406 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_IBLINKERRRECOV);
1407 /*
1408 * The link downed counter counts when the other side downs the
1409 * connection. We add in the number of times we downed the link
1410 * due to local link integrity errors to compensate.
1411 */
1412 cntrs->link_downed_counter =
1413 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_IBLINKDOWN);
1414 cntrs->port_rcv_errors =
1415 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RXDROPPKT) +
1416 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RCVOVFL) +
1417 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERR_RLEN) +
1418 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_INVALIDRLEN) +
1419 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERRLINK) +
1420 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERRICRC) +
1421 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERRVCRC) +
1422 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERRLPCRC) +
1423 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_BADFORMAT);
1424 cntrs->port_rcv_errors +=
1425 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RXLOCALPHYERR);
1426 cntrs->port_rcv_errors +=
1427 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RXVLERR);
1428 cntrs->port_rcv_remphys_errors =
1429 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RCVEBP);
1430 cntrs->port_xmit_discards =
1431 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_UNSUPVL);
1432 cntrs->port_xmit_data = ppd->dd->f_portcntr(ppd,
1433 QIBPORTCNTR_WORDSEND);
1434 cntrs->port_rcv_data = ppd->dd->f_portcntr(ppd,
1435 QIBPORTCNTR_WORDRCV);
1436 cntrs->port_xmit_packets = ppd->dd->f_portcntr(ppd,
1437 QIBPORTCNTR_PKTSEND);
1438 cntrs->port_rcv_packets = ppd->dd->f_portcntr(ppd,
1439 QIBPORTCNTR_PKTRCV);
1440 cntrs->local_link_integrity_errors =
1441 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_LLI);
1442 cntrs->excessive_buffer_overrun_errors =
1443 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_EXCESSBUFOVFL);
1444 cntrs->vl15_dropped =
1445 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_VL15PKTDROP);
1446
1447 ret = 0;
1448
1449 bail:
1450 return ret;
1451 }
1452
1453 /**
1454 * qib_ib_piobufavail - callback when a PIO buffer is available
1455 * @dd: the device pointer
1456 *
1457 * This is called from qib_intr() at interrupt level when a PIO buffer is
1458 * available after qib_verbs_send() returned an error that no buffers were
1459 * available. Disable the interrupt if there are no more QPs waiting.
1460 */
1461 void qib_ib_piobufavail(struct qib_devdata *dd)
1462 {
1463 struct qib_ibdev *dev = &dd->verbs_dev;
1464 struct list_head *list;
1465 struct qib_qp *qps[5];
1466 struct qib_qp *qp;
1467 unsigned long flags;
1468 unsigned i, n;
1469
1470 list = &dev->piowait;
1471 n = 0;
1472
1473 /*
1474 * Note: checking that the piowait list is empty and clearing
1475 * the buffer available interrupt needs to be atomic or we
1476 * could end up with QPs on the wait list with the interrupt
1477 * disabled.
1478 */
1479 spin_lock_irqsave(&dev->pending_lock, flags);
1480 while (!list_empty(list)) {
1481 if (n == ARRAY_SIZE(qps))
1482 goto full;
1483 qp = list_entry(list->next, struct qib_qp, iowait);
1484 list_del_init(&qp->iowait);
1485 atomic_inc(&qp->refcount);
1486 qps[n++] = qp;
1487 }
1488 dd->f_wantpiobuf_intr(dd, 0);
1489 full:
1490 spin_unlock_irqrestore(&dev->pending_lock, flags);
1491
1492 for (i = 0; i < n; i++) {
1493 qp = qps[i];
1494
1495 spin_lock_irqsave(&qp->s_lock, flags);
1496 if (qp->s_flags & QIB_S_WAIT_PIO) {
1497 qp->s_flags &= ~QIB_S_WAIT_PIO;
1498 qib_schedule_send(qp);
1499 }
1500 spin_unlock_irqrestore(&qp->s_lock, flags);
1501
1502 /* Notify qib_destroy_qp() if it is waiting. */
1503 if (atomic_dec_and_test(&qp->refcount))
1504 wake_up(&qp->wait);
1505 }
1506 }
1507
1508 static int qib_query_device(struct ib_device *ibdev,
1509 struct ib_device_attr *props)
1510 {
1511 struct qib_devdata *dd = dd_from_ibdev(ibdev);
1512 struct qib_ibdev *dev = to_idev(ibdev);
1513
1514 memset(props, 0, sizeof(*props));
1515
1516 props->device_cap_flags = IB_DEVICE_BAD_PKEY_CNTR |
1517 IB_DEVICE_BAD_QKEY_CNTR | IB_DEVICE_SHUTDOWN_PORT |
1518 IB_DEVICE_SYS_IMAGE_GUID | IB_DEVICE_RC_RNR_NAK_GEN |
1519 IB_DEVICE_PORT_ACTIVE_EVENT | IB_DEVICE_SRQ_RESIZE;
1520 props->page_size_cap = PAGE_SIZE;
1521 props->vendor_id =
1522 QIB_SRC_OUI_1 << 16 | QIB_SRC_OUI_2 << 8 | QIB_SRC_OUI_3;
1523 props->vendor_part_id = dd->deviceid;
1524 props->hw_ver = dd->minrev;
1525 props->sys_image_guid = ib_qib_sys_image_guid;
1526 props->max_mr_size = ~0ULL;
1527 props->max_qp = ib_qib_max_qps;
1528 props->max_qp_wr = ib_qib_max_qp_wrs;
1529 props->max_sge = ib_qib_max_sges;
1530 props->max_cq = ib_qib_max_cqs;
1531 props->max_ah = ib_qib_max_ahs;
1532 props->max_cqe = ib_qib_max_cqes;
1533 props->max_mr = dev->lk_table.max;
1534 props->max_fmr = dev->lk_table.max;
1535 props->max_map_per_fmr = 32767;
1536 props->max_pd = ib_qib_max_pds;
1537 props->max_qp_rd_atom = QIB_MAX_RDMA_ATOMIC;
1538 props->max_qp_init_rd_atom = 255;
1539 /* props->max_res_rd_atom */
1540 props->max_srq = ib_qib_max_srqs;
1541 props->max_srq_wr = ib_qib_max_srq_wrs;
1542 props->max_srq_sge = ib_qib_max_srq_sges;
1543 /* props->local_ca_ack_delay */
1544 props->atomic_cap = IB_ATOMIC_GLOB;
1545 props->max_pkeys = qib_get_npkeys(dd);
1546 props->max_mcast_grp = ib_qib_max_mcast_grps;
1547 props->max_mcast_qp_attach = ib_qib_max_mcast_qp_attached;
1548 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
1549 props->max_mcast_grp;
1550
1551 return 0;
1552 }
1553
1554 static int qib_query_port(struct ib_device *ibdev, u8 port,
1555 struct ib_port_attr *props)
1556 {
1557 struct qib_devdata *dd = dd_from_ibdev(ibdev);
1558 struct qib_ibport *ibp = to_iport(ibdev, port);
1559 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1560 enum ib_mtu mtu;
1561 u16 lid = ppd->lid;
1562
1563 memset(props, 0, sizeof(*props));
1564 props->lid = lid ? lid : be16_to_cpu(IB_LID_PERMISSIVE);
1565 props->lmc = ppd->lmc;
1566 props->sm_lid = ibp->sm_lid;
1567 props->sm_sl = ibp->sm_sl;
1568 props->state = dd->f_iblink_state(ppd->lastibcstat);
1569 props->phys_state = dd->f_ibphys_portstate(ppd->lastibcstat);
1570 props->port_cap_flags = ibp->port_cap_flags;
1571 props->gid_tbl_len = QIB_GUIDS_PER_PORT;
1572 props->max_msg_sz = 0x80000000;
1573 props->pkey_tbl_len = qib_get_npkeys(dd);
1574 props->bad_pkey_cntr = ibp->pkey_violations;
1575 props->qkey_viol_cntr = ibp->qkey_violations;
1576 props->active_width = ppd->link_width_active;
1577 /* See rate_show() */
1578 props->active_speed = ppd->link_speed_active;
1579 props->max_vl_num = qib_num_vls(ppd->vls_supported);
1580 props->init_type_reply = 0;
1581
1582 props->max_mtu = qib_ibmtu ? qib_ibmtu : IB_MTU_4096;
1583 switch (ppd->ibmtu) {
1584 case 4096:
1585 mtu = IB_MTU_4096;
1586 break;
1587 case 2048:
1588 mtu = IB_MTU_2048;
1589 break;
1590 case 1024:
1591 mtu = IB_MTU_1024;
1592 break;
1593 case 512:
1594 mtu = IB_MTU_512;
1595 break;
1596 case 256:
1597 mtu = IB_MTU_256;
1598 break;
1599 default:
1600 mtu = IB_MTU_2048;
1601 }
1602 props->active_mtu = mtu;
1603 props->subnet_timeout = ibp->subnet_timeout;
1604
1605 return 0;
1606 }
1607
1608 static int qib_modify_device(struct ib_device *device,
1609 int device_modify_mask,
1610 struct ib_device_modify *device_modify)
1611 {
1612 struct qib_devdata *dd = dd_from_ibdev(device);
1613 unsigned i;
1614 int ret;
1615
1616 if (device_modify_mask & ~(IB_DEVICE_MODIFY_SYS_IMAGE_GUID |
1617 IB_DEVICE_MODIFY_NODE_DESC)) {
1618 ret = -EOPNOTSUPP;
1619 goto bail;
1620 }
1621
1622 if (device_modify_mask & IB_DEVICE_MODIFY_NODE_DESC) {
1623 memcpy(device->node_desc, device_modify->node_desc, 64);
1624 for (i = 0; i < dd->num_pports; i++) {
1625 struct qib_ibport *ibp = &dd->pport[i].ibport_data;
1626
1627 qib_node_desc_chg(ibp);
1628 }
1629 }
1630
1631 if (device_modify_mask & IB_DEVICE_MODIFY_SYS_IMAGE_GUID) {
1632 ib_qib_sys_image_guid =
1633 cpu_to_be64(device_modify->sys_image_guid);
1634 for (i = 0; i < dd->num_pports; i++) {
1635 struct qib_ibport *ibp = &dd->pport[i].ibport_data;
1636
1637 qib_sys_guid_chg(ibp);
1638 }
1639 }
1640
1641 ret = 0;
1642
1643 bail:
1644 return ret;
1645 }
1646
1647 static int qib_modify_port(struct ib_device *ibdev, u8 port,
1648 int port_modify_mask, struct ib_port_modify *props)
1649 {
1650 struct qib_ibport *ibp = to_iport(ibdev, port);
1651 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1652
1653 ibp->port_cap_flags |= props->set_port_cap_mask;
1654 ibp->port_cap_flags &= ~props->clr_port_cap_mask;
1655 if (props->set_port_cap_mask || props->clr_port_cap_mask)
1656 qib_cap_mask_chg(ibp);
1657 if (port_modify_mask & IB_PORT_SHUTDOWN)
1658 qib_set_linkstate(ppd, QIB_IB_LINKDOWN);
1659 if (port_modify_mask & IB_PORT_RESET_QKEY_CNTR)
1660 ibp->qkey_violations = 0;
1661 return 0;
1662 }
1663
1664 static int qib_query_gid(struct ib_device *ibdev, u8 port,
1665 int index, union ib_gid *gid)
1666 {
1667 struct qib_devdata *dd = dd_from_ibdev(ibdev);
1668 int ret = 0;
1669
1670 if (!port || port > dd->num_pports)
1671 ret = -EINVAL;
1672 else {
1673 struct qib_ibport *ibp = to_iport(ibdev, port);
1674 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1675
1676 gid->global.subnet_prefix = ibp->gid_prefix;
1677 if (index == 0)
1678 gid->global.interface_id = ppd->guid;
1679 else if (index < QIB_GUIDS_PER_PORT)
1680 gid->global.interface_id = ibp->guids[index - 1];
1681 else
1682 ret = -EINVAL;
1683 }
1684
1685 return ret;
1686 }
1687
1688 static struct ib_pd *qib_alloc_pd(struct ib_device *ibdev,
1689 struct ib_ucontext *context,
1690 struct ib_udata *udata)
1691 {
1692 struct qib_ibdev *dev = to_idev(ibdev);
1693 struct qib_pd *pd;
1694 struct ib_pd *ret;
1695
1696 /*
1697 * This is actually totally arbitrary. Some correctness tests
1698 * assume there's a maximum number of PDs that can be allocated.
1699 * We don't actually have this limit, but we fail the test if
1700 * we allow allocations of more than we report for this value.
1701 */
1702
1703 pd = kmalloc(sizeof *pd, GFP_KERNEL);
1704 if (!pd) {
1705 ret = ERR_PTR(-ENOMEM);
1706 goto bail;
1707 }
1708
1709 spin_lock(&dev->n_pds_lock);
1710 if (dev->n_pds_allocated == ib_qib_max_pds) {
1711 spin_unlock(&dev->n_pds_lock);
1712 kfree(pd);
1713 ret = ERR_PTR(-ENOMEM);
1714 goto bail;
1715 }
1716
1717 dev->n_pds_allocated++;
1718 spin_unlock(&dev->n_pds_lock);
1719
1720 /* ib_alloc_pd() will initialize pd->ibpd. */
1721 pd->user = udata != NULL;
1722
1723 ret = &pd->ibpd;
1724
1725 bail:
1726 return ret;
1727 }
1728
1729 static int qib_dealloc_pd(struct ib_pd *ibpd)
1730 {
1731 struct qib_pd *pd = to_ipd(ibpd);
1732 struct qib_ibdev *dev = to_idev(ibpd->device);
1733
1734 spin_lock(&dev->n_pds_lock);
1735 dev->n_pds_allocated--;
1736 spin_unlock(&dev->n_pds_lock);
1737
1738 kfree(pd);
1739
1740 return 0;
1741 }
1742
1743 int qib_check_ah(struct ib_device *ibdev, struct ib_ah_attr *ah_attr)
1744 {
1745 /* A multicast address requires a GRH (see ch. 8.4.1). */
1746 if (ah_attr->dlid >= QIB_MULTICAST_LID_BASE &&
1747 ah_attr->dlid != QIB_PERMISSIVE_LID &&
1748 !(ah_attr->ah_flags & IB_AH_GRH))
1749 goto bail;
1750 if ((ah_attr->ah_flags & IB_AH_GRH) &&
1751 ah_attr->grh.sgid_index >= QIB_GUIDS_PER_PORT)
1752 goto bail;
1753 if (ah_attr->dlid == 0)
1754 goto bail;
1755 if (ah_attr->port_num < 1 ||
1756 ah_attr->port_num > ibdev->phys_port_cnt)
1757 goto bail;
1758 if (ah_attr->static_rate != IB_RATE_PORT_CURRENT &&
1759 ib_rate_to_mult(ah_attr->static_rate) < 0)
1760 goto bail;
1761 if (ah_attr->sl > 15)
1762 goto bail;
1763 return 0;
1764 bail:
1765 return -EINVAL;
1766 }
1767
1768 /**
1769 * qib_create_ah - create an address handle
1770 * @pd: the protection domain
1771 * @ah_attr: the attributes of the AH
1772 *
1773 * This may be called from interrupt context.
1774 */
1775 static struct ib_ah *qib_create_ah(struct ib_pd *pd,
1776 struct ib_ah_attr *ah_attr)
1777 {
1778 struct qib_ah *ah;
1779 struct ib_ah *ret;
1780 struct qib_ibdev *dev = to_idev(pd->device);
1781 unsigned long flags;
1782
1783 if (qib_check_ah(pd->device, ah_attr)) {
1784 ret = ERR_PTR(-EINVAL);
1785 goto bail;
1786 }
1787
1788 ah = kmalloc(sizeof *ah, GFP_ATOMIC);
1789 if (!ah) {
1790 ret = ERR_PTR(-ENOMEM);
1791 goto bail;
1792 }
1793
1794 spin_lock_irqsave(&dev->n_ahs_lock, flags);
1795 if (dev->n_ahs_allocated == ib_qib_max_ahs) {
1796 spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1797 kfree(ah);
1798 ret = ERR_PTR(-ENOMEM);
1799 goto bail;
1800 }
1801
1802 dev->n_ahs_allocated++;
1803 spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1804
1805 /* ib_create_ah() will initialize ah->ibah. */
1806 ah->attr = *ah_attr;
1807 atomic_set(&ah->refcount, 0);
1808
1809 ret = &ah->ibah;
1810
1811 bail:
1812 return ret;
1813 }
1814
1815 /**
1816 * qib_destroy_ah - destroy an address handle
1817 * @ibah: the AH to destroy
1818 *
1819 * This may be called from interrupt context.
1820 */
1821 static int qib_destroy_ah(struct ib_ah *ibah)
1822 {
1823 struct qib_ibdev *dev = to_idev(ibah->device);
1824 struct qib_ah *ah = to_iah(ibah);
1825 unsigned long flags;
1826
1827 if (atomic_read(&ah->refcount) != 0)
1828 return -EBUSY;
1829
1830 spin_lock_irqsave(&dev->n_ahs_lock, flags);
1831 dev->n_ahs_allocated--;
1832 spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1833
1834 kfree(ah);
1835
1836 return 0;
1837 }
1838
1839 static int qib_modify_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr)
1840 {
1841 struct qib_ah *ah = to_iah(ibah);
1842
1843 if (qib_check_ah(ibah->device, ah_attr))
1844 return -EINVAL;
1845
1846 ah->attr = *ah_attr;
1847
1848 return 0;
1849 }
1850
1851 static int qib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr)
1852 {
1853 struct qib_ah *ah = to_iah(ibah);
1854
1855 *ah_attr = ah->attr;
1856
1857 return 0;
1858 }
1859
1860 /**
1861 * qib_get_npkeys - return the size of the PKEY table for context 0
1862 * @dd: the qlogic_ib device
1863 */
1864 unsigned qib_get_npkeys(struct qib_devdata *dd)
1865 {
1866 return ARRAY_SIZE(dd->rcd[0]->pkeys);
1867 }
1868
1869 /*
1870 * Return the indexed PKEY from the port PKEY table.
1871 * No need to validate rcd[ctxt]; the port is setup if we are here.
1872 */
1873 unsigned qib_get_pkey(struct qib_ibport *ibp, unsigned index)
1874 {
1875 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1876 struct qib_devdata *dd = ppd->dd;
1877 unsigned ctxt = ppd->hw_pidx;
1878 unsigned ret;
1879
1880 /* dd->rcd null if mini_init or some init failures */
1881 if (!dd->rcd || index >= ARRAY_SIZE(dd->rcd[ctxt]->pkeys))
1882 ret = 0;
1883 else
1884 ret = dd->rcd[ctxt]->pkeys[index];
1885
1886 return ret;
1887 }
1888
1889 static int qib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1890 u16 *pkey)
1891 {
1892 struct qib_devdata *dd = dd_from_ibdev(ibdev);
1893 int ret;
1894
1895 if (index >= qib_get_npkeys(dd)) {
1896 ret = -EINVAL;
1897 goto bail;
1898 }
1899
1900 *pkey = qib_get_pkey(to_iport(ibdev, port), index);
1901 ret = 0;
1902
1903 bail:
1904 return ret;
1905 }
1906
1907 /**
1908 * qib_alloc_ucontext - allocate a ucontest
1909 * @ibdev: the infiniband device
1910 * @udata: not used by the QLogic_IB driver
1911 */
1912
1913 static struct ib_ucontext *qib_alloc_ucontext(struct ib_device *ibdev,
1914 struct ib_udata *udata)
1915 {
1916 struct qib_ucontext *context;
1917 struct ib_ucontext *ret;
1918
1919 context = kmalloc(sizeof *context, GFP_KERNEL);
1920 if (!context) {
1921 ret = ERR_PTR(-ENOMEM);
1922 goto bail;
1923 }
1924
1925 ret = &context->ibucontext;
1926
1927 bail:
1928 return ret;
1929 }
1930
1931 static int qib_dealloc_ucontext(struct ib_ucontext *context)
1932 {
1933 kfree(to_iucontext(context));
1934 return 0;
1935 }
1936
1937 static void init_ibport(struct qib_pportdata *ppd)
1938 {
1939 struct qib_verbs_counters cntrs;
1940 struct qib_ibport *ibp = &ppd->ibport_data;
1941
1942 spin_lock_init(&ibp->lock);
1943 /* Set the prefix to the default value (see ch. 4.1.1) */
1944 ibp->gid_prefix = IB_DEFAULT_GID_PREFIX;
1945 ibp->sm_lid = be16_to_cpu(IB_LID_PERMISSIVE);
1946 ibp->port_cap_flags = IB_PORT_SYS_IMAGE_GUID_SUP |
1947 IB_PORT_CLIENT_REG_SUP | IB_PORT_SL_MAP_SUP |
1948 IB_PORT_TRAP_SUP | IB_PORT_AUTO_MIGR_SUP |
1949 IB_PORT_DR_NOTICE_SUP | IB_PORT_CAP_MASK_NOTICE_SUP |
1950 IB_PORT_OTHER_LOCAL_CHANGES_SUP;
1951 if (ppd->dd->flags & QIB_HAS_LINK_LATENCY)
1952 ibp->port_cap_flags |= IB_PORT_LINK_LATENCY_SUP;
1953 ibp->pma_counter_select[0] = IB_PMA_PORT_XMIT_DATA;
1954 ibp->pma_counter_select[1] = IB_PMA_PORT_RCV_DATA;
1955 ibp->pma_counter_select[2] = IB_PMA_PORT_XMIT_PKTS;
1956 ibp->pma_counter_select[3] = IB_PMA_PORT_RCV_PKTS;
1957 ibp->pma_counter_select[4] = IB_PMA_PORT_XMIT_WAIT;
1958
1959 /* Snapshot current HW counters to "clear" them. */
1960 qib_get_counters(ppd, &cntrs);
1961 ibp->z_symbol_error_counter = cntrs.symbol_error_counter;
1962 ibp->z_link_error_recovery_counter =
1963 cntrs.link_error_recovery_counter;
1964 ibp->z_link_downed_counter = cntrs.link_downed_counter;
1965 ibp->z_port_rcv_errors = cntrs.port_rcv_errors;
1966 ibp->z_port_rcv_remphys_errors = cntrs.port_rcv_remphys_errors;
1967 ibp->z_port_xmit_discards = cntrs.port_xmit_discards;
1968 ibp->z_port_xmit_data = cntrs.port_xmit_data;
1969 ibp->z_port_rcv_data = cntrs.port_rcv_data;
1970 ibp->z_port_xmit_packets = cntrs.port_xmit_packets;
1971 ibp->z_port_rcv_packets = cntrs.port_rcv_packets;
1972 ibp->z_local_link_integrity_errors =
1973 cntrs.local_link_integrity_errors;
1974 ibp->z_excessive_buffer_overrun_errors =
1975 cntrs.excessive_buffer_overrun_errors;
1976 ibp->z_vl15_dropped = cntrs.vl15_dropped;
1977 }
1978
1979 /**
1980 * qib_register_ib_device - register our device with the infiniband core
1981 * @dd: the device data structure
1982 * Return the allocated qib_ibdev pointer or NULL on error.
1983 */
1984 int qib_register_ib_device(struct qib_devdata *dd)
1985 {
1986 struct qib_ibdev *dev = &dd->verbs_dev;
1987 struct ib_device *ibdev = &dev->ibdev;
1988 struct qib_pportdata *ppd = dd->pport;
1989 unsigned i, lk_tab_size;
1990 int ret;
1991
1992 dev->qp_table_size = ib_qib_qp_table_size;
1993 dev->qp_table = kzalloc(dev->qp_table_size * sizeof *dev->qp_table,
1994 GFP_KERNEL);
1995 if (!dev->qp_table) {
1996 ret = -ENOMEM;
1997 goto err_qpt;
1998 }
1999
2000 for (i = 0; i < dd->num_pports; i++)
2001 init_ibport(ppd + i);
2002
2003 /* Only need to initialize non-zero fields. */
2004 spin_lock_init(&dev->qpt_lock);
2005 spin_lock_init(&dev->n_pds_lock);
2006 spin_lock_init(&dev->n_ahs_lock);
2007 spin_lock_init(&dev->n_cqs_lock);
2008 spin_lock_init(&dev->n_qps_lock);
2009 spin_lock_init(&dev->n_srqs_lock);
2010 spin_lock_init(&dev->n_mcast_grps_lock);
2011 init_timer(&dev->mem_timer);
2012 dev->mem_timer.function = mem_timer;
2013 dev->mem_timer.data = (unsigned long) dev;
2014
2015 qib_init_qpn_table(dd, &dev->qpn_table);
2016
2017 /*
2018 * The top ib_qib_lkey_table_size bits are used to index the
2019 * table. The lower 8 bits can be owned by the user (copied from
2020 * the LKEY). The remaining bits act as a generation number or tag.
2021 */
2022 spin_lock_init(&dev->lk_table.lock);
2023 dev->lk_table.max = 1 << ib_qib_lkey_table_size;
2024 lk_tab_size = dev->lk_table.max * sizeof(*dev->lk_table.table);
2025 dev->lk_table.table = (struct qib_mregion **)
2026 __get_free_pages(GFP_KERNEL, get_order(lk_tab_size));
2027 if (dev->lk_table.table == NULL) {
2028 ret = -ENOMEM;
2029 goto err_lk;
2030 }
2031 memset(dev->lk_table.table, 0, lk_tab_size);
2032 INIT_LIST_HEAD(&dev->pending_mmaps);
2033 spin_lock_init(&dev->pending_lock);
2034 dev->mmap_offset = PAGE_SIZE;
2035 spin_lock_init(&dev->mmap_offset_lock);
2036 INIT_LIST_HEAD(&dev->piowait);
2037 INIT_LIST_HEAD(&dev->dmawait);
2038 INIT_LIST_HEAD(&dev->txwait);
2039 INIT_LIST_HEAD(&dev->memwait);
2040 INIT_LIST_HEAD(&dev->txreq_free);
2041
2042 if (ppd->sdma_descq_cnt) {
2043 dev->pio_hdrs = dma_alloc_coherent(&dd->pcidev->dev,
2044 ppd->sdma_descq_cnt *
2045 sizeof(struct qib_pio_header),
2046 &dev->pio_hdrs_phys,
2047 GFP_KERNEL);
2048 if (!dev->pio_hdrs) {
2049 ret = -ENOMEM;
2050 goto err_hdrs;
2051 }
2052 }
2053
2054 for (i = 0; i < ppd->sdma_descq_cnt; i++) {
2055 struct qib_verbs_txreq *tx;
2056
2057 tx = kzalloc(sizeof *tx, GFP_KERNEL);
2058 if (!tx) {
2059 ret = -ENOMEM;
2060 goto err_tx;
2061 }
2062 tx->hdr_inx = i;
2063 list_add(&tx->txreq.list, &dev->txreq_free);
2064 }
2065
2066 /*
2067 * The system image GUID is supposed to be the same for all
2068 * IB HCAs in a single system but since there can be other
2069 * device types in the system, we can't be sure this is unique.
2070 */
2071 if (!ib_qib_sys_image_guid)
2072 ib_qib_sys_image_guid = ppd->guid;
2073
2074 strlcpy(ibdev->name, "qib%d", IB_DEVICE_NAME_MAX);
2075 ibdev->owner = THIS_MODULE;
2076 ibdev->node_guid = ppd->guid;
2077 ibdev->uverbs_abi_ver = QIB_UVERBS_ABI_VERSION;
2078 ibdev->uverbs_cmd_mask =
2079 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2080 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2081 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2082 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2083 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2084 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
2085 (1ull << IB_USER_VERBS_CMD_MODIFY_AH) |
2086 (1ull << IB_USER_VERBS_CMD_QUERY_AH) |
2087 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
2088 (1ull << IB_USER_VERBS_CMD_REG_MR) |
2089 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2090 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2091 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
2092 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
2093 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2094 (1ull << IB_USER_VERBS_CMD_POLL_CQ) |
2095 (1ull << IB_USER_VERBS_CMD_REQ_NOTIFY_CQ) |
2096 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2097 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
2098 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
2099 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2100 (1ull << IB_USER_VERBS_CMD_POST_SEND) |
2101 (1ull << IB_USER_VERBS_CMD_POST_RECV) |
2102 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
2103 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
2104 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
2105 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
2106 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
2107 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
2108 (1ull << IB_USER_VERBS_CMD_POST_SRQ_RECV);
2109 ibdev->node_type = RDMA_NODE_IB_CA;
2110 ibdev->phys_port_cnt = dd->num_pports;
2111 ibdev->num_comp_vectors = 1;
2112 ibdev->dma_device = &dd->pcidev->dev;
2113 ibdev->query_device = qib_query_device;
2114 ibdev->modify_device = qib_modify_device;
2115 ibdev->query_port = qib_query_port;
2116 ibdev->modify_port = qib_modify_port;
2117 ibdev->query_pkey = qib_query_pkey;
2118 ibdev->query_gid = qib_query_gid;
2119 ibdev->alloc_ucontext = qib_alloc_ucontext;
2120 ibdev->dealloc_ucontext = qib_dealloc_ucontext;
2121 ibdev->alloc_pd = qib_alloc_pd;
2122 ibdev->dealloc_pd = qib_dealloc_pd;
2123 ibdev->create_ah = qib_create_ah;
2124 ibdev->destroy_ah = qib_destroy_ah;
2125 ibdev->modify_ah = qib_modify_ah;
2126 ibdev->query_ah = qib_query_ah;
2127 ibdev->create_srq = qib_create_srq;
2128 ibdev->modify_srq = qib_modify_srq;
2129 ibdev->query_srq = qib_query_srq;
2130 ibdev->destroy_srq = qib_destroy_srq;
2131 ibdev->create_qp = qib_create_qp;
2132 ibdev->modify_qp = qib_modify_qp;
2133 ibdev->query_qp = qib_query_qp;
2134 ibdev->destroy_qp = qib_destroy_qp;
2135 ibdev->post_send = qib_post_send;
2136 ibdev->post_recv = qib_post_receive;
2137 ibdev->post_srq_recv = qib_post_srq_receive;
2138 ibdev->create_cq = qib_create_cq;
2139 ibdev->destroy_cq = qib_destroy_cq;
2140 ibdev->resize_cq = qib_resize_cq;
2141 ibdev->poll_cq = qib_poll_cq;
2142 ibdev->req_notify_cq = qib_req_notify_cq;
2143 ibdev->get_dma_mr = qib_get_dma_mr;
2144 ibdev->reg_phys_mr = qib_reg_phys_mr;
2145 ibdev->reg_user_mr = qib_reg_user_mr;
2146 ibdev->dereg_mr = qib_dereg_mr;
2147 ibdev->alloc_fast_reg_mr = qib_alloc_fast_reg_mr;
2148 ibdev->alloc_fast_reg_page_list = qib_alloc_fast_reg_page_list;
2149 ibdev->free_fast_reg_page_list = qib_free_fast_reg_page_list;
2150 ibdev->alloc_fmr = qib_alloc_fmr;
2151 ibdev->map_phys_fmr = qib_map_phys_fmr;
2152 ibdev->unmap_fmr = qib_unmap_fmr;
2153 ibdev->dealloc_fmr = qib_dealloc_fmr;
2154 ibdev->attach_mcast = qib_multicast_attach;
2155 ibdev->detach_mcast = qib_multicast_detach;
2156 ibdev->process_mad = qib_process_mad;
2157 ibdev->mmap = qib_mmap;
2158 ibdev->dma_ops = &qib_dma_mapping_ops;
2159
2160 snprintf(ibdev->node_desc, sizeof(ibdev->node_desc),
2161 QIB_IDSTR " %s", init_utsname()->nodename);
2162
2163 ret = ib_register_device(ibdev, qib_create_port_files);
2164 if (ret)
2165 goto err_reg;
2166
2167 ret = qib_create_agents(dev);
2168 if (ret)
2169 goto err_agents;
2170
2171 if (qib_verbs_register_sysfs(dd))
2172 goto err_class;
2173
2174 goto bail;
2175
2176 err_class:
2177 qib_free_agents(dev);
2178 err_agents:
2179 ib_unregister_device(ibdev);
2180 err_reg:
2181 err_tx:
2182 while (!list_empty(&dev->txreq_free)) {
2183 struct list_head *l = dev->txreq_free.next;
2184 struct qib_verbs_txreq *tx;
2185
2186 list_del(l);
2187 tx = list_entry(l, struct qib_verbs_txreq, txreq.list);
2188 kfree(tx);
2189 }
2190 if (ppd->sdma_descq_cnt)
2191 dma_free_coherent(&dd->pcidev->dev,
2192 ppd->sdma_descq_cnt *
2193 sizeof(struct qib_pio_header),
2194 dev->pio_hdrs, dev->pio_hdrs_phys);
2195 err_hdrs:
2196 free_pages((unsigned long) dev->lk_table.table, get_order(lk_tab_size));
2197 err_lk:
2198 kfree(dev->qp_table);
2199 err_qpt:
2200 qib_dev_err(dd, "cannot register verbs: %d!\n", -ret);
2201 bail:
2202 return ret;
2203 }
2204
2205 void qib_unregister_ib_device(struct qib_devdata *dd)
2206 {
2207 struct qib_ibdev *dev = &dd->verbs_dev;
2208 struct ib_device *ibdev = &dev->ibdev;
2209 u32 qps_inuse;
2210 unsigned lk_tab_size;
2211
2212 qib_verbs_unregister_sysfs(dd);
2213
2214 qib_free_agents(dev);
2215
2216 ib_unregister_device(ibdev);
2217
2218 if (!list_empty(&dev->piowait))
2219 qib_dev_err(dd, "piowait list not empty!\n");
2220 if (!list_empty(&dev->dmawait))
2221 qib_dev_err(dd, "dmawait list not empty!\n");
2222 if (!list_empty(&dev->txwait))
2223 qib_dev_err(dd, "txwait list not empty!\n");
2224 if (!list_empty(&dev->memwait))
2225 qib_dev_err(dd, "memwait list not empty!\n");
2226 if (dev->dma_mr)
2227 qib_dev_err(dd, "DMA MR not NULL!\n");
2228
2229 qps_inuse = qib_free_all_qps(dd);
2230 if (qps_inuse)
2231 qib_dev_err(dd, "QP memory leak! %u still in use\n",
2232 qps_inuse);
2233
2234 del_timer_sync(&dev->mem_timer);
2235 qib_free_qpn_table(&dev->qpn_table);
2236 while (!list_empty(&dev->txreq_free)) {
2237 struct list_head *l = dev->txreq_free.next;
2238 struct qib_verbs_txreq *tx;
2239
2240 list_del(l);
2241 tx = list_entry(l, struct qib_verbs_txreq, txreq.list);
2242 kfree(tx);
2243 }
2244 if (dd->pport->sdma_descq_cnt)
2245 dma_free_coherent(&dd->pcidev->dev,
2246 dd->pport->sdma_descq_cnt *
2247 sizeof(struct qib_pio_header),
2248 dev->pio_hdrs, dev->pio_hdrs_phys);
2249 lk_tab_size = dev->lk_table.max * sizeof(*dev->lk_table.table);
2250 free_pages((unsigned long) dev->lk_table.table,
2251 get_order(lk_tab_size));
2252 kfree(dev->qp_table);
2253 }