spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / boot / compressed / head-xscale.S
blobaa5ee49c5c5ae7c1e37b6ab281a2f09388902f57
1 /*
2  * linux/arch/arm/boot/compressed/head-xscale.S
3  *
4  * XScale specific tweaks.  This is merged into head.S by the linker.
5  *
6  */
8 #include <linux/linkage.h>
10                 .section        ".start", "ax"
12 __XScale_start:
14                 @ Preserve r8/r7 i.e. kernel entry values
16                 @ Data cache might be active.
17                 @ Be sure to flush kernel binary out of the cache,
18                 @ whatever state it is, before it is turned off.
19                 @ This is done by fetching through currently executed
20                 @ memory to be sure we hit the same cache.
21                 bic     r2, pc, #0x1f
22                 add     r3, r2, #0x10000        @ 64 kb is quite enough...
23 1:              ldr     r0, [r2], #32
24                 teq     r2, r3
25                 bne     1b
26                 mcr     p15, 0, r0, c7, c10, 4  @ drain WB
27                 mcr     p15, 0, r0, c7, c7, 0   @ flush I & D caches
29                 @ disabling MMU and caches
30                 mrc     p15, 0, r0, c1, c0, 0   @ read control reg
31                 bic     r0, r0, #0x05           @ clear DC, MMU
32                 bic     r0, r0, #0x1000         @ clear Icache
33                 mcr     p15, 0, r0, c1, c0, 0
35 #ifdef CONFIG_ARCH_IXP2000
36                 mov     r1, #-1
37                 mov     r0, #0xd6000000
38                 str     r1, [r0, #0x14]
39                 str     r1, [r0, #0x18]
40 #endif