spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / boot / dts / imx6q-sabrelite.dts
blob08d920de72868a33347091a9d5f09dbc2147994d
1 /*
2  * Copyright 2011 Freescale Semiconductor, Inc.
3  * Copyright 2011 Linaro Ltd.
4  *
5  * The code contained herein is licensed under the GNU General Public
6  * License. You may obtain a copy of the GNU General Public License
7  * Version 2 or later at the following locations:
8  *
9  * http://www.opensource.org/licenses/gpl-license.html
10  * http://www.gnu.org/copyleft/gpl.html
11  */
13 /dts-v1/;
14 /include/ "imx6q.dtsi"
16 / {
17         model = "Freescale i.MX6 Quad SABRE Lite Board";
18         compatible = "fsl,imx6q-sabrelite", "fsl,imx6q";
20         memory {
21                 reg = <0x10000000 0x40000000>;
22         };
24         soc {
25                 aips-bus@02100000 { /* AIPS2 */
26                         enet@02188000 {
27                                 phy-mode = "rgmii";
28                                 phy-reset-gpios = <&gpio3 23 0>;
29                                 status = "okay";
30                         };
32                         usdhc@02198000 { /* uSDHC3 */
33                                 cd-gpios = <&gpio7 0 0>;
34                                 wp-gpios = <&gpio7 1 0>;
35                                 status = "okay";
36                         };
38                         usdhc@0219c000 { /* uSDHC4 */
39                                 cd-gpios = <&gpio2 6 0>;
40                                 wp-gpios = <&gpio2 7 0>;
41                                 status = "okay";
42                         };
44                         uart2: uart@021e8000 {
45                                 status = "okay";
46                         };
47                 };
48         };