2 * arch/arm/include/asm/assembler.h
4 * Copyright (C) 1996-2000 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This file contains arm architecture specific defines
11 * for the different processors.
13 * Do not include any C declarations in this file - it is included by
16 #ifndef __ASM_ASSEMBLER_H__
17 #define __ASM_ASSEMBLER_H__
20 #error "Only include this from assembly code"
23 #include <asm/ptrace.h>
24 #include <asm/domain.h>
27 * Endian independent macros for shifting bytes within registers.
32 #define get_byte_0 lsl #0
33 #define get_byte_1 lsr #8
34 #define get_byte_2 lsr #16
35 #define get_byte_3 lsr #24
36 #define put_byte_0 lsl #0
37 #define put_byte_1 lsl #8
38 #define put_byte_2 lsl #16
39 #define put_byte_3 lsl #24
43 #define get_byte_0 lsr #24
44 #define get_byte_1 lsr #16
45 #define get_byte_2 lsr #8
46 #define get_byte_3 lsl #0
47 #define put_byte_0 lsl #24
48 #define put_byte_1 lsl #16
49 #define put_byte_2 lsl #8
50 #define put_byte_3 lsl #0
54 * Data preload for architectures that support it
56 #if __LINUX_ARM_ARCH__ >= 5
57 #define PLD(code...) code
63 * This can be used to enable code to cacheline align the destination
64 * pointer when bulk writing to memory. Experiments on StrongARM and
65 * XScale didn't show this a worthwhile thing to do when the cache is not
66 * set to write-allocate (this would need further testing on XScale when WA
69 * On Feroceon there is much to gain however, regardless of cache mode.
71 #ifdef CONFIG_CPU_FEROCEON
72 #define CALGN(code...) code
74 #define CALGN(code...)
78 * Enable and disable interrupts
80 #if __LINUX_ARM_ARCH__ >= 6
81 .macro disable_irq_notrace
85 .macro enable_irq_notrace
89 .macro disable_irq_notrace
90 msr cpsr_c
, #PSR_I_BIT | SVC_MODE
93 .macro enable_irq_notrace
98 .macro asm_trace_hardirqs_off
99 #if defined(CONFIG_TRACE_IRQFLAGS)
100 stmdb sp
!, {r0
-r3
, ip
, lr
}
101 bl trace_hardirqs_off
102 ldmia sp
!, {r0
-r3
, ip
, lr
}
106 .macro asm_trace_hardirqs_on_cond
, cond
107 #if defined(CONFIG_TRACE_IRQFLAGS)
109 * actually the registers should be pushed and pop'd conditionally, but
110 * after bl the flags are certainly clobbered
112 stmdb sp
!, {r0
-r3
, ip
, lr
}
113 bl\cond trace_hardirqs_on
114 ldmia sp
!, {r0
-r3
, ip
, lr
}
118 .macro asm_trace_hardirqs_on
119 asm_trace_hardirqs_on_cond al
124 asm_trace_hardirqs_off
128 asm_trace_hardirqs_on
132 * Save the current IRQ state and disable IRQs. Note that this macro
133 * assumes FIQs are enabled, and that the processor is in SVC mode.
135 .macro save_and_disable_irqs
, oldcpsr
140 .macro save_and_disable_irqs_notrace
, oldcpsr
146 * Restore interrupt state previously stored in a register. We don't
147 * guarantee that this will preserve the flags.
149 .macro restore_irqs_notrace
, oldcpsr
153 .macro restore_irqs
, oldcpsr
154 tst \oldcpsr
, #PSR_I_BIT
155 asm_trace_hardirqs_on_cond eq
156 restore_irqs_notrace \oldcpsr
161 .pushsection __ex_table,"a"; \
167 #define ALT_SMP(instr...) \
170 * Note: if you get assembler errors from ALT_UP() when building with
171 * CONFIG_THUMB2_KERNEL, you almost certainly need to use
172 * ALT_SMP( W(instr) ... )
174 #define ALT_UP(instr...) \
175 .pushsection ".alt.smp.init", "a" ;\
178 .if . - 9997b != 4 ;\
179 .error "ALT_UP() content must assemble to exactly 4 bytes";\
182 #define ALT_UP_B(label) \
183 .equ up_b_offset, label - 9998b ;\
184 .pushsection ".alt.smp.init", "a" ;\
186 W(b) . + up_b_offset ;\
189 #define ALT_SMP(instr...)
190 #define ALT_UP(instr...) instr
191 #define ALT_UP_B(label) b label
195 * Instruction barrier
198 #if __LINUX_ARM_ARCH__ >= 7
200 #elif __LINUX_ARM_ARCH__ == 6
201 mcr p15
, 0, r0
, c7
, c5
, 4
206 * SMP data memory barrier
210 #if __LINUX_ARM_ARCH__ >= 7
216 #elif __LINUX_ARM_ARCH__ == 6
217 ALT_SMP(mcr p15
, 0, r0
, c7
, c10
, 5) @ dmb
219 #error Incompatible SMP platform
229 #ifdef CONFIG_THUMB2_KERNEL
230 .macro setmode
, mode
, reg
235 .macro setmode
, mode
, reg
241 * STRT/LDRT access macros with ARM and Thumb-2 variants
243 #ifdef CONFIG_THUMB2_KERNEL
245 .macro usraccoff
, instr
, reg
, ptr
, inc
, off
, cond
, abort
, t
=TUSER()
248 \instr\cond\
()b\
()\t\
().w
\reg
, [\ptr
, #\off]
250 \instr\cond\
()\t\
().w
\reg
, [\ptr
, #\off]
252 .error
"Unsupported inc macro argument"
255 .pushsection __ex_table
,"a"
261 .macro usracc
, instr
, reg
, ptr
, inc
, cond
, rept
, abort
262 @
explicit IT instruction needed because of the label
263 @ introduced by the USER macro
270 .error
"Unsupported rept macro argument"
274 @ Slightly optimised to avoid incrementing the pointer twice
275 usraccoff \instr
, \reg
, \ptr
, \inc
, 0, \cond
, \abort
277 usraccoff \instr
, \reg
, \ptr
, \inc
, \inc
, \cond
, \abort
280 add\cond \ptr
, #\rept * \inc
283 #else /* !CONFIG_THUMB2_KERNEL */
285 .macro usracc
, instr
, reg
, ptr
, inc
, cond
, rept
, abort
, t
=TUSER()
289 \instr\cond\
()b\
()\t \reg
, [\ptr
], #\inc
291 \instr\cond\
()\t \reg
, [\ptr
], #\inc
293 .error
"Unsupported inc macro argument"
296 .pushsection __ex_table
,"a"
303 #endif /* CONFIG_THUMB2_KERNEL */
305 .macro strusr
, reg
, ptr
, inc
, cond
=al
, rept
=1, abort
=9001f
306 usracc str
, \reg
, \ptr
, \inc
, \cond
, \rept
, \abort
309 .macro ldrusr
, reg
, ptr
, inc
, cond
=al
, rept
=1, abort
=9001f
310 usracc ldr
, \reg
, \ptr
, \inc
, \cond
, \rept
, \abort
313 /* Utility macro for declaring string literals */
314 .macro string name
:req
, string
315 .type
\name
, #object
318 .size
\name
, . - \name
321 #endif /* __ASM_ASSEMBLER_H__ */