spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / include / asm / mach / irq.h
blobfebe495d0c6e15777b9e393a50cc08d7fbdd917c
1 /*
2 * arch/arm/include/asm/mach/irq.h
4 * Copyright (C) 1995-2000 Russell King.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10 #ifndef __ASM_ARM_MACH_IRQ_H
11 #define __ASM_ARM_MACH_IRQ_H
13 #include <linux/irq.h>
15 struct seq_file;
18 * This is internal. Do not use it.
20 extern void init_FIQ(void);
21 extern int show_fiq_list(struct seq_file *, int);
23 #ifdef CONFIG_MULTI_IRQ_HANDLER
24 extern void (*handle_arch_irq)(struct pt_regs *);
25 #endif
28 * This is for easy migration, but should be changed in the source
30 #define do_bad_IRQ(irq,desc) \
31 do { \
32 raw_spin_lock(&desc->lock); \
33 handle_bad_irq(irq, desc); \
34 raw_spin_unlock(&desc->lock); \
35 } while(0)
37 #ifndef __ASSEMBLY__
39 * Entry/exit functions for chained handlers where the primary IRQ chip
40 * may implement either fasteoi or level-trigger flow control.
42 static inline void chained_irq_enter(struct irq_chip *chip,
43 struct irq_desc *desc)
45 /* FastEOI controllers require no action on entry. */
46 if (chip->irq_eoi)
47 return;
49 if (chip->irq_mask_ack) {
50 chip->irq_mask_ack(&desc->irq_data);
51 } else {
52 chip->irq_mask(&desc->irq_data);
53 if (chip->irq_ack)
54 chip->irq_ack(&desc->irq_data);
58 static inline void chained_irq_exit(struct irq_chip *chip,
59 struct irq_desc *desc)
61 if (chip->irq_eoi)
62 chip->irq_eoi(&desc->irq_data);
63 else
64 chip->irq_unmask(&desc->irq_data);
66 #endif
68 #endif