spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / include / asm / perf_event.h
blob99cfe36079893101b382acf9a5fefd6279f206aa
1 /*
2 * linux/arch/arm/include/asm/perf_event.h
4 * Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
12 #ifndef __ARM_PERF_EVENT_H__
13 #define __ARM_PERF_EVENT_H__
15 /* ARM performance counters start from 1 (in the cp15 accesses) so use the
16 * same indexes here for consistency. */
17 #define PERF_EVENT_INDEX_OFFSET 1
19 /* ARM perf PMU IDs for use by internal perf clients. */
20 enum arm_perf_pmu_ids {
21 ARM_PERF_PMU_ID_XSCALE1 = 0,
22 ARM_PERF_PMU_ID_XSCALE2,
23 ARM_PERF_PMU_ID_V6,
24 ARM_PERF_PMU_ID_V6MP,
25 ARM_PERF_PMU_ID_CA8,
26 ARM_PERF_PMU_ID_CA9,
27 ARM_PERF_PMU_ID_CA5,
28 ARM_PERF_PMU_ID_CA15,
29 ARM_NUM_PMU_IDS,
32 extern enum arm_perf_pmu_ids
33 armpmu_get_pmu_id(void);
35 #endif /* __ARM_PERF_EVENT_H__ */