spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / include / asm / swab.h
blobb859d82e30cafb5489fdb0297319a570f8362df3
1 /*
2 * arch/arm/include/asm/byteorder.h
4 * ARM Endian-ness. In little endian mode, the data bus is connected such
5 * that byte accesses appear as:
6 * 0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31
7 * and word accesses (data or instruction) appear as:
8 * d0...d31
10 * When in big endian mode, byte accesses appear as:
11 * 0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7
12 * and word accesses (data or instruction) appear as:
13 * d0...d31
15 #ifndef __ASM_ARM_SWAB_H
16 #define __ASM_ARM_SWAB_H
18 #include <linux/compiler.h>
19 #include <linux/types.h>
21 #if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
22 # define __SWAB_64_THRU_32__
23 #endif
25 #if defined(__KERNEL__)
26 #if __LINUX_ARM_ARCH__ >= 6
28 static inline __attribute_const__ __u32 __arch_swahb32(__u32 x)
30 __asm__ ("rev16 %0, %1" : "=r" (x) : "r" (x));
31 return x;
33 #define __arch_swahb32 __arch_swahb32
34 #define __arch_swab16(x) ((__u16)__arch_swahb32(x))
36 static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
38 __asm__ ("rev %0, %1" : "=r" (x) : "r" (x));
39 return x;
41 #define __arch_swab32 __arch_swab32
43 #endif
44 #endif
46 #if !defined(__KERNEL__) || __LINUX_ARM_ARCH__ < 6
47 static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
49 __u32 t;
51 #ifndef __thumb__
52 if (!__builtin_constant_p(x)) {
54 * The compiler needs a bit of a hint here to always do the
55 * right thing and not screw it up to different degrees
56 * depending on the gcc version.
58 asm ("eor\t%0, %1, %1, ror #16" : "=r" (t) : "r" (x));
59 } else
60 #endif
61 t = x ^ ((x << 16) | (x >> 16)); /* eor r1,r0,r0,ror #16 */
63 x = (x << 24) | (x >> 8); /* mov r0,r0,ror #8 */
64 t &= ~0x00FF0000; /* bic r1,r1,#0x00FF0000 */
65 x ^= (t >> 8); /* eor r0,r0,r1,lsr #8 */
67 return x;
69 #define __arch_swab32 __arch_swab32
71 #endif
73 #endif