spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / include / asm / vfp.h
blobf4ab34fd4f72cc70ce0ece49eef7187f97e33763
1 /*
2 * arch/arm/include/asm/vfp.h
4 * VFP register definitions.
5 * First, the standard VFP set.
6 */
8 #define FPSID cr0
9 #define FPSCR cr1
10 #define MVFR1 cr6
11 #define MVFR0 cr7
12 #define FPEXC cr8
13 #define FPINST cr9
14 #define FPINST2 cr10
16 /* FPSID bits */
17 #define FPSID_IMPLEMENTER_BIT (24)
18 #define FPSID_IMPLEMENTER_MASK (0xff << FPSID_IMPLEMENTER_BIT)
19 #define FPSID_SOFTWARE (1<<23)
20 #define FPSID_FORMAT_BIT (21)
21 #define FPSID_FORMAT_MASK (0x3 << FPSID_FORMAT_BIT)
22 #define FPSID_NODOUBLE (1<<20)
23 #define FPSID_ARCH_BIT (16)
24 #define FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT)
25 #define FPSID_PART_BIT (8)
26 #define FPSID_PART_MASK (0xFF << FPSID_PART_BIT)
27 #define FPSID_VARIANT_BIT (4)
28 #define FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT)
29 #define FPSID_REV_BIT (0)
30 #define FPSID_REV_MASK (0xF << FPSID_REV_BIT)
32 /* FPEXC bits */
33 #define FPEXC_EX (1 << 31)
34 #define FPEXC_EN (1 << 30)
35 #define FPEXC_DEX (1 << 29)
36 #define FPEXC_FP2V (1 << 28)
37 #define FPEXC_VV (1 << 27)
38 #define FPEXC_TFV (1 << 26)
39 #define FPEXC_LENGTH_BIT (8)
40 #define FPEXC_LENGTH_MASK (7 << FPEXC_LENGTH_BIT)
41 #define FPEXC_IDF (1 << 7)
42 #define FPEXC_IXF (1 << 4)
43 #define FPEXC_UFF (1 << 3)
44 #define FPEXC_OFF (1 << 2)
45 #define FPEXC_DZF (1 << 1)
46 #define FPEXC_IOF (1 << 0)
47 #define FPEXC_TRAP_MASK (FPEXC_IDF|FPEXC_IXF|FPEXC_UFF|FPEXC_OFF|FPEXC_DZF|FPEXC_IOF)
49 /* FPSCR bits */
50 #define FPSCR_DEFAULT_NAN (1<<25)
51 #define FPSCR_FLUSHTOZERO (1<<24)
52 #define FPSCR_ROUND_NEAREST (0<<22)
53 #define FPSCR_ROUND_PLUSINF (1<<22)
54 #define FPSCR_ROUND_MINUSINF (2<<22)
55 #define FPSCR_ROUND_TOZERO (3<<22)
56 #define FPSCR_RMODE_BIT (22)
57 #define FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT)
58 #define FPSCR_STRIDE_BIT (20)
59 #define FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT)
60 #define FPSCR_LENGTH_BIT (16)
61 #define FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT)
62 #define FPSCR_IOE (1<<8)
63 #define FPSCR_DZE (1<<9)
64 #define FPSCR_OFE (1<<10)
65 #define FPSCR_UFE (1<<11)
66 #define FPSCR_IXE (1<<12)
67 #define FPSCR_IDE (1<<15)
68 #define FPSCR_IOC (1<<0)
69 #define FPSCR_DZC (1<<1)
70 #define FPSCR_OFC (1<<2)
71 #define FPSCR_UFC (1<<3)
72 #define FPSCR_IXC (1<<4)
73 #define FPSCR_IDC (1<<7)
75 /* MVFR0 bits */
76 #define MVFR0_A_SIMD_BIT (0)
77 #define MVFR0_A_SIMD_MASK (0xf << MVFR0_A_SIMD_BIT)
79 /* Bit patterns for decoding the packaged operation descriptors */
80 #define VFPOPDESC_LENGTH_BIT (9)
81 #define VFPOPDESC_LENGTH_MASK (0x07 << VFPOPDESC_LENGTH_BIT)
82 #define VFPOPDESC_UNUSED_BIT (24)
83 #define VFPOPDESC_UNUSED_MASK (0xFF << VFPOPDESC_UNUSED_BIT)
84 #define VFPOPDESC_OPDESC_MASK (~(VFPOPDESC_LENGTH_MASK | VFPOPDESC_UNUSED_MASK))