spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / include / asm / vfpmacros.h
blob3d5fc41ae8d38a7743b3bee9c55490135c19dcea
1 /*
2 * arch/arm/include/asm/vfpmacros.h
4 * Assembler-only file containing VFP macros and register definitions.
5 */
6 #include <asm/hwcap.h>
8 #include "vfp.h"
10 @ Macros to allow building with old toolkits (with no VFP support)
11 .macro VFPFMRX, rd, sysreg, cond
12 MRC\cond p10, 7, \rd, \sysreg, cr0, 0 @ FMRX \rd, \sysreg
13 .endm
15 .macro VFPFMXR, sysreg, rd, cond
16 MCR\cond p10, 7, \rd, \sysreg, cr0, 0 @ FMXR \sysreg, \rd
17 .endm
19 @ read all the working registers back into the VFP
20 .macro VFPFLDMIA, base, tmp
21 #if __LINUX_ARM_ARCH__ < 6
22 LDC p11, cr0, [\base],#33*4 @ FLDMIAX \base!, {d0-d15}
23 #else
24 LDC p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d0-d15}
25 #endif
26 #ifdef CONFIG_VFPv3
27 #if __LINUX_ARM_ARCH__ <= 6
28 ldr \tmp, =elf_hwcap @ may not have MVFR regs
29 ldr \tmp, [\tmp, #0]
30 tst \tmp, #HWCAP_VFPv3D16
31 ldceq p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31}
32 addne \base, \base, #32*4 @ step over unused register space
33 #else
34 VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0
35 and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field
36 cmp \tmp, #2 @ 32 x 64bit registers?
37 ldceql p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31}
38 addne \base, \base, #32*4 @ step over unused register space
39 #endif
40 #endif
41 .endm
43 @ write all the working registers out of the VFP
44 .macro VFPFSTMIA, base, tmp
45 #if __LINUX_ARM_ARCH__ < 6
46 STC p11, cr0, [\base],#33*4 @ FSTMIAX \base!, {d0-d15}
47 #else
48 STC p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d0-d15}
49 #endif
50 #ifdef CONFIG_VFPv3
51 #if __LINUX_ARM_ARCH__ <= 6
52 ldr \tmp, =elf_hwcap @ may not have MVFR regs
53 ldr \tmp, [\tmp, #0]
54 tst \tmp, #HWCAP_VFPv3D16
55 stceq p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31}
56 addne \base, \base, #32*4 @ step over unused register space
57 #else
58 VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0
59 and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field
60 cmp \tmp, #2 @ 32 x 64bit registers?
61 stceql p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31}
62 addne \base, \base, #32*4 @ step over unused register space
63 #endif
64 #endif
65 .endm