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spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / mach-at91 / at91rm9200_devices.c
blob97676bdae9983c98b79f77cb85dd88e833756789
1 /*
2 * arch/arm/mach-at91/at91rm9200_devices.c
3 *
4 * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
5 * Copyright (C) 2005 David Brownell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13 #include <asm/mach/arch.h>
14 #include <asm/mach/map.h>
15
16 #include <linux/dma-mapping.h>
17 #include <linux/gpio.h>
18 #include <linux/platform_device.h>
19 #include <linux/i2c-gpio.h>
20
21 #include <mach/board.h>
22 #include <mach/at91rm9200.h>
23 #include <mach/at91rm9200_mc.h>
24
25 #include "generic.h"
26
27
28 /* --------------------------------------------------------------------
29 * USB Host
30 * -------------------------------------------------------------------- */
31
32 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
33 static u64 ohci_dmamask = DMA_BIT_MASK(32);
34 static struct at91_usbh_data usbh_data;
35
36 static struct resource usbh_resources[] = {
37 [0] = {
38 .start = AT91RM9200_UHP_BASE,
39 .end = AT91RM9200_UHP_BASE + SZ_1M - 1,
40 .flags = IORESOURCE_MEM,
41 },
42 [1] = {
43 .start = AT91RM9200_ID_UHP,
44 .end = AT91RM9200_ID_UHP,
45 .flags = IORESOURCE_IRQ,
46 },
47 };
48
49 static struct platform_device at91rm9200_usbh_device = {
50 .name = "at91_ohci",
51 .id = -1,
52 .dev = {
53 .dma_mask = &ohci_dmamask,
54 .coherent_dma_mask = DMA_BIT_MASK(32),
55 .platform_data = &usbh_data,
56 },
57 .resource = usbh_resources,
58 .num_resources = ARRAY_SIZE(usbh_resources),
59 };
60
61 void __init at91_add_device_usbh(struct at91_usbh_data *data)
62 {
63 int i;
64
65 if (!data)
66 return;
67
68 /* Enable overcurrent notification */
69 for (i = 0; i < data->ports; i++) {
70 if (data->overcurrent_pin[i])
71 at91_set_gpio_input(data->overcurrent_pin[i], 1);
72 }
73
74 usbh_data = *data;
75 platform_device_register(&at91rm9200_usbh_device);
76 }
77 #else
78 void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
79 #endif
80
81
82 /* --------------------------------------------------------------------
83 * USB Device (Gadget)
84 * -------------------------------------------------------------------- */
85
86 #if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
87 static struct at91_udc_data udc_data;
88
89 static struct resource udc_resources[] = {
90 [0] = {
91 .start = AT91RM9200_BASE_UDP,
92 .end = AT91RM9200_BASE_UDP + SZ_16K - 1,
93 .flags = IORESOURCE_MEM,
94 },
95 [1] = {
96 .start = AT91RM9200_ID_UDP,
97 .end = AT91RM9200_ID_UDP,
98 .flags = IORESOURCE_IRQ,
99 },
100 };
101
102 static struct platform_device at91rm9200_udc_device = {
103 .name = "at91_udc",
104 .id = -1,
105 .dev = {
106 .platform_data = &udc_data,
107 },
108 .resource = udc_resources,
109 .num_resources = ARRAY_SIZE(udc_resources),
110 };
111
112 void __init at91_add_device_udc(struct at91_udc_data *data)
113 {
114 if (!data)
115 return;
116
117 if (gpio_is_valid(data->vbus_pin)) {
118 at91_set_gpio_input(data->vbus_pin, 0);
119 at91_set_deglitch(data->vbus_pin, 1);
120 }
121 if (gpio_is_valid(data->pullup_pin))
122 at91_set_gpio_output(data->pullup_pin, 0);
123
124 udc_data = *data;
125 platform_device_register(&at91rm9200_udc_device);
126 }
127 #else
128 void __init at91_add_device_udc(struct at91_udc_data *data) {}
129 #endif
130
131
132 /* --------------------------------------------------------------------
133 * Ethernet
134 * -------------------------------------------------------------------- */
135
136 #if defined(CONFIG_ARM_AT91_ETHER) || defined(CONFIG_ARM_AT91_ETHER_MODULE)
137 static u64 eth_dmamask = DMA_BIT_MASK(32);
138 static struct macb_platform_data eth_data;
139
140 static struct resource eth_resources[] = {
141 [0] = {
142 .start = AT91_VA_BASE_EMAC,
143 .end = AT91_VA_BASE_EMAC + SZ_16K - 1,
144 .flags = IORESOURCE_MEM,
145 },
146 [1] = {
147 .start = AT91RM9200_ID_EMAC,
148 .end = AT91RM9200_ID_EMAC,
149 .flags = IORESOURCE_IRQ,
150 },
151 };
152
153 static struct platform_device at91rm9200_eth_device = {
154 .name = "at91_ether",
155 .id = -1,
156 .dev = {
157 .dma_mask = &eth_dmamask,
158 .coherent_dma_mask = DMA_BIT_MASK(32),
159 .platform_data = &eth_data,
160 },
161 .resource = eth_resources,
162 .num_resources = ARRAY_SIZE(eth_resources),
163 };
164
165 void __init at91_add_device_eth(struct macb_platform_data *data)
166 {
167 if (!data)
168 return;
169
170 if (gpio_is_valid(data->phy_irq_pin)) {
171 at91_set_gpio_input(data->phy_irq_pin, 0);
172 at91_set_deglitch(data->phy_irq_pin, 1);
173 }
174
175 /* Pins used for MII and RMII */
176 at91_set_A_periph(AT91_PIN_PA16, 0); /* EMDIO */
177 at91_set_A_periph(AT91_PIN_PA15, 0); /* EMDC */
178 at91_set_A_periph(AT91_PIN_PA14, 0); /* ERXER */
179 at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
180 at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
181 at91_set_A_periph(AT91_PIN_PA11, 0); /* ECRS_ECRSDV */
182 at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX1 */
183 at91_set_A_periph(AT91_PIN_PA9, 0); /* ETX0 */
184 at91_set_A_periph(AT91_PIN_PA8, 0); /* ETXEN */
185 at91_set_A_periph(AT91_PIN_PA7, 0); /* ETXCK_EREFCK */
186
187 if (!data->is_rmii) {
188 at91_set_B_periph(AT91_PIN_PB19, 0); /* ERXCK */
189 at91_set_B_periph(AT91_PIN_PB18, 0); /* ECOL */
190 at91_set_B_periph(AT91_PIN_PB17, 0); /* ERXDV */
191 at91_set_B_periph(AT91_PIN_PB16, 0); /* ERX3 */
192 at91_set_B_periph(AT91_PIN_PB15, 0); /* ERX2 */
193 at91_set_B_periph(AT91_PIN_PB14, 0); /* ETXER */
194 at91_set_B_periph(AT91_PIN_PB13, 0); /* ETX3 */
195 at91_set_B_periph(AT91_PIN_PB12, 0); /* ETX2 */
196 }
197
198 eth_data = *data;
199 platform_device_register(&at91rm9200_eth_device);
200 }
201 #else
202 void __init at91_add_device_eth(struct macb_platform_data *data) {}
203 #endif
204
205
206 /* --------------------------------------------------------------------
207 * Compact Flash / PCMCIA
208 * -------------------------------------------------------------------- */
209
210 #if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
211 static struct at91_cf_data cf_data;
212
213 #define CF_BASE AT91_CHIPSELECT_4
214
215 static struct resource cf_resources[] = {
216 [0] = {
217 .start = CF_BASE,
218 /* ties up CS4, CS5 and CS6 */
219 .end = CF_BASE + (0x30000000 - 1),
220 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
221 },
222 };
223
224 static struct platform_device at91rm9200_cf_device = {
225 .name = "at91_cf",
226 .id = -1,
227 .dev = {
228 .platform_data = &cf_data,
229 },
230 .resource = cf_resources,
231 .num_resources = ARRAY_SIZE(cf_resources),
232 };
233
234 void __init at91_add_device_cf(struct at91_cf_data *data)
235 {
236 unsigned int csa;
237
238 if (!data)
239 return;
240
241 data->chipselect = 4; /* can only use EBI ChipSelect 4 */
242
243 /* CF takes over CS4, CS5, CS6 */
244 csa = at91_sys_read(AT91_EBI_CSA);
245 at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
246
247 /*
248 * Static memory controller timing adjustments.
249 * REVISIT: these timings are in terms of MCK cycles, so
250 * when MCK changes (cpufreq etc) so must these values...
251 */
252 at91_sys_write(AT91_SMC_CSR(4),
253 AT91_SMC_ACSS_STD
254 | AT91_SMC_DBW_16
255 | AT91_SMC_BAT
256 | AT91_SMC_WSEN
257 | AT91_SMC_NWS_(32) /* wait states */
258 | AT91_SMC_RWSETUP_(6) /* setup time */
259 | AT91_SMC_RWHOLD_(4) /* hold time */
260 );
261
262 /* input/irq */
263 if (gpio_is_valid(data->irq_pin)) {
264 at91_set_gpio_input(data->irq_pin, 1);
265 at91_set_deglitch(data->irq_pin, 1);
266 }
267 at91_set_gpio_input(data->det_pin, 1);
268 at91_set_deglitch(data->det_pin, 1);
269
270 /* outputs, initially off */
271 if (gpio_is_valid(data->vcc_pin))
272 at91_set_gpio_output(data->vcc_pin, 0);
273 at91_set_gpio_output(data->rst_pin, 0);
274
275 /* force poweron defaults for these pins ... */
276 at91_set_A_periph(AT91_PIN_PC9, 0); /* A25/CFRNW */
277 at91_set_A_periph(AT91_PIN_PC10, 0); /* NCS4/CFCS */
278 at91_set_A_periph(AT91_PIN_PC11, 0); /* NCS5/CFCE1 */
279 at91_set_A_periph(AT91_PIN_PC12, 0); /* NCS6/CFCE2 */
280
281 /* nWAIT is _not_ a default setting */
282 at91_set_A_periph(AT91_PIN_PC6, 1); /* nWAIT */
283
284 cf_data = *data;
285 platform_device_register(&at91rm9200_cf_device);
286 }
287 #else
288 void __init at91_add_device_cf(struct at91_cf_data *data) {}
289 #endif
290
291
292 /* --------------------------------------------------------------------
293 * MMC / SD
294 * -------------------------------------------------------------------- */
295
296 #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
297 static u64 mmc_dmamask = DMA_BIT_MASK(32);
298 static struct at91_mmc_data mmc_data;
299
300 static struct resource mmc_resources[] = {
301 [0] = {
302 .start = AT91RM9200_BASE_MCI,
303 .end = AT91RM9200_BASE_MCI + SZ_16K - 1,
304 .flags = IORESOURCE_MEM,
305 },
306 [1] = {
307 .start = AT91RM9200_ID_MCI,
308 .end = AT91RM9200_ID_MCI,
309 .flags = IORESOURCE_IRQ,
310 },
311 };
312
313 static struct platform_device at91rm9200_mmc_device = {
314 .name = "at91_mci",
315 .id = -1,
316 .dev = {
317 .dma_mask = &mmc_dmamask,
318 .coherent_dma_mask = DMA_BIT_MASK(32),
319 .platform_data = &mmc_data,
320 },
321 .resource = mmc_resources,
322 .num_resources = ARRAY_SIZE(mmc_resources),
323 };
324
325 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
326 {
327 if (!data)
328 return;
329
330 /* input/irq */
331 if (gpio_is_valid(data->det_pin)) {
332 at91_set_gpio_input(data->det_pin, 1);
333 at91_set_deglitch(data->det_pin, 1);
334 }
335 if (gpio_is_valid(data->wp_pin))
336 at91_set_gpio_input(data->wp_pin, 1);
337 if (gpio_is_valid(data->vcc_pin))
338 at91_set_gpio_output(data->vcc_pin, 0);
339
340 /* CLK */
341 at91_set_A_periph(AT91_PIN_PA27, 0);
342
343 if (data->slot_b) {
344 /* CMD */
345 at91_set_B_periph(AT91_PIN_PA8, 1);
346
347 /* DAT0, maybe DAT1..DAT3 */
348 at91_set_B_periph(AT91_PIN_PA9, 1);
349 if (data->wire4) {
350 at91_set_B_periph(AT91_PIN_PA10, 1);
351 at91_set_B_periph(AT91_PIN_PA11, 1);
352 at91_set_B_periph(AT91_PIN_PA12, 1);
353 }
354 } else {
355 /* CMD */
356 at91_set_A_periph(AT91_PIN_PA28, 1);
357
358 /* DAT0, maybe DAT1..DAT3 */
359 at91_set_A_periph(AT91_PIN_PA29, 1);
360 if (data->wire4) {
361 at91_set_B_periph(AT91_PIN_PB3, 1);
362 at91_set_B_periph(AT91_PIN_PB4, 1);
363 at91_set_B_periph(AT91_PIN_PB5, 1);
364 }
365 }
366
367 mmc_data = *data;
368 platform_device_register(&at91rm9200_mmc_device);
369 }
370 #else
371 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
372 #endif
373
374
375 /* --------------------------------------------------------------------
376 * NAND / SmartMedia
377 * -------------------------------------------------------------------- */
378
379 #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
380 static struct atmel_nand_data nand_data;
381
382 #define NAND_BASE AT91_CHIPSELECT_3
383
384 static struct resource nand_resources[] = {
385 {
386 .start = NAND_BASE,
387 .end = NAND_BASE + SZ_256M - 1,
388 .flags = IORESOURCE_MEM,
389 }
390 };
391
392 static struct platform_device at91rm9200_nand_device = {
393 .name = "atmel_nand",
394 .id = -1,
395 .dev = {
396 .platform_data = &nand_data,
397 },
398 .resource = nand_resources,
399 .num_resources = ARRAY_SIZE(nand_resources),
400 };
401
402 void __init at91_add_device_nand(struct atmel_nand_data *data)
403 {
404 unsigned int csa;
405
406 if (!data)
407 return;
408
409 /* enable the address range of CS3 */
410 csa = at91_sys_read(AT91_EBI_CSA);
411 at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
412
413 /* set the bus interface characteristics */
414 at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
415 | AT91_SMC_NWS_(5)
416 | AT91_SMC_TDF_(1)
417 | AT91_SMC_RWSETUP_(0) /* tDS Data Set up Time 30 - ns */
418 | AT91_SMC_RWHOLD_(1) /* tDH Data Hold Time 20 - ns */
419 );
420
421 /* enable pin */
422 if (gpio_is_valid(data->enable_pin))
423 at91_set_gpio_output(data->enable_pin, 1);
424
425 /* ready/busy pin */
426 if (gpio_is_valid(data->rdy_pin))
427 at91_set_gpio_input(data->rdy_pin, 1);
428
429 /* card detect pin */
430 if (gpio_is_valid(data->det_pin))
431 at91_set_gpio_input(data->det_pin, 1);
432
433 at91_set_A_periph(AT91_PIN_PC1, 0); /* SMOE */
434 at91_set_A_periph(AT91_PIN_PC3, 0); /* SMWE */
435
436 nand_data = *data;
437 platform_device_register(&at91rm9200_nand_device);
438 }
439 #else
440 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
441 #endif
442
443
444 /* --------------------------------------------------------------------
445 * TWI (i2c)
446 * -------------------------------------------------------------------- */
447
448 /*
449 * Prefer the GPIO code since the TWI controller isn't robust
450 * (gets overruns and underruns under load) and can only issue
451 * repeated STARTs in one scenario (the driver doesn't yet handle them).
452 */
453 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
454
455 static struct i2c_gpio_platform_data pdata = {
456 .sda_pin = AT91_PIN_PA25,
457 .sda_is_open_drain = 1,
458 .scl_pin = AT91_PIN_PA26,
459 .scl_is_open_drain = 1,
460 .udelay = 2, /* ~100 kHz */
461 };
462
463 static struct platform_device at91rm9200_twi_device = {
464 .name = "i2c-gpio",
465 .id = -1,
466 .dev.platform_data = &pdata,
467 };
468
469 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
470 {
471 at91_set_GPIO_periph(AT91_PIN_PA25, 1); /* TWD (SDA) */
472 at91_set_multi_drive(AT91_PIN_PA25, 1);
473
474 at91_set_GPIO_periph(AT91_PIN_PA26, 1); /* TWCK (SCL) */
475 at91_set_multi_drive(AT91_PIN_PA26, 1);
476
477 i2c_register_board_info(0, devices, nr_devices);
478 platform_device_register(&at91rm9200_twi_device);
479 }
480
481 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
482
483 static struct resource twi_resources[] = {
484 [0] = {
485 .start = AT91RM9200_BASE_TWI,
486 .end = AT91RM9200_BASE_TWI + SZ_16K - 1,
487 .flags = IORESOURCE_MEM,
488 },
489 [1] = {
490 .start = AT91RM9200_ID_TWI,
491 .end = AT91RM9200_ID_TWI,
492 .flags = IORESOURCE_IRQ,
493 },
494 };
495
496 static struct platform_device at91rm9200_twi_device = {
497 .name = "at91_i2c",
498 .id = -1,
499 .resource = twi_resources,
500 .num_resources = ARRAY_SIZE(twi_resources),
501 };
502
503 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
504 {
505 /* pins used for TWI interface */
506 at91_set_A_periph(AT91_PIN_PA25, 0); /* TWD */
507 at91_set_multi_drive(AT91_PIN_PA25, 1);
508
509 at91_set_A_periph(AT91_PIN_PA26, 0); /* TWCK */
510 at91_set_multi_drive(AT91_PIN_PA26, 1);
511
512 i2c_register_board_info(0, devices, nr_devices);
513 platform_device_register(&at91rm9200_twi_device);
514 }
515 #else
516 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
517 #endif
518
519
520 /* --------------------------------------------------------------------
521 * SPI
522 * -------------------------------------------------------------------- */
523
524 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
525 static u64 spi_dmamask = DMA_BIT_MASK(32);
526
527 static struct resource spi_resources[] = {
528 [0] = {
529 .start = AT91RM9200_BASE_SPI,
530 .end = AT91RM9200_BASE_SPI + SZ_16K - 1,
531 .flags = IORESOURCE_MEM,
532 },
533 [1] = {
534 .start = AT91RM9200_ID_SPI,
535 .end = AT91RM9200_ID_SPI,
536 .flags = IORESOURCE_IRQ,
537 },
538 };
539
540 static struct platform_device at91rm9200_spi_device = {
541 .name = "atmel_spi",
542 .id = 0,
543 .dev = {
544 .dma_mask = &spi_dmamask,
545 .coherent_dma_mask = DMA_BIT_MASK(32),
546 },
547 .resource = spi_resources,
548 .num_resources = ARRAY_SIZE(spi_resources),
549 };
550
551 static const unsigned spi_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
552
553 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
554 {
555 int i;
556 unsigned long cs_pin;
557
558 at91_set_A_periph(AT91_PIN_PA0, 0); /* MISO */
559 at91_set_A_periph(AT91_PIN_PA1, 0); /* MOSI */
560 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPCK */
561
562 /* Enable SPI chip-selects */
563 for (i = 0; i < nr_devices; i++) {
564 if (devices[i].controller_data)
565 cs_pin = (unsigned long) devices[i].controller_data;
566 else
567 cs_pin = spi_standard_cs[devices[i].chip_select];
568
569 if (devices[i].chip_select == 0) /* for CS0 errata */
570 at91_set_A_periph(cs_pin, 0);
571 else
572 at91_set_gpio_output(cs_pin, 1);
573
574
575 /* pass chip-select pin to driver */
576 devices[i].controller_data = (void *) cs_pin;
577 }
578
579 spi_register_board_info(devices, nr_devices);
580 platform_device_register(&at91rm9200_spi_device);
581 }
582 #else
583 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
584 #endif
585
586
587 /* --------------------------------------------------------------------
588 * Timer/Counter blocks
589 * -------------------------------------------------------------------- */
590
591 #ifdef CONFIG_ATMEL_TCLIB
592
593 static struct resource tcb0_resources[] = {
594 [0] = {
595 .start = AT91RM9200_BASE_TCB0,
596 .end = AT91RM9200_BASE_TCB0 + SZ_16K - 1,
597 .flags = IORESOURCE_MEM,
598 },
599 [1] = {
600 .start = AT91RM9200_ID_TC0,
601 .end = AT91RM9200_ID_TC0,
602 .flags = IORESOURCE_IRQ,
603 },
604 [2] = {
605 .start = AT91RM9200_ID_TC1,
606 .end = AT91RM9200_ID_TC1,
607 .flags = IORESOURCE_IRQ,
608 },
609 [3] = {
610 .start = AT91RM9200_ID_TC2,
611 .end = AT91RM9200_ID_TC2,
612 .flags = IORESOURCE_IRQ,
613 },
614 };
615
616 static struct platform_device at91rm9200_tcb0_device = {
617 .name = "atmel_tcb",
618 .id = 0,
619 .resource = tcb0_resources,
620 .num_resources = ARRAY_SIZE(tcb0_resources),
621 };
622
623 static struct resource tcb1_resources[] = {
624 [0] = {
625 .start = AT91RM9200_BASE_TCB1,
626 .end = AT91RM9200_BASE_TCB1 + SZ_16K - 1,
627 .flags = IORESOURCE_MEM,
628 },
629 [1] = {
630 .start = AT91RM9200_ID_TC3,
631 .end = AT91RM9200_ID_TC3,
632 .flags = IORESOURCE_IRQ,
633 },
634 [2] = {
635 .start = AT91RM9200_ID_TC4,
636 .end = AT91RM9200_ID_TC4,
637 .flags = IORESOURCE_IRQ,
638 },
639 [3] = {
640 .start = AT91RM9200_ID_TC5,
641 .end = AT91RM9200_ID_TC5,
642 .flags = IORESOURCE_IRQ,
643 },
644 };
645
646 static struct platform_device at91rm9200_tcb1_device = {
647 .name = "atmel_tcb",
648 .id = 1,
649 .resource = tcb1_resources,
650 .num_resources = ARRAY_SIZE(tcb1_resources),
651 };
652
653 static void __init at91_add_device_tc(void)
654 {
655 platform_device_register(&at91rm9200_tcb0_device);
656 platform_device_register(&at91rm9200_tcb1_device);
657 }
658 #else
659 static void __init at91_add_device_tc(void) { }
660 #endif
661
662
663 /* --------------------------------------------------------------------
664 * RTC
665 * -------------------------------------------------------------------- */
666
667 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
668 static struct resource rtc_resources[] = {
669 [0] = {
670 .start = AT91RM9200_BASE_RTC,
671 .end = AT91RM9200_BASE_RTC + SZ_256 - 1,
672 .flags = IORESOURCE_MEM,
673 },
674 [1] = {
675 .start = AT91_ID_SYS,
676 .end = AT91_ID_SYS,
677 .flags = IORESOURCE_IRQ,
678 },
679 };
680
681 static struct platform_device at91rm9200_rtc_device = {
682 .name = "at91_rtc",
683 .id = -1,
684 .resource = rtc_resources,
685 .num_resources = ARRAY_SIZE(rtc_resources),
686 };
687
688 static void __init at91_add_device_rtc(void)
689 {
690 platform_device_register(&at91rm9200_rtc_device);
691 }
692 #else
693 static void __init at91_add_device_rtc(void) {}
694 #endif
695
696
697 /* --------------------------------------------------------------------
698 * Watchdog
699 * -------------------------------------------------------------------- */
700
701 #if defined(CONFIG_AT91RM9200_WATCHDOG) || defined(CONFIG_AT91RM9200_WATCHDOG_MODULE)
702 static struct platform_device at91rm9200_wdt_device = {
703 .name = "at91_wdt",
704 .id = -1,
705 .num_resources = 0,
706 };
707
708 static void __init at91_add_device_watchdog(void)
709 {
710 platform_device_register(&at91rm9200_wdt_device);
711 }
712 #else
713 static void __init at91_add_device_watchdog(void) {}
714 #endif
715
716
717 /* --------------------------------------------------------------------
718 * SSC -- Synchronous Serial Controller
719 * -------------------------------------------------------------------- */
720
721 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
722 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
723
724 static struct resource ssc0_resources[] = {
725 [0] = {
726 .start = AT91RM9200_BASE_SSC0,
727 .end = AT91RM9200_BASE_SSC0 + SZ_16K - 1,
728 .flags = IORESOURCE_MEM,
729 },
730 [1] = {
731 .start = AT91RM9200_ID_SSC0,
732 .end = AT91RM9200_ID_SSC0,
733 .flags = IORESOURCE_IRQ,
734 },
735 };
736
737 static struct platform_device at91rm9200_ssc0_device = {
738 .name = "ssc",
739 .id = 0,
740 .dev = {
741 .dma_mask = &ssc0_dmamask,
742 .coherent_dma_mask = DMA_BIT_MASK(32),
743 },
744 .resource = ssc0_resources,
745 .num_resources = ARRAY_SIZE(ssc0_resources),
746 };
747
748 static inline void configure_ssc0_pins(unsigned pins)
749 {
750 if (pins & ATMEL_SSC_TF)
751 at91_set_A_periph(AT91_PIN_PB0, 1);
752 if (pins & ATMEL_SSC_TK)
753 at91_set_A_periph(AT91_PIN_PB1, 1);
754 if (pins & ATMEL_SSC_TD)
755 at91_set_A_periph(AT91_PIN_PB2, 1);
756 if (pins & ATMEL_SSC_RD)
757 at91_set_A_periph(AT91_PIN_PB3, 1);
758 if (pins & ATMEL_SSC_RK)
759 at91_set_A_periph(AT91_PIN_PB4, 1);
760 if (pins & ATMEL_SSC_RF)
761 at91_set_A_periph(AT91_PIN_PB5, 1);
762 }
763
764 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
765
766 static struct resource ssc1_resources[] = {
767 [0] = {
768 .start = AT91RM9200_BASE_SSC1,
769 .end = AT91RM9200_BASE_SSC1 + SZ_16K - 1,
770 .flags = IORESOURCE_MEM,
771 },
772 [1] = {
773 .start = AT91RM9200_ID_SSC1,
774 .end = AT91RM9200_ID_SSC1,
775 .flags = IORESOURCE_IRQ,
776 },
777 };
778
779 static struct platform_device at91rm9200_ssc1_device = {
780 .name = "ssc",
781 .id = 1,
782 .dev = {
783 .dma_mask = &ssc1_dmamask,
784 .coherent_dma_mask = DMA_BIT_MASK(32),
785 },
786 .resource = ssc1_resources,
787 .num_resources = ARRAY_SIZE(ssc1_resources),
788 };
789
790 static inline void configure_ssc1_pins(unsigned pins)
791 {
792 if (pins & ATMEL_SSC_TF)
793 at91_set_A_periph(AT91_PIN_PB6, 1);
794 if (pins & ATMEL_SSC_TK)
795 at91_set_A_periph(AT91_PIN_PB7, 1);
796 if (pins & ATMEL_SSC_TD)
797 at91_set_A_periph(AT91_PIN_PB8, 1);
798 if (pins & ATMEL_SSC_RD)
799 at91_set_A_periph(AT91_PIN_PB9, 1);
800 if (pins & ATMEL_SSC_RK)
801 at91_set_A_periph(AT91_PIN_PB10, 1);
802 if (pins & ATMEL_SSC_RF)
803 at91_set_A_periph(AT91_PIN_PB11, 1);
804 }
805
806 static u64 ssc2_dmamask = DMA_BIT_MASK(32);
807
808 static struct resource ssc2_resources[] = {
809 [0] = {
810 .start = AT91RM9200_BASE_SSC2,
811 .end = AT91RM9200_BASE_SSC2 + SZ_16K - 1,
812 .flags = IORESOURCE_MEM,
813 },
814 [1] = {
815 .start = AT91RM9200_ID_SSC2,
816 .end = AT91RM9200_ID_SSC2,
817 .flags = IORESOURCE_IRQ,
818 },
819 };
820
821 static struct platform_device at91rm9200_ssc2_device = {
822 .name = "ssc",
823 .id = 2,
824 .dev = {
825 .dma_mask = &ssc2_dmamask,
826 .coherent_dma_mask = DMA_BIT_MASK(32),
827 },
828 .resource = ssc2_resources,
829 .num_resources = ARRAY_SIZE(ssc2_resources),
830 };
831
832 static inline void configure_ssc2_pins(unsigned pins)
833 {
834 if (pins & ATMEL_SSC_TF)
835 at91_set_A_periph(AT91_PIN_PB12, 1);
836 if (pins & ATMEL_SSC_TK)
837 at91_set_A_periph(AT91_PIN_PB13, 1);
838 if (pins & ATMEL_SSC_TD)
839 at91_set_A_periph(AT91_PIN_PB14, 1);
840 if (pins & ATMEL_SSC_RD)
841 at91_set_A_periph(AT91_PIN_PB15, 1);
842 if (pins & ATMEL_SSC_RK)
843 at91_set_A_periph(AT91_PIN_PB16, 1);
844 if (pins & ATMEL_SSC_RF)
845 at91_set_A_periph(AT91_PIN_PB17, 1);
846 }
847
848 /*
849 * SSC controllers are accessed through library code, instead of any
850 * kind of all-singing/all-dancing driver. For example one could be
851 * used by a particular I2S audio codec's driver, while another one
852 * on the same system might be used by a custom data capture driver.
853 */
854 void __init at91_add_device_ssc(unsigned id, unsigned pins)
855 {
856 struct platform_device *pdev;
857
858 /*
859 * NOTE: caller is responsible for passing information matching
860 * "pins" to whatever will be using each particular controller.
861 */
862 switch (id) {
863 case AT91RM9200_ID_SSC0:
864 pdev = &at91rm9200_ssc0_device;
865 configure_ssc0_pins(pins);
866 break;
867 case AT91RM9200_ID_SSC1:
868 pdev = &at91rm9200_ssc1_device;
869 configure_ssc1_pins(pins);
870 break;
871 case AT91RM9200_ID_SSC2:
872 pdev = &at91rm9200_ssc2_device;
873 configure_ssc2_pins(pins);
874 break;
875 default:
876 return;
877 }
878
879 platform_device_register(pdev);
880 }
881
882 #else
883 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
884 #endif
885
886
887 /* --------------------------------------------------------------------
888 * UART
889 * -------------------------------------------------------------------- */
890
891 #if defined(CONFIG_SERIAL_ATMEL)
892 static struct resource dbgu_resources[] = {
893 [0] = {
894 .start = AT91RM9200_BASE_DBGU,
895 .end = AT91RM9200_BASE_DBGU + SZ_512 - 1,
896 .flags = IORESOURCE_MEM,
897 },
898 [1] = {
899 .start = AT91_ID_SYS,
900 .end = AT91_ID_SYS,
901 .flags = IORESOURCE_IRQ,
902 },
903 };
904
905 static struct atmel_uart_data dbgu_data = {
906 .use_dma_tx = 0,
907 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
908 };
909
910 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
911
912 static struct platform_device at91rm9200_dbgu_device = {
913 .name = "atmel_usart",
914 .id = 0,
915 .dev = {
916 .dma_mask = &dbgu_dmamask,
917 .coherent_dma_mask = DMA_BIT_MASK(32),
918 .platform_data = &dbgu_data,
919 },
920 .resource = dbgu_resources,
921 .num_resources = ARRAY_SIZE(dbgu_resources),
922 };
923
924 static inline void configure_dbgu_pins(void)
925 {
926 at91_set_A_periph(AT91_PIN_PA30, 0); /* DRXD */
927 at91_set_A_periph(AT91_PIN_PA31, 1); /* DTXD */
928 }
929
930 static struct resource uart0_resources[] = {
931 [0] = {
932 .start = AT91RM9200_BASE_US0,
933 .end = AT91RM9200_BASE_US0 + SZ_16K - 1,
934 .flags = IORESOURCE_MEM,
935 },
936 [1] = {
937 .start = AT91RM9200_ID_US0,
938 .end = AT91RM9200_ID_US0,
939 .flags = IORESOURCE_IRQ,
940 },
941 };
942
943 static struct atmel_uart_data uart0_data = {
944 .use_dma_tx = 1,
945 .use_dma_rx = 1,
946 };
947
948 static u64 uart0_dmamask = DMA_BIT_MASK(32);
949
950 static struct platform_device at91rm9200_uart0_device = {
951 .name = "atmel_usart",
952 .id = 1,
953 .dev = {
954 .dma_mask = &uart0_dmamask,
955 .coherent_dma_mask = DMA_BIT_MASK(32),
956 .platform_data = &uart0_data,
957 },
958 .resource = uart0_resources,
959 .num_resources = ARRAY_SIZE(uart0_resources),
960 };
961
962 static inline void configure_usart0_pins(unsigned pins)
963 {
964 at91_set_A_periph(AT91_PIN_PA17, 1); /* TXD0 */
965 at91_set_A_periph(AT91_PIN_PA18, 0); /* RXD0 */
966
967 if (pins & ATMEL_UART_CTS)
968 at91_set_A_periph(AT91_PIN_PA20, 0); /* CTS0 */
969
970 if (pins & ATMEL_UART_RTS) {
971 /*
972 * AT91RM9200 Errata #39 - RTS0 is not internally connected to PA21.
973 * We need to drive the pin manually. Default is off (RTS is active low).
974 */
975 at91_set_gpio_output(AT91_PIN_PA21, 1);
976 }
977 }
978
979 static struct resource uart1_resources[] = {
980 [0] = {
981 .start = AT91RM9200_BASE_US1,
982 .end = AT91RM9200_BASE_US1 + SZ_16K - 1,
983 .flags = IORESOURCE_MEM,
984 },
985 [1] = {
986 .start = AT91RM9200_ID_US1,
987 .end = AT91RM9200_ID_US1,
988 .flags = IORESOURCE_IRQ,
989 },
990 };
991
992 static struct atmel_uart_data uart1_data = {
993 .use_dma_tx = 1,
994 .use_dma_rx = 1,
995 };
996
997 static u64 uart1_dmamask = DMA_BIT_MASK(32);
998
999 static struct platform_device at91rm9200_uart1_device = {
1000 .name = "atmel_usart",
1001 .id = 2,
1002 .dev = {
1003 .dma_mask = &uart1_dmamask,
1004 .coherent_dma_mask = DMA_BIT_MASK(32),
1005 .platform_data = &uart1_data,
1006 },
1007 .resource = uart1_resources,
1008 .num_resources = ARRAY_SIZE(uart1_resources),
1009 };
1010
1011 static inline void configure_usart1_pins(unsigned pins)
1012 {
1013 at91_set_A_periph(AT91_PIN_PB20, 1); /* TXD1 */
1014 at91_set_A_periph(AT91_PIN_PB21, 0); /* RXD1 */
1015
1016 if (pins & ATMEL_UART_RI)
1017 at91_set_A_periph(AT91_PIN_PB18, 0); /* RI1 */
1018 if (pins & ATMEL_UART_DTR)
1019 at91_set_A_periph(AT91_PIN_PB19, 0); /* DTR1 */
1020 if (pins & ATMEL_UART_DCD)
1021 at91_set_A_periph(AT91_PIN_PB23, 0); /* DCD1 */
1022 if (pins & ATMEL_UART_CTS)
1023 at91_set_A_periph(AT91_PIN_PB24, 0); /* CTS1 */
1024 if (pins & ATMEL_UART_DSR)
1025 at91_set_A_periph(AT91_PIN_PB25, 0); /* DSR1 */
1026 if (pins & ATMEL_UART_RTS)
1027 at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS1 */
1028 }
1029
1030 static struct resource uart2_resources[] = {
1031 [0] = {
1032 .start = AT91RM9200_BASE_US2,
1033 .end = AT91RM9200_BASE_US2 + SZ_16K - 1,
1034 .flags = IORESOURCE_MEM,
1035 },
1036 [1] = {
1037 .start = AT91RM9200_ID_US2,
1038 .end = AT91RM9200_ID_US2,
1039 .flags = IORESOURCE_IRQ,
1040 },
1041 };
1042
1043 static struct atmel_uart_data uart2_data = {
1044 .use_dma_tx = 1,
1045 .use_dma_rx = 1,
1046 };
1047
1048 static u64 uart2_dmamask = DMA_BIT_MASK(32);
1049
1050 static struct platform_device at91rm9200_uart2_device = {
1051 .name = "atmel_usart",
1052 .id = 3,
1053 .dev = {
1054 .dma_mask = &uart2_dmamask,
1055 .coherent_dma_mask = DMA_BIT_MASK(32),
1056 .platform_data = &uart2_data,
1057 },
1058 .resource = uart2_resources,
1059 .num_resources = ARRAY_SIZE(uart2_resources),
1060 };
1061
1062 static inline void configure_usart2_pins(unsigned pins)
1063 {
1064 at91_set_A_periph(AT91_PIN_PA22, 0); /* RXD2 */
1065 at91_set_A_periph(AT91_PIN_PA23, 1); /* TXD2 */
1066
1067 if (pins & ATMEL_UART_CTS)
1068 at91_set_B_periph(AT91_PIN_PA30, 0); /* CTS2 */
1069 if (pins & ATMEL_UART_RTS)
1070 at91_set_B_periph(AT91_PIN_PA31, 0); /* RTS2 */
1071 }
1072
1073 static struct resource uart3_resources[] = {
1074 [0] = {
1075 .start = AT91RM9200_BASE_US3,
1076 .end = AT91RM9200_BASE_US3 + SZ_16K - 1,
1077 .flags = IORESOURCE_MEM,
1078 },
1079 [1] = {
1080 .start = AT91RM9200_ID_US3,
1081 .end = AT91RM9200_ID_US3,
1082 .flags = IORESOURCE_IRQ,
1083 },
1084 };
1085
1086 static struct atmel_uart_data uart3_data = {
1087 .use_dma_tx = 1,
1088 .use_dma_rx = 1,
1089 };
1090
1091 static u64 uart3_dmamask = DMA_BIT_MASK(32);
1092
1093 static struct platform_device at91rm9200_uart3_device = {
1094 .name = "atmel_usart",
1095 .id = 4,
1096 .dev = {
1097 .dma_mask = &uart3_dmamask,
1098 .coherent_dma_mask = DMA_BIT_MASK(32),
1099 .platform_data = &uart3_data,
1100 },
1101 .resource = uart3_resources,
1102 .num_resources = ARRAY_SIZE(uart3_resources),
1103 };
1104
1105 static inline void configure_usart3_pins(unsigned pins)
1106 {
1107 at91_set_B_periph(AT91_PIN_PA5, 1); /* TXD3 */
1108 at91_set_B_periph(AT91_PIN_PA6, 0); /* RXD3 */
1109
1110 if (pins & ATMEL_UART_CTS)
1111 at91_set_B_periph(AT91_PIN_PB1, 0); /* CTS3 */
1112 if (pins & ATMEL_UART_RTS)
1113 at91_set_B_periph(AT91_PIN_PB0, 0); /* RTS3 */
1114 }
1115
1116 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1117 struct platform_device *atmel_default_console_device; /* the serial console device */
1118
1119 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1120 {
1121 struct platform_device *pdev;
1122 struct atmel_uart_data *pdata;
1123
1124 switch (id) {
1125 case 0: /* DBGU */
1126 pdev = &at91rm9200_dbgu_device;
1127 configure_dbgu_pins();
1128 break;
1129 case AT91RM9200_ID_US0:
1130 pdev = &at91rm9200_uart0_device;
1131 configure_usart0_pins(pins);
1132 break;
1133 case AT91RM9200_ID_US1:
1134 pdev = &at91rm9200_uart1_device;
1135 configure_usart1_pins(pins);
1136 break;
1137 case AT91RM9200_ID_US2:
1138 pdev = &at91rm9200_uart2_device;
1139 configure_usart2_pins(pins);
1140 break;
1141 case AT91RM9200_ID_US3:
1142 pdev = &at91rm9200_uart3_device;
1143 configure_usart3_pins(pins);
1144 break;
1145 default:
1146 return;
1147 }
1148 pdata = pdev->dev.platform_data;
1149 pdata->num = portnr; /* update to mapped ID */
1150
1151 if (portnr < ATMEL_MAX_UART)
1152 at91_uarts[portnr] = pdev;
1153 }
1154
1155 void __init at91_set_serial_console(unsigned portnr)
1156 {
1157 if (portnr < ATMEL_MAX_UART) {
1158 atmel_default_console_device = at91_uarts[portnr];
1159 at91rm9200_set_console_clock(at91_uarts[portnr]->id);
1160 }
1161 }
1162
1163 void __init at91_add_device_serial(void)
1164 {
1165 int i;
1166
1167 for (i = 0; i < ATMEL_MAX_UART; i++) {
1168 if (at91_uarts[i])
1169 platform_device_register(at91_uarts[i]);
1170 }
1171
1172 if (!atmel_default_console_device)
1173 printk(KERN_INFO "AT91: No default serial console defined.\n");
1174 }
1175 #else
1176 void __init __deprecated at91_init_serial(struct at91_uart_config *config) {}
1177 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1178 void __init at91_set_serial_console(unsigned portnr) {}
1179 void __init at91_add_device_serial(void) {}
1180 #endif
1181
1182
1183 /* -------------------------------------------------------------------- */
1184
1185 /*
1186 * These devices are always present and don't need any board-specific
1187 * setup.
1188 */
1189 static int __init at91_add_standard_devices(void)
1190 {
1191 at91_add_device_rtc();
1192 at91_add_device_watchdog();
1193 at91_add_device_tc();
1194 return 0;
1195 }
1196
1197 arch_initcall(at91_add_standard_devices);