arch/arm/mach-at91/at91rm9200_time.c

   1 /*
   2  * linux/arch/arm/mach-at91/at91rm9200_time.c
   3  *
   4  *  Copyright (C) 2003 SAN People
   5  *  Copyright (C) 2003 ATMEL
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irq.h>
  25 #include <linux/clockchips.h>
  26
  27 #include <asm/mach/time.h>
  28
  29 #include <mach/at91_st.h>
  30
  31 static unsigned long last_crtr;
  32 static u32 irqmask;
  33 static struct clock_event_device clkevt;
  34
  35 #define RM9200_TIMER_LATCH      ((AT91_SLOW_CLOCK + HZ/2) / HZ)
  36
  37 /*
  38  * The ST_CRTR is updated asynchronously to the master clock ... but
  39  * the updates as seen by the CPU don't seem to be strictly monotonic.
  40  * Waiting until we read the same value twice avoids glitching.
  41  */
  42 static inline unsigned long read_CRTR(void)
  43 {
  44         unsigned long x1, x2;
  45
  46         x1 = at91_sys_read(AT91_ST_CRTR);
  47         do {
  48                 x2 = at91_sys_read(AT91_ST_CRTR);
  49                 if (x1 == x2)
  50                         break;
  51                 x1 = x2;
  52         } while (1);
  53         return x1;
  54 }
  55
  56 /*
  57  * IRQ handler for the timer.
  58  */
  59 static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
  60 {
  61         u32     sr = at91_sys_read(AT91_ST_SR) & irqmask;
  62
  63         /*
  64          * irqs should be disabled here, but as the irq is shared they are only
  65          * guaranteed to be off if the timer irq is registered first.
  66          */
  67         WARN_ON_ONCE(!irqs_disabled());
  68
  69         /* simulate "oneshot" timer with alarm */
  70         if (sr & AT91_ST_ALMS) {
  71                 clkevt.event_handler(&clkevt);
  72                 return IRQ_HANDLED;
  73         }
  74
  75         /* periodic mode should handle delayed ticks */
  76         if (sr & AT91_ST_PITS) {
  77                 u32     crtr = read_CRTR();
  78
  79                 while (((crtr - last_crtr) & AT91_ST_CRTV) >= RM9200_TIMER_LATCH) {
  80                         last_crtr += RM9200_TIMER_LATCH;
  81                         clkevt.event_handler(&clkevt);
  82                 }
  83                 return IRQ_HANDLED;
  84         }
  85
  86         /* this irq is shared ... */
  87         return IRQ_NONE;
  88 }
  89
  90 static struct irqaction at91rm9200_timer_irq = {
  91         .name           = "at91_tick",
  92         .flags          = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
  93         .handler        = at91rm9200_timer_interrupt
  94 };
  95
  96 static cycle_t read_clk32k(struct clocksource *cs)
  97 {
  98         return read_CRTR();
  99 }
 100
 101 static struct clocksource clk32k = {
 102         .name           = "32k_counter",
 103         .rating         = 150,
 104         .read           = read_clk32k,
 105         .mask           = CLOCKSOURCE_MASK(20),
 106         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 107 };
 108
 109 static void
 110 clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
 111 {
 112         /* Disable and flush pending timer interrupts */
 113         at91_sys_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
 114         (void) at91_sys_read(AT91_ST_SR);
 115
 116         last_crtr = read_CRTR();
 117         switch (mode) {
 118         case CLOCK_EVT_MODE_PERIODIC:
 119                 /* PIT for periodic irqs; fixed rate of 1/HZ */
 120                 irqmask = AT91_ST_PITS;
 121                 at91_sys_write(AT91_ST_PIMR, RM9200_TIMER_LATCH);
 122                 break;
 123         case CLOCK_EVT_MODE_ONESHOT:
 124                 /* ALM for oneshot irqs, set by next_event()
 125                  * before 32 seconds have passed
 126                  */
 127                 irqmask = AT91_ST_ALMS;
 128                 at91_sys_write(AT91_ST_RTAR, last_crtr);
 129                 break;
 130         case CLOCK_EVT_MODE_SHUTDOWN:
 131         case CLOCK_EVT_MODE_UNUSED:
 132         case CLOCK_EVT_MODE_RESUME:
 133                 irqmask = 0;
 134                 break;
 135         }
 136         at91_sys_write(AT91_ST_IER, irqmask);
 137 }
 138
 139 static int
 140 clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
 141 {
 142         u32             alm;
 143         int             status = 0;
 144
 145         BUG_ON(delta < 2);
 146
 147         /* The alarm IRQ uses absolute time (now+delta), not the relative
 148          * time (delta) in our calling convention.  Like all clockevents
 149          * using such "match" hardware, we have a race to defend against.
 150          *
 151          * Our defense here is to have set up the clockevent device so the
 152          * delta is at least two.  That way we never end up writing RTAR
 153          * with the value then held in CRTR ... which would mean the match
 154          * wouldn't trigger until 32 seconds later, after CRTR wraps.
 155          */
 156         alm = read_CRTR();
 157
 158         /* Cancel any pending alarm; flush any pending IRQ */
 159         at91_sys_write(AT91_ST_RTAR, alm);
 160         (void) at91_sys_read(AT91_ST_SR);
 161
 162         /* Schedule alarm by writing RTAR. */
 163         alm += delta;
 164         at91_sys_write(AT91_ST_RTAR, alm);
 165
 166         return status;
 167 }
 168
 169 static struct clock_event_device clkevt = {
 170         .name           = "at91_tick",
 171         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 172         .shift          = 32,
 173         .rating         = 150,
 174         .set_next_event = clkevt32k_next_event,
 175         .set_mode       = clkevt32k_mode,
 176 };
 177
 178 /*
 179  * ST (system timer) module supports both clockevents and clocksource.
 180  */
 181 void __init at91rm9200_timer_init(void)
 182 {
 183         /* Disable all timer interrupts, and clear any pending ones */
 184         at91_sys_write(AT91_ST_IDR,
 185                 AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
 186         (void) at91_sys_read(AT91_ST_SR);
 187
 188         /* Make IRQs happen for the system timer */
 189         setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq);
 190
 191         /* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
 192          * directly for the clocksource and all clockevents, after adjusting
 193          * its prescaler from the 1 Hz default.
 194          */
 195         at91_sys_write(AT91_ST_RTMR, 1);
 196
 197         /* Setup timer clockevent, with minimum of two ticks (important!!) */
 198         clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift);
 199         clkevt.max_delta_ns = clockevent_delta2ns(AT91_ST_ALMV, &clkevt);
 200         clkevt.min_delta_ns = clockevent_delta2ns(2, &clkevt) + 1;
 201         clkevt.cpumask = cpumask_of(0);
 202         clockevents_register_device(&clkevt);
 203
 204         /* register clocksource */
 205         clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK);
 206 }
 207
 208 struct sys_timer at91rm9200_timer = {
 209         .init           = at91rm9200_timer_init,
 210 };
 211