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spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / mach-at91 / at91sam9263_devices.c
blob026ae37678b66e9c8ba522a5e4c9e03ab84877cf
1 /*
2 * arch/arm/mach-at91/at91sam9263_devices.c
3 *
4 * Copyright (C) 2007 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12 #include <asm/mach/arch.h>
13 #include <asm/mach/map.h>
14
15 #include <linux/dma-mapping.h>
16 #include <linux/gpio.h>
17 #include <linux/platform_device.h>
18 #include <linux/i2c-gpio.h>
19
20 #include <linux/fb.h>
21 #include <video/atmel_lcdc.h>
22
23 #include <mach/board.h>
24 #include <mach/at91sam9263.h>
25 #include <mach/at91sam9263_matrix.h>
26 #include <mach/at91sam9_smc.h>
27
28 #include "generic.h"
29
30
31 /* --------------------------------------------------------------------
32 * USB Host
33 * -------------------------------------------------------------------- */
34
35 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
36 static u64 ohci_dmamask = DMA_BIT_MASK(32);
37 static struct at91_usbh_data usbh_data;
38
39 static struct resource usbh_resources[] = {
40 [0] = {
41 .start = AT91SAM9263_UHP_BASE,
42 .end = AT91SAM9263_UHP_BASE + SZ_1M - 1,
43 .flags = IORESOURCE_MEM,
44 },
45 [1] = {
46 .start = AT91SAM9263_ID_UHP,
47 .end = AT91SAM9263_ID_UHP,
48 .flags = IORESOURCE_IRQ,
49 },
50 };
51
52 static struct platform_device at91_usbh_device = {
53 .name = "at91_ohci",
54 .id = -1,
55 .dev = {
56 .dma_mask = &ohci_dmamask,
57 .coherent_dma_mask = DMA_BIT_MASK(32),
58 .platform_data = &usbh_data,
59 },
60 .resource = usbh_resources,
61 .num_resources = ARRAY_SIZE(usbh_resources),
62 };
63
64 void __init at91_add_device_usbh(struct at91_usbh_data *data)
65 {
66 int i;
67
68 if (!data)
69 return;
70
71 /* Enable VBus control for UHP ports */
72 for (i = 0; i < data->ports; i++) {
73 if (gpio_is_valid(data->vbus_pin[i]))
74 at91_set_gpio_output(data->vbus_pin[i],
75 data->vbus_pin_active_low[i]);
76 }
77
78 /* Enable overcurrent notification */
79 for (i = 0; i < data->ports; i++) {
80 if (data->overcurrent_pin[i])
81 at91_set_gpio_input(data->overcurrent_pin[i], 1);
82 }
83
84 usbh_data = *data;
85 platform_device_register(&at91_usbh_device);
86 }
87 #else
88 void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
89 #endif
90
91
92 /* --------------------------------------------------------------------
93 * USB Device (Gadget)
94 * -------------------------------------------------------------------- */
95
96 #if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
97 static struct at91_udc_data udc_data;
98
99 static struct resource udc_resources[] = {
100 [0] = {
101 .start = AT91SAM9263_BASE_UDP,
102 .end = AT91SAM9263_BASE_UDP + SZ_16K - 1,
103 .flags = IORESOURCE_MEM,
104 },
105 [1] = {
106 .start = AT91SAM9263_ID_UDP,
107 .end = AT91SAM9263_ID_UDP,
108 .flags = IORESOURCE_IRQ,
109 },
110 };
111
112 static struct platform_device at91_udc_device = {
113 .name = "at91_udc",
114 .id = -1,
115 .dev = {
116 .platform_data = &udc_data,
117 },
118 .resource = udc_resources,
119 .num_resources = ARRAY_SIZE(udc_resources),
120 };
121
122 void __init at91_add_device_udc(struct at91_udc_data *data)
123 {
124 if (!data)
125 return;
126
127 if (gpio_is_valid(data->vbus_pin)) {
128 at91_set_gpio_input(data->vbus_pin, 0);
129 at91_set_deglitch(data->vbus_pin, 1);
130 }
131
132 /* Pullup pin is handled internally by USB device peripheral */
133
134 udc_data = *data;
135 platform_device_register(&at91_udc_device);
136 }
137 #else
138 void __init at91_add_device_udc(struct at91_udc_data *data) {}
139 #endif
140
141
142 /* --------------------------------------------------------------------
143 * Ethernet
144 * -------------------------------------------------------------------- */
145
146 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
147 static u64 eth_dmamask = DMA_BIT_MASK(32);
148 static struct macb_platform_data eth_data;
149
150 static struct resource eth_resources[] = {
151 [0] = {
152 .start = AT91SAM9263_BASE_EMAC,
153 .end = AT91SAM9263_BASE_EMAC + SZ_16K - 1,
154 .flags = IORESOURCE_MEM,
155 },
156 [1] = {
157 .start = AT91SAM9263_ID_EMAC,
158 .end = AT91SAM9263_ID_EMAC,
159 .flags = IORESOURCE_IRQ,
160 },
161 };
162
163 static struct platform_device at91sam9263_eth_device = {
164 .name = "macb",
165 .id = -1,
166 .dev = {
167 .dma_mask = &eth_dmamask,
168 .coherent_dma_mask = DMA_BIT_MASK(32),
169 .platform_data = &eth_data,
170 },
171 .resource = eth_resources,
172 .num_resources = ARRAY_SIZE(eth_resources),
173 };
174
175 void __init at91_add_device_eth(struct macb_platform_data *data)
176 {
177 if (!data)
178 return;
179
180 if (gpio_is_valid(data->phy_irq_pin)) {
181 at91_set_gpio_input(data->phy_irq_pin, 0);
182 at91_set_deglitch(data->phy_irq_pin, 1);
183 }
184
185 /* Pins used for MII and RMII */
186 at91_set_A_periph(AT91_PIN_PE21, 0); /* ETXCK_EREFCK */
187 at91_set_B_periph(AT91_PIN_PC25, 0); /* ERXDV */
188 at91_set_A_periph(AT91_PIN_PE25, 0); /* ERX0 */
189 at91_set_A_periph(AT91_PIN_PE26, 0); /* ERX1 */
190 at91_set_A_periph(AT91_PIN_PE27, 0); /* ERXER */
191 at91_set_A_periph(AT91_PIN_PE28, 0); /* ETXEN */
192 at91_set_A_periph(AT91_PIN_PE23, 0); /* ETX0 */
193 at91_set_A_periph(AT91_PIN_PE24, 0); /* ETX1 */
194 at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */
195 at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */
196
197 if (!data->is_rmii) {
198 at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */
199 at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
200 at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
201 at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
202 at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
203 at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
204 at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
205 at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
206 }
207
208 eth_data = *data;
209 platform_device_register(&at91sam9263_eth_device);
210 }
211 #else
212 void __init at91_add_device_eth(struct macb_platform_data *data) {}
213 #endif
214
215
216 /* --------------------------------------------------------------------
217 * MMC / SD
218 * -------------------------------------------------------------------- */
219
220 #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
221 static u64 mmc_dmamask = DMA_BIT_MASK(32);
222 static struct at91_mmc_data mmc0_data, mmc1_data;
223
224 static struct resource mmc0_resources[] = {
225 [0] = {
226 .start = AT91SAM9263_BASE_MCI0,
227 .end = AT91SAM9263_BASE_MCI0 + SZ_16K - 1,
228 .flags = IORESOURCE_MEM,
229 },
230 [1] = {
231 .start = AT91SAM9263_ID_MCI0,
232 .end = AT91SAM9263_ID_MCI0,
233 .flags = IORESOURCE_IRQ,
234 },
235 };
236
237 static struct platform_device at91sam9263_mmc0_device = {
238 .name = "at91_mci",
239 .id = 0,
240 .dev = {
241 .dma_mask = &mmc_dmamask,
242 .coherent_dma_mask = DMA_BIT_MASK(32),
243 .platform_data = &mmc0_data,
244 },
245 .resource = mmc0_resources,
246 .num_resources = ARRAY_SIZE(mmc0_resources),
247 };
248
249 static struct resource mmc1_resources[] = {
250 [0] = {
251 .start = AT91SAM9263_BASE_MCI1,
252 .end = AT91SAM9263_BASE_MCI1 + SZ_16K - 1,
253 .flags = IORESOURCE_MEM,
254 },
255 [1] = {
256 .start = AT91SAM9263_ID_MCI1,
257 .end = AT91SAM9263_ID_MCI1,
258 .flags = IORESOURCE_IRQ,
259 },
260 };
261
262 static struct platform_device at91sam9263_mmc1_device = {
263 .name = "at91_mci",
264 .id = 1,
265 .dev = {
266 .dma_mask = &mmc_dmamask,
267 .coherent_dma_mask = DMA_BIT_MASK(32),
268 .platform_data = &mmc1_data,
269 },
270 .resource = mmc1_resources,
271 .num_resources = ARRAY_SIZE(mmc1_resources),
272 };
273
274 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
275 {
276 if (!data)
277 return;
278
279 /* input/irq */
280 if (gpio_is_valid(data->det_pin)) {
281 at91_set_gpio_input(data->det_pin, 1);
282 at91_set_deglitch(data->det_pin, 1);
283 }
284 if (gpio_is_valid(data->wp_pin))
285 at91_set_gpio_input(data->wp_pin, 1);
286 if (gpio_is_valid(data->vcc_pin))
287 at91_set_gpio_output(data->vcc_pin, 0);
288
289 if (mmc_id == 0) { /* MCI0 */
290 /* CLK */
291 at91_set_A_periph(AT91_PIN_PA12, 0);
292
293 if (data->slot_b) {
294 /* CMD */
295 at91_set_A_periph(AT91_PIN_PA16, 1);
296
297 /* DAT0, maybe DAT1..DAT3 */
298 at91_set_A_periph(AT91_PIN_PA17, 1);
299 if (data->wire4) {
300 at91_set_A_periph(AT91_PIN_PA18, 1);
301 at91_set_A_periph(AT91_PIN_PA19, 1);
302 at91_set_A_periph(AT91_PIN_PA20, 1);
303 }
304 } else {
305 /* CMD */
306 at91_set_A_periph(AT91_PIN_PA1, 1);
307
308 /* DAT0, maybe DAT1..DAT3 */
309 at91_set_A_periph(AT91_PIN_PA0, 1);
310 if (data->wire4) {
311 at91_set_A_periph(AT91_PIN_PA3, 1);
312 at91_set_A_periph(AT91_PIN_PA4, 1);
313 at91_set_A_periph(AT91_PIN_PA5, 1);
314 }
315 }
316
317 mmc0_data = *data;
318 platform_device_register(&at91sam9263_mmc0_device);
319 } else { /* MCI1 */
320 /* CLK */
321 at91_set_A_periph(AT91_PIN_PA6, 0);
322
323 if (data->slot_b) {
324 /* CMD */
325 at91_set_A_periph(AT91_PIN_PA21, 1);
326
327 /* DAT0, maybe DAT1..DAT3 */
328 at91_set_A_periph(AT91_PIN_PA22, 1);
329 if (data->wire4) {
330 at91_set_A_periph(AT91_PIN_PA23, 1);
331 at91_set_A_periph(AT91_PIN_PA24, 1);
332 at91_set_A_periph(AT91_PIN_PA25, 1);
333 }
334 } else {
335 /* CMD */
336 at91_set_A_periph(AT91_PIN_PA7, 1);
337
338 /* DAT0, maybe DAT1..DAT3 */
339 at91_set_A_periph(AT91_PIN_PA8, 1);
340 if (data->wire4) {
341 at91_set_A_periph(AT91_PIN_PA9, 1);
342 at91_set_A_periph(AT91_PIN_PA10, 1);
343 at91_set_A_periph(AT91_PIN_PA11, 1);
344 }
345 }
346
347 mmc1_data = *data;
348 platform_device_register(&at91sam9263_mmc1_device);
349 }
350 }
351 #else
352 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
353 #endif
354
355 /* --------------------------------------------------------------------
356 * Compact Flash (PCMCIA or IDE)
357 * -------------------------------------------------------------------- */
358
359 #if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \
360 defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
361
362 static struct at91_cf_data cf0_data;
363
364 static struct resource cf0_resources[] = {
365 [0] = {
366 .start = AT91_CHIPSELECT_4,
367 .end = AT91_CHIPSELECT_4 + SZ_256M - 1,
368 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
369 }
370 };
371
372 static struct platform_device cf0_device = {
373 .id = 0,
374 .dev = {
375 .platform_data = &cf0_data,
376 },
377 .resource = cf0_resources,
378 .num_resources = ARRAY_SIZE(cf0_resources),
379 };
380
381 static struct at91_cf_data cf1_data;
382
383 static struct resource cf1_resources[] = {
384 [0] = {
385 .start = AT91_CHIPSELECT_5,
386 .end = AT91_CHIPSELECT_5 + SZ_256M - 1,
387 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
388 }
389 };
390
391 static struct platform_device cf1_device = {
392 .id = 1,
393 .dev = {
394 .platform_data = &cf1_data,
395 },
396 .resource = cf1_resources,
397 .num_resources = ARRAY_SIZE(cf1_resources),
398 };
399
400 void __init at91_add_device_cf(struct at91_cf_data *data)
401 {
402 unsigned long ebi0_csa;
403 struct platform_device *pdev;
404
405 if (!data)
406 return;
407
408 /*
409 * assign CS4 or CS5 to SMC with Compact Flash logic support,
410 * we assume SMC timings are configured by board code,
411 * except True IDE where timings are controlled by driver
412 */
413 ebi0_csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
414 switch (data->chipselect) {
415 case 4:
416 at91_set_A_periph(AT91_PIN_PD6, 0); /* EBI0_NCS4/CFCS0 */
417 ebi0_csa |= AT91_MATRIX_EBI0_CS4A_SMC_CF1;
418 cf0_data = *data;
419 pdev = &cf0_device;
420 break;
421 case 5:
422 at91_set_A_periph(AT91_PIN_PD7, 0); /* EBI0_NCS5/CFCS1 */
423 ebi0_csa |= AT91_MATRIX_EBI0_CS5A_SMC_CF2;
424 cf1_data = *data;
425 pdev = &cf1_device;
426 break;
427 default:
428 printk(KERN_ERR "AT91 CF: bad chip-select requested (%u)\n",
429 data->chipselect);
430 return;
431 }
432 at91_sys_write(AT91_MATRIX_EBI0CSA, ebi0_csa);
433
434 if (gpio_is_valid(data->det_pin)) {
435 at91_set_gpio_input(data->det_pin, 1);
436 at91_set_deglitch(data->det_pin, 1);
437 }
438
439 if (gpio_is_valid(data->irq_pin)) {
440 at91_set_gpio_input(data->irq_pin, 1);
441 at91_set_deglitch(data->irq_pin, 1);
442 }
443
444 if (gpio_is_valid(data->vcc_pin))
445 /* initially off */
446 at91_set_gpio_output(data->vcc_pin, 0);
447
448 /* enable EBI controlled pins */
449 at91_set_A_periph(AT91_PIN_PD5, 1); /* NWAIT */
450 at91_set_A_periph(AT91_PIN_PD8, 0); /* CFCE1 */
451 at91_set_A_periph(AT91_PIN_PD9, 0); /* CFCE2 */
452 at91_set_A_periph(AT91_PIN_PD14, 0); /* CFNRW */
453
454 pdev->name = (data->flags & AT91_CF_TRUE_IDE) ? "pata_at91" : "at91_cf";
455 platform_device_register(pdev);
456 }
457 #else
458 void __init at91_add_device_cf(struct at91_cf_data *data) {}
459 #endif
460
461 /* --------------------------------------------------------------------
462 * NAND / SmartMedia
463 * -------------------------------------------------------------------- */
464
465 #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
466 static struct atmel_nand_data nand_data;
467
468 #define NAND_BASE AT91_CHIPSELECT_3
469
470 static struct resource nand_resources[] = {
471 [0] = {
472 .start = NAND_BASE,
473 .end = NAND_BASE + SZ_256M - 1,
474 .flags = IORESOURCE_MEM,
475 },
476 [1] = {
477 .start = AT91SAM9263_BASE_ECC0,
478 .end = AT91SAM9263_BASE_ECC0 + SZ_512 - 1,
479 .flags = IORESOURCE_MEM,
480 }
481 };
482
483 static struct platform_device at91sam9263_nand_device = {
484 .name = "atmel_nand",
485 .id = -1,
486 .dev = {
487 .platform_data = &nand_data,
488 },
489 .resource = nand_resources,
490 .num_resources = ARRAY_SIZE(nand_resources),
491 };
492
493 void __init at91_add_device_nand(struct atmel_nand_data *data)
494 {
495 unsigned long csa;
496
497 if (!data)
498 return;
499
500 csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
501 at91_sys_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
502
503 /* enable pin */
504 if (gpio_is_valid(data->enable_pin))
505 at91_set_gpio_output(data->enable_pin, 1);
506
507 /* ready/busy pin */
508 if (gpio_is_valid(data->rdy_pin))
509 at91_set_gpio_input(data->rdy_pin, 1);
510
511 /* card detect pin */
512 if (gpio_is_valid(data->det_pin))
513 at91_set_gpio_input(data->det_pin, 1);
514
515 nand_data = *data;
516 platform_device_register(&at91sam9263_nand_device);
517 }
518 #else
519 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
520 #endif
521
522
523 /* --------------------------------------------------------------------
524 * TWI (i2c)
525 * -------------------------------------------------------------------- */
526
527 /*
528 * Prefer the GPIO code since the TWI controller isn't robust
529 * (gets overruns and underruns under load) and can only issue
530 * repeated STARTs in one scenario (the driver doesn't yet handle them).
531 */
532 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
533
534 static struct i2c_gpio_platform_data pdata = {
535 .sda_pin = AT91_PIN_PB4,
536 .sda_is_open_drain = 1,
537 .scl_pin = AT91_PIN_PB5,
538 .scl_is_open_drain = 1,
539 .udelay = 2, /* ~100 kHz */
540 };
541
542 static struct platform_device at91sam9263_twi_device = {
543 .name = "i2c-gpio",
544 .id = -1,
545 .dev.platform_data = &pdata,
546 };
547
548 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
549 {
550 at91_set_GPIO_periph(AT91_PIN_PB4, 1); /* TWD (SDA) */
551 at91_set_multi_drive(AT91_PIN_PB4, 1);
552
553 at91_set_GPIO_periph(AT91_PIN_PB5, 1); /* TWCK (SCL) */
554 at91_set_multi_drive(AT91_PIN_PB5, 1);
555
556 i2c_register_board_info(0, devices, nr_devices);
557 platform_device_register(&at91sam9263_twi_device);
558 }
559
560 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
561
562 static struct resource twi_resources[] = {
563 [0] = {
564 .start = AT91SAM9263_BASE_TWI,
565 .end = AT91SAM9263_BASE_TWI + SZ_16K - 1,
566 .flags = IORESOURCE_MEM,
567 },
568 [1] = {
569 .start = AT91SAM9263_ID_TWI,
570 .end = AT91SAM9263_ID_TWI,
571 .flags = IORESOURCE_IRQ,
572 },
573 };
574
575 static struct platform_device at91sam9263_twi_device = {
576 .name = "at91_i2c",
577 .id = -1,
578 .resource = twi_resources,
579 .num_resources = ARRAY_SIZE(twi_resources),
580 };
581
582 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
583 {
584 /* pins used for TWI interface */
585 at91_set_A_periph(AT91_PIN_PB4, 0); /* TWD */
586 at91_set_multi_drive(AT91_PIN_PB4, 1);
587
588 at91_set_A_periph(AT91_PIN_PB5, 0); /* TWCK */
589 at91_set_multi_drive(AT91_PIN_PB5, 1);
590
591 i2c_register_board_info(0, devices, nr_devices);
592 platform_device_register(&at91sam9263_twi_device);
593 }
594 #else
595 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
596 #endif
597
598
599 /* --------------------------------------------------------------------
600 * SPI
601 * -------------------------------------------------------------------- */
602
603 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
604 static u64 spi_dmamask = DMA_BIT_MASK(32);
605
606 static struct resource spi0_resources[] = {
607 [0] = {
608 .start = AT91SAM9263_BASE_SPI0,
609 .end = AT91SAM9263_BASE_SPI0 + SZ_16K - 1,
610 .flags = IORESOURCE_MEM,
611 },
612 [1] = {
613 .start = AT91SAM9263_ID_SPI0,
614 .end = AT91SAM9263_ID_SPI0,
615 .flags = IORESOURCE_IRQ,
616 },
617 };
618
619 static struct platform_device at91sam9263_spi0_device = {
620 .name = "atmel_spi",
621 .id = 0,
622 .dev = {
623 .dma_mask = &spi_dmamask,
624 .coherent_dma_mask = DMA_BIT_MASK(32),
625 },
626 .resource = spi0_resources,
627 .num_resources = ARRAY_SIZE(spi0_resources),
628 };
629
630 static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA5, AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PB11 };
631
632 static struct resource spi1_resources[] = {
633 [0] = {
634 .start = AT91SAM9263_BASE_SPI1,
635 .end = AT91SAM9263_BASE_SPI1 + SZ_16K - 1,
636 .flags = IORESOURCE_MEM,
637 },
638 [1] = {
639 .start = AT91SAM9263_ID_SPI1,
640 .end = AT91SAM9263_ID_SPI1,
641 .flags = IORESOURCE_IRQ,
642 },
643 };
644
645 static struct platform_device at91sam9263_spi1_device = {
646 .name = "atmel_spi",
647 .id = 1,
648 .dev = {
649 .dma_mask = &spi_dmamask,
650 .coherent_dma_mask = DMA_BIT_MASK(32),
651 },
652 .resource = spi1_resources,
653 .num_resources = ARRAY_SIZE(spi1_resources),
654 };
655
656 static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB15, AT91_PIN_PB16, AT91_PIN_PB17, AT91_PIN_PB18 };
657
658 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
659 {
660 int i;
661 unsigned long cs_pin;
662 short enable_spi0 = 0;
663 short enable_spi1 = 0;
664
665 /* Choose SPI chip-selects */
666 for (i = 0; i < nr_devices; i++) {
667 if (devices[i].controller_data)
668 cs_pin = (unsigned long) devices[i].controller_data;
669 else if (devices[i].bus_num == 0)
670 cs_pin = spi0_standard_cs[devices[i].chip_select];
671 else
672 cs_pin = spi1_standard_cs[devices[i].chip_select];
673
674 if (devices[i].bus_num == 0)
675 enable_spi0 = 1;
676 else
677 enable_spi1 = 1;
678
679 /* enable chip-select pin */
680 at91_set_gpio_output(cs_pin, 1);
681
682 /* pass chip-select pin to driver */
683 devices[i].controller_data = (void *) cs_pin;
684 }
685
686 spi_register_board_info(devices, nr_devices);
687
688 /* Configure SPI bus(es) */
689 if (enable_spi0) {
690 at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
691 at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
692 at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
693
694 platform_device_register(&at91sam9263_spi0_device);
695 }
696 if (enable_spi1) {
697 at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */
698 at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */
699 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */
700
701 platform_device_register(&at91sam9263_spi1_device);
702 }
703 }
704 #else
705 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
706 #endif
707
708
709 /* --------------------------------------------------------------------
710 * AC97
711 * -------------------------------------------------------------------- */
712
713 #if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
714 static u64 ac97_dmamask = DMA_BIT_MASK(32);
715 static struct ac97c_platform_data ac97_data;
716
717 static struct resource ac97_resources[] = {
718 [0] = {
719 .start = AT91SAM9263_BASE_AC97C,
720 .end = AT91SAM9263_BASE_AC97C + SZ_16K - 1,
721 .flags = IORESOURCE_MEM,
722 },
723 [1] = {
724 .start = AT91SAM9263_ID_AC97C,
725 .end = AT91SAM9263_ID_AC97C,
726 .flags = IORESOURCE_IRQ,
727 },
728 };
729
730 static struct platform_device at91sam9263_ac97_device = {
731 .name = "atmel_ac97c",
732 .id = 0,
733 .dev = {
734 .dma_mask = &ac97_dmamask,
735 .coherent_dma_mask = DMA_BIT_MASK(32),
736 .platform_data = &ac97_data,
737 },
738 .resource = ac97_resources,
739 .num_resources = ARRAY_SIZE(ac97_resources),
740 };
741
742 void __init at91_add_device_ac97(struct ac97c_platform_data *data)
743 {
744 if (!data)
745 return;
746
747 at91_set_A_periph(AT91_PIN_PB0, 0); /* AC97FS */
748 at91_set_A_periph(AT91_PIN_PB1, 0); /* AC97CK */
749 at91_set_A_periph(AT91_PIN_PB2, 0); /* AC97TX */
750 at91_set_A_periph(AT91_PIN_PB3, 0); /* AC97RX */
751
752 /* reset */
753 if (gpio_is_valid(data->reset_pin))
754 at91_set_gpio_output(data->reset_pin, 0);
755
756 ac97_data = *data;
757 platform_device_register(&at91sam9263_ac97_device);
758 }
759 #else
760 void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
761 #endif
762
763 /* --------------------------------------------------------------------
764 * CAN Controller
765 * -------------------------------------------------------------------- */
766
767 #if defined(CONFIG_CAN_AT91) || defined(CONFIG_CAN_AT91_MODULE)
768 static struct resource can_resources[] = {
769 [0] = {
770 .start = AT91SAM9263_BASE_CAN,
771 .end = AT91SAM9263_BASE_CAN + SZ_16K - 1,
772 .flags = IORESOURCE_MEM,
773 },
774 [1] = {
775 .start = AT91SAM9263_ID_CAN,
776 .end = AT91SAM9263_ID_CAN,
777 .flags = IORESOURCE_IRQ,
778 },
779 };
780
781 static struct platform_device at91sam9263_can_device = {
782 .name = "at91_can",
783 .id = -1,
784 .resource = can_resources,
785 .num_resources = ARRAY_SIZE(can_resources),
786 };
787
788 void __init at91_add_device_can(struct at91_can_data *data)
789 {
790 at91_set_A_periph(AT91_PIN_PA13, 0); /* CANTX */
791 at91_set_A_periph(AT91_PIN_PA14, 0); /* CANRX */
792 at91sam9263_can_device.dev.platform_data = data;
793
794 platform_device_register(&at91sam9263_can_device);
795 }
796 #else
797 void __init at91_add_device_can(struct at91_can_data *data) {}
798 #endif
799
800 /* --------------------------------------------------------------------
801 * LCD Controller
802 * -------------------------------------------------------------------- */
803
804 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
805 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
806 static struct atmel_lcdfb_info lcdc_data;
807
808 static struct resource lcdc_resources[] = {
809 [0] = {
810 .start = AT91SAM9263_LCDC_BASE,
811 .end = AT91SAM9263_LCDC_BASE + SZ_4K - 1,
812 .flags = IORESOURCE_MEM,
813 },
814 [1] = {
815 .start = AT91SAM9263_ID_LCDC,
816 .end = AT91SAM9263_ID_LCDC,
817 .flags = IORESOURCE_IRQ,
818 },
819 };
820
821 static struct platform_device at91_lcdc_device = {
822 .name = "atmel_lcdfb",
823 .id = 0,
824 .dev = {
825 .dma_mask = &lcdc_dmamask,
826 .coherent_dma_mask = DMA_BIT_MASK(32),
827 .platform_data = &lcdc_data,
828 },
829 .resource = lcdc_resources,
830 .num_resources = ARRAY_SIZE(lcdc_resources),
831 };
832
833 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
834 {
835 if (!data)
836 return;
837
838 at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
839 at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
840 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
841 at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
842 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
843 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
844 at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
845 at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
846 at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
847 at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
848 at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
849 at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
850 at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
851 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */
852 at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
853 at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
854 at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
855 at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
856 at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
857 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */
858 at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
859 at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
860
861 lcdc_data = *data;
862 platform_device_register(&at91_lcdc_device);
863 }
864 #else
865 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
866 #endif
867
868
869 /* --------------------------------------------------------------------
870 * Image Sensor Interface
871 * -------------------------------------------------------------------- */
872
873 #if defined(CONFIG_VIDEO_AT91_ISI) || defined(CONFIG_VIDEO_AT91_ISI_MODULE)
874
875 struct resource isi_resources[] = {
876 [0] = {
877 .start = AT91SAM9263_BASE_ISI,
878 .end = AT91SAM9263_BASE_ISI + SZ_16K - 1,
879 .flags = IORESOURCE_MEM,
880 },
881 [1] = {
882 .start = AT91SAM9263_ID_ISI,
883 .end = AT91SAM9263_ID_ISI,
884 .flags = IORESOURCE_IRQ,
885 },
886 };
887
888 static struct platform_device at91sam9263_isi_device = {
889 .name = "at91_isi",
890 .id = -1,
891 .resource = isi_resources,
892 .num_resources = ARRAY_SIZE(isi_resources),
893 };
894
895 void __init at91_add_device_isi(void)
896 {
897 at91_set_A_periph(AT91_PIN_PE0, 0); /* ISI_D0 */
898 at91_set_A_periph(AT91_PIN_PE1, 0); /* ISI_D1 */
899 at91_set_A_periph(AT91_PIN_PE2, 0); /* ISI_D2 */
900 at91_set_A_periph(AT91_PIN_PE3, 0); /* ISI_D3 */
901 at91_set_A_periph(AT91_PIN_PE4, 0); /* ISI_D4 */
902 at91_set_A_periph(AT91_PIN_PE5, 0); /* ISI_D5 */
903 at91_set_A_periph(AT91_PIN_PE6, 0); /* ISI_D6 */
904 at91_set_A_periph(AT91_PIN_PE7, 0); /* ISI_D7 */
905 at91_set_A_periph(AT91_PIN_PE8, 0); /* ISI_PCK */
906 at91_set_A_periph(AT91_PIN_PE9, 0); /* ISI_HSYNC */
907 at91_set_A_periph(AT91_PIN_PE10, 0); /* ISI_VSYNC */
908 at91_set_B_periph(AT91_PIN_PE11, 0); /* ISI_MCK (PCK3) */
909 at91_set_B_periph(AT91_PIN_PE12, 0); /* ISI_PD8 */
910 at91_set_B_periph(AT91_PIN_PE13, 0); /* ISI_PD9 */
911 at91_set_B_periph(AT91_PIN_PE14, 0); /* ISI_PD10 */
912 at91_set_B_periph(AT91_PIN_PE15, 0); /* ISI_PD11 */
913 }
914 #else
915 void __init at91_add_device_isi(void) {}
916 #endif
917
918
919 /* --------------------------------------------------------------------
920 * Timer/Counter block
921 * -------------------------------------------------------------------- */
922
923 #ifdef CONFIG_ATMEL_TCLIB
924
925 static struct resource tcb_resources[] = {
926 [0] = {
927 .start = AT91SAM9263_BASE_TCB0,
928 .end = AT91SAM9263_BASE_TCB0 + SZ_16K - 1,
929 .flags = IORESOURCE_MEM,
930 },
931 [1] = {
932 .start = AT91SAM9263_ID_TCB,
933 .end = AT91SAM9263_ID_TCB,
934 .flags = IORESOURCE_IRQ,
935 },
936 };
937
938 static struct platform_device at91sam9263_tcb_device = {
939 .name = "atmel_tcb",
940 .id = 0,
941 .resource = tcb_resources,
942 .num_resources = ARRAY_SIZE(tcb_resources),
943 };
944
945 static void __init at91_add_device_tc(void)
946 {
947 platform_device_register(&at91sam9263_tcb_device);
948 }
949 #else
950 static void __init at91_add_device_tc(void) { }
951 #endif
952
953
954 /* --------------------------------------------------------------------
955 * RTT
956 * -------------------------------------------------------------------- */
957
958 static struct resource rtt0_resources[] = {
959 {
960 .start = AT91SAM9263_BASE_RTT0,
961 .end = AT91SAM9263_BASE_RTT0 + SZ_16 - 1,
962 .flags = IORESOURCE_MEM,
963 }
964 };
965
966 static struct platform_device at91sam9263_rtt0_device = {
967 .name = "at91_rtt",
968 .id = 0,
969 .resource = rtt0_resources,
970 .num_resources = ARRAY_SIZE(rtt0_resources),
971 };
972
973 static struct resource rtt1_resources[] = {
974 {
975 .start = AT91SAM9263_BASE_RTT1,
976 .end = AT91SAM9263_BASE_RTT1 + SZ_16 - 1,
977 .flags = IORESOURCE_MEM,
978 }
979 };
980
981 static struct platform_device at91sam9263_rtt1_device = {
982 .name = "at91_rtt",
983 .id = 1,
984 .resource = rtt1_resources,
985 .num_resources = ARRAY_SIZE(rtt1_resources),
986 };
987
988 static void __init at91_add_device_rtt(void)
989 {
990 platform_device_register(&at91sam9263_rtt0_device);
991 platform_device_register(&at91sam9263_rtt1_device);
992 }
993
994
995 /* --------------------------------------------------------------------
996 * Watchdog
997 * -------------------------------------------------------------------- */
998
999 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
1000 static struct resource wdt_resources[] = {
1001 {
1002 .start = AT91SAM9263_BASE_WDT,
1003 .end = AT91SAM9263_BASE_WDT + SZ_16 - 1,
1004 .flags = IORESOURCE_MEM,
1005 }
1006 };
1007
1008 static struct platform_device at91sam9263_wdt_device = {
1009 .name = "at91_wdt",
1010 .id = -1,
1011 .resource = wdt_resources,
1012 .num_resources = ARRAY_SIZE(wdt_resources),
1013 };
1014
1015 static void __init at91_add_device_watchdog(void)
1016 {
1017 platform_device_register(&at91sam9263_wdt_device);
1018 }
1019 #else
1020 static void __init at91_add_device_watchdog(void) {}
1021 #endif
1022
1023
1024 /* --------------------------------------------------------------------
1025 * PWM
1026 * --------------------------------------------------------------------*/
1027
1028 #if defined(CONFIG_ATMEL_PWM)
1029 static u32 pwm_mask;
1030
1031 static struct resource pwm_resources[] = {
1032 [0] = {
1033 .start = AT91SAM9263_BASE_PWMC,
1034 .end = AT91SAM9263_BASE_PWMC + SZ_16K - 1,
1035 .flags = IORESOURCE_MEM,
1036 },
1037 [1] = {
1038 .start = AT91SAM9263_ID_PWMC,
1039 .end = AT91SAM9263_ID_PWMC,
1040 .flags = IORESOURCE_IRQ,
1041 },
1042 };
1043
1044 static struct platform_device at91sam9263_pwm0_device = {
1045 .name = "atmel_pwm",
1046 .id = -1,
1047 .dev = {
1048 .platform_data = &pwm_mask,
1049 },
1050 .resource = pwm_resources,
1051 .num_resources = ARRAY_SIZE(pwm_resources),
1052 };
1053
1054 void __init at91_add_device_pwm(u32 mask)
1055 {
1056 if (mask & (1 << AT91_PWM0))
1057 at91_set_B_periph(AT91_PIN_PB7, 1); /* enable PWM0 */
1058
1059 if (mask & (1 << AT91_PWM1))
1060 at91_set_B_periph(AT91_PIN_PB8, 1); /* enable PWM1 */
1061
1062 if (mask & (1 << AT91_PWM2))
1063 at91_set_B_periph(AT91_PIN_PC29, 1); /* enable PWM2 */
1064
1065 if (mask & (1 << AT91_PWM3))
1066 at91_set_B_periph(AT91_PIN_PB29, 1); /* enable PWM3 */
1067
1068 pwm_mask = mask;
1069
1070 platform_device_register(&at91sam9263_pwm0_device);
1071 }
1072 #else
1073 void __init at91_add_device_pwm(u32 mask) {}
1074 #endif
1075
1076
1077 /* --------------------------------------------------------------------
1078 * SSC -- Synchronous Serial Controller
1079 * -------------------------------------------------------------------- */
1080
1081 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
1082 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
1083
1084 static struct resource ssc0_resources[] = {
1085 [0] = {
1086 .start = AT91SAM9263_BASE_SSC0,
1087 .end = AT91SAM9263_BASE_SSC0 + SZ_16K - 1,
1088 .flags = IORESOURCE_MEM,
1089 },
1090 [1] = {
1091 .start = AT91SAM9263_ID_SSC0,
1092 .end = AT91SAM9263_ID_SSC0,
1093 .flags = IORESOURCE_IRQ,
1094 },
1095 };
1096
1097 static struct platform_device at91sam9263_ssc0_device = {
1098 .name = "ssc",
1099 .id = 0,
1100 .dev = {
1101 .dma_mask = &ssc0_dmamask,
1102 .coherent_dma_mask = DMA_BIT_MASK(32),
1103 },
1104 .resource = ssc0_resources,
1105 .num_resources = ARRAY_SIZE(ssc0_resources),
1106 };
1107
1108 static inline void configure_ssc0_pins(unsigned pins)
1109 {
1110 if (pins & ATMEL_SSC_TF)
1111 at91_set_B_periph(AT91_PIN_PB0, 1);
1112 if (pins & ATMEL_SSC_TK)
1113 at91_set_B_periph(AT91_PIN_PB1, 1);
1114 if (pins & ATMEL_SSC_TD)
1115 at91_set_B_periph(AT91_PIN_PB2, 1);
1116 if (pins & ATMEL_SSC_RD)
1117 at91_set_B_periph(AT91_PIN_PB3, 1);
1118 if (pins & ATMEL_SSC_RK)
1119 at91_set_B_periph(AT91_PIN_PB4, 1);
1120 if (pins & ATMEL_SSC_RF)
1121 at91_set_B_periph(AT91_PIN_PB5, 1);
1122 }
1123
1124 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
1125
1126 static struct resource ssc1_resources[] = {
1127 [0] = {
1128 .start = AT91SAM9263_BASE_SSC1,
1129 .end = AT91SAM9263_BASE_SSC1 + SZ_16K - 1,
1130 .flags = IORESOURCE_MEM,
1131 },
1132 [1] = {
1133 .start = AT91SAM9263_ID_SSC1,
1134 .end = AT91SAM9263_ID_SSC1,
1135 .flags = IORESOURCE_IRQ,
1136 },
1137 };
1138
1139 static struct platform_device at91sam9263_ssc1_device = {
1140 .name = "ssc",
1141 .id = 1,
1142 .dev = {
1143 .dma_mask = &ssc1_dmamask,
1144 .coherent_dma_mask = DMA_BIT_MASK(32),
1145 },
1146 .resource = ssc1_resources,
1147 .num_resources = ARRAY_SIZE(ssc1_resources),
1148 };
1149
1150 static inline void configure_ssc1_pins(unsigned pins)
1151 {
1152 if (pins & ATMEL_SSC_TF)
1153 at91_set_A_periph(AT91_PIN_PB6, 1);
1154 if (pins & ATMEL_SSC_TK)
1155 at91_set_A_periph(AT91_PIN_PB7, 1);
1156 if (pins & ATMEL_SSC_TD)
1157 at91_set_A_periph(AT91_PIN_PB8, 1);
1158 if (pins & ATMEL_SSC_RD)
1159 at91_set_A_periph(AT91_PIN_PB9, 1);
1160 if (pins & ATMEL_SSC_RK)
1161 at91_set_A_periph(AT91_PIN_PB10, 1);
1162 if (pins & ATMEL_SSC_RF)
1163 at91_set_A_periph(AT91_PIN_PB11, 1);
1164 }
1165
1166 /*
1167 * SSC controllers are accessed through library code, instead of any
1168 * kind of all-singing/all-dancing driver. For example one could be
1169 * used by a particular I2S audio codec's driver, while another one
1170 * on the same system might be used by a custom data capture driver.
1171 */
1172 void __init at91_add_device_ssc(unsigned id, unsigned pins)
1173 {
1174 struct platform_device *pdev;
1175
1176 /*
1177 * NOTE: caller is responsible for passing information matching
1178 * "pins" to whatever will be using each particular controller.
1179 */
1180 switch (id) {
1181 case AT91SAM9263_ID_SSC0:
1182 pdev = &at91sam9263_ssc0_device;
1183 configure_ssc0_pins(pins);
1184 break;
1185 case AT91SAM9263_ID_SSC1:
1186 pdev = &at91sam9263_ssc1_device;
1187 configure_ssc1_pins(pins);
1188 break;
1189 default:
1190 return;
1191 }
1192
1193 platform_device_register(pdev);
1194 }
1195
1196 #else
1197 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1198 #endif
1199
1200
1201 /* --------------------------------------------------------------------
1202 * UART
1203 * -------------------------------------------------------------------- */
1204
1205 #if defined(CONFIG_SERIAL_ATMEL)
1206
1207 static struct resource dbgu_resources[] = {
1208 [0] = {
1209 .start = AT91SAM9263_BASE_DBGU,
1210 .end = AT91SAM9263_BASE_DBGU + SZ_512 - 1,
1211 .flags = IORESOURCE_MEM,
1212 },
1213 [1] = {
1214 .start = AT91_ID_SYS,
1215 .end = AT91_ID_SYS,
1216 .flags = IORESOURCE_IRQ,
1217 },
1218 };
1219
1220 static struct atmel_uart_data dbgu_data = {
1221 .use_dma_tx = 0,
1222 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
1223 };
1224
1225 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1226
1227 static struct platform_device at91sam9263_dbgu_device = {
1228 .name = "atmel_usart",
1229 .id = 0,
1230 .dev = {
1231 .dma_mask = &dbgu_dmamask,
1232 .coherent_dma_mask = DMA_BIT_MASK(32),
1233 .platform_data = &dbgu_data,
1234 },
1235 .resource = dbgu_resources,
1236 .num_resources = ARRAY_SIZE(dbgu_resources),
1237 };
1238
1239 static inline void configure_dbgu_pins(void)
1240 {
1241 at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
1242 at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
1243 }
1244
1245 static struct resource uart0_resources[] = {
1246 [0] = {
1247 .start = AT91SAM9263_BASE_US0,
1248 .end = AT91SAM9263_BASE_US0 + SZ_16K - 1,
1249 .flags = IORESOURCE_MEM,
1250 },
1251 [1] = {
1252 .start = AT91SAM9263_ID_US0,
1253 .end = AT91SAM9263_ID_US0,
1254 .flags = IORESOURCE_IRQ,
1255 },
1256 };
1257
1258 static struct atmel_uart_data uart0_data = {
1259 .use_dma_tx = 1,
1260 .use_dma_rx = 1,
1261 };
1262
1263 static u64 uart0_dmamask = DMA_BIT_MASK(32);
1264
1265 static struct platform_device at91sam9263_uart0_device = {
1266 .name = "atmel_usart",
1267 .id = 1,
1268 .dev = {
1269 .dma_mask = &uart0_dmamask,
1270 .coherent_dma_mask = DMA_BIT_MASK(32),
1271 .platform_data = &uart0_data,
1272 },
1273 .resource = uart0_resources,
1274 .num_resources = ARRAY_SIZE(uart0_resources),
1275 };
1276
1277 static inline void configure_usart0_pins(unsigned pins)
1278 {
1279 at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */
1280 at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */
1281
1282 if (pins & ATMEL_UART_RTS)
1283 at91_set_A_periph(AT91_PIN_PA28, 0); /* RTS0 */
1284 if (pins & ATMEL_UART_CTS)
1285 at91_set_A_periph(AT91_PIN_PA29, 0); /* CTS0 */
1286 }
1287
1288 static struct resource uart1_resources[] = {
1289 [0] = {
1290 .start = AT91SAM9263_BASE_US1,
1291 .end = AT91SAM9263_BASE_US1 + SZ_16K - 1,
1292 .flags = IORESOURCE_MEM,
1293 },
1294 [1] = {
1295 .start = AT91SAM9263_ID_US1,
1296 .end = AT91SAM9263_ID_US1,
1297 .flags = IORESOURCE_IRQ,
1298 },
1299 };
1300
1301 static struct atmel_uart_data uart1_data = {
1302 .use_dma_tx = 1,
1303 .use_dma_rx = 1,
1304 };
1305
1306 static u64 uart1_dmamask = DMA_BIT_MASK(32);
1307
1308 static struct platform_device at91sam9263_uart1_device = {
1309 .name = "atmel_usart",
1310 .id = 2,
1311 .dev = {
1312 .dma_mask = &uart1_dmamask,
1313 .coherent_dma_mask = DMA_BIT_MASK(32),
1314 .platform_data = &uart1_data,
1315 },
1316 .resource = uart1_resources,
1317 .num_resources = ARRAY_SIZE(uart1_resources),
1318 };
1319
1320 static inline void configure_usart1_pins(unsigned pins)
1321 {
1322 at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
1323 at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
1324
1325 if (pins & ATMEL_UART_RTS)
1326 at91_set_B_periph(AT91_PIN_PD7, 0); /* RTS1 */
1327 if (pins & ATMEL_UART_CTS)
1328 at91_set_B_periph(AT91_PIN_PD8, 0); /* CTS1 */
1329 }
1330
1331 static struct resource uart2_resources[] = {
1332 [0] = {
1333 .start = AT91SAM9263_BASE_US2,
1334 .end = AT91SAM9263_BASE_US2 + SZ_16K - 1,
1335 .flags = IORESOURCE_MEM,
1336 },
1337 [1] = {
1338 .start = AT91SAM9263_ID_US2,
1339 .end = AT91SAM9263_ID_US2,
1340 .flags = IORESOURCE_IRQ,
1341 },
1342 };
1343
1344 static struct atmel_uart_data uart2_data = {
1345 .use_dma_tx = 1,
1346 .use_dma_rx = 1,
1347 };
1348
1349 static u64 uart2_dmamask = DMA_BIT_MASK(32);
1350
1351 static struct platform_device at91sam9263_uart2_device = {
1352 .name = "atmel_usart",
1353 .id = 3,
1354 .dev = {
1355 .dma_mask = &uart2_dmamask,
1356 .coherent_dma_mask = DMA_BIT_MASK(32),
1357 .platform_data = &uart2_data,
1358 },
1359 .resource = uart2_resources,
1360 .num_resources = ARRAY_SIZE(uart2_resources),
1361 };
1362
1363 static inline void configure_usart2_pins(unsigned pins)
1364 {
1365 at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
1366 at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
1367
1368 if (pins & ATMEL_UART_RTS)
1369 at91_set_B_periph(AT91_PIN_PD5, 0); /* RTS2 */
1370 if (pins & ATMEL_UART_CTS)
1371 at91_set_B_periph(AT91_PIN_PD6, 0); /* CTS2 */
1372 }
1373
1374 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1375 struct platform_device *atmel_default_console_device; /* the serial console device */
1376
1377 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1378 {
1379 struct platform_device *pdev;
1380 struct atmel_uart_data *pdata;
1381
1382 switch (id) {
1383 case 0: /* DBGU */
1384 pdev = &at91sam9263_dbgu_device;
1385 configure_dbgu_pins();
1386 break;
1387 case AT91SAM9263_ID_US0:
1388 pdev = &at91sam9263_uart0_device;
1389 configure_usart0_pins(pins);
1390 break;
1391 case AT91SAM9263_ID_US1:
1392 pdev = &at91sam9263_uart1_device;
1393 configure_usart1_pins(pins);
1394 break;
1395 case AT91SAM9263_ID_US2:
1396 pdev = &at91sam9263_uart2_device;
1397 configure_usart2_pins(pins);
1398 break;
1399 default:
1400 return;
1401 }
1402 pdata = pdev->dev.platform_data;
1403 pdata->num = portnr; /* update to mapped ID */
1404
1405 if (portnr < ATMEL_MAX_UART)
1406 at91_uarts[portnr] = pdev;
1407 }
1408
1409 void __init at91_set_serial_console(unsigned portnr)
1410 {
1411 if (portnr < ATMEL_MAX_UART) {
1412 atmel_default_console_device = at91_uarts[portnr];
1413 at91sam9263_set_console_clock(at91_uarts[portnr]->id);
1414 }
1415 }
1416
1417 void __init at91_add_device_serial(void)
1418 {
1419 int i;
1420
1421 for (i = 0; i < ATMEL_MAX_UART; i++) {
1422 if (at91_uarts[i])
1423 platform_device_register(at91_uarts[i]);
1424 }
1425
1426 if (!atmel_default_console_device)
1427 printk(KERN_INFO "AT91: No default serial console defined.\n");
1428 }
1429 #else
1430 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1431 void __init at91_set_serial_console(unsigned portnr) {}
1432 void __init at91_add_device_serial(void) {}
1433 #endif
1434
1435
1436 /* -------------------------------------------------------------------- */
1437 /*
1438 * These devices are always present and don't need any board-specific
1439 * setup.
1440 */
1441 static int __init at91_add_standard_devices(void)
1442 {
1443 at91_add_device_rtt();
1444 at91_add_device_watchdog();
1445 at91_add_device_tc();
1446 return 0;
1447 }
1448
1449 arch_initcall(at91_add_standard_devices);