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spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / mach-at91 / at91sam9g45_devices.c
bloba8c48be6efeb768ad2581869ede6037954a4c2b0
1 /*
2 * On-Chip devices setup code for the AT91SAM9G45 family
3 *
4 * Copyright (C) 2009 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12 #include <asm/mach/arch.h>
13 #include <asm/mach/map.h>
14
15 #include <linux/dma-mapping.h>
16 #include <linux/gpio.h>
17 #include <linux/platform_device.h>
18 #include <linux/i2c-gpio.h>
19 #include <linux/atmel-mci.h>
20
21 #include <linux/fb.h>
22 #include <video/atmel_lcdc.h>
23
24 #include <mach/board.h>
25 #include <mach/at91sam9g45.h>
26 #include <mach/at91sam9g45_matrix.h>
27 #include <mach/at91sam9_smc.h>
28 #include <mach/at_hdmac.h>
29 #include <mach/atmel-mci.h>
30
31 #include "generic.h"
32
33
34 /* --------------------------------------------------------------------
35 * HDMAC - AHB DMA Controller
36 * -------------------------------------------------------------------- */
37
38 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
39 static u64 hdmac_dmamask = DMA_BIT_MASK(32);
40
41 static struct resource hdmac_resources[] = {
42 [0] = {
43 .start = AT91SAM9G45_BASE_DMA,
44 .end = AT91SAM9G45_BASE_DMA + SZ_512 - 1,
45 .flags = IORESOURCE_MEM,
46 },
47 [1] = {
48 .start = AT91SAM9G45_ID_DMA,
49 .end = AT91SAM9G45_ID_DMA,
50 .flags = IORESOURCE_IRQ,
51 },
52 };
53
54 static struct platform_device at_hdmac_device = {
55 .name = "at91sam9g45_dma",
56 .id = -1,
57 .dev = {
58 .dma_mask = &hdmac_dmamask,
59 .coherent_dma_mask = DMA_BIT_MASK(32),
60 },
61 .resource = hdmac_resources,
62 .num_resources = ARRAY_SIZE(hdmac_resources),
63 };
64
65 void __init at91_add_device_hdmac(void)
66 {
67 #if defined(CONFIG_OF)
68 struct device_node *of_node =
69 of_find_node_by_name(NULL, "dma-controller");
70
71 if (of_node)
72 of_node_put(of_node);
73 else
74 #endif
75 platform_device_register(&at_hdmac_device);
76 }
77 #else
78 void __init at91_add_device_hdmac(void) {}
79 #endif
80
81
82 /* --------------------------------------------------------------------
83 * USB Host (OHCI)
84 * -------------------------------------------------------------------- */
85
86 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
87 static u64 ohci_dmamask = DMA_BIT_MASK(32);
88 static struct at91_usbh_data usbh_ohci_data;
89
90 static struct resource usbh_ohci_resources[] = {
91 [0] = {
92 .start = AT91SAM9G45_OHCI_BASE,
93 .end = AT91SAM9G45_OHCI_BASE + SZ_1M - 1,
94 .flags = IORESOURCE_MEM,
95 },
96 [1] = {
97 .start = AT91SAM9G45_ID_UHPHS,
98 .end = AT91SAM9G45_ID_UHPHS,
99 .flags = IORESOURCE_IRQ,
100 },
101 };
102
103 static struct platform_device at91_usbh_ohci_device = {
104 .name = "at91_ohci",
105 .id = -1,
106 .dev = {
107 .dma_mask = &ohci_dmamask,
108 .coherent_dma_mask = DMA_BIT_MASK(32),
109 .platform_data = &usbh_ohci_data,
110 },
111 .resource = usbh_ohci_resources,
112 .num_resources = ARRAY_SIZE(usbh_ohci_resources),
113 };
114
115 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
116 {
117 int i;
118
119 if (!data)
120 return;
121
122 /* Enable VBus control for UHP ports */
123 for (i = 0; i < data->ports; i++) {
124 if (gpio_is_valid(data->vbus_pin[i]))
125 at91_set_gpio_output(data->vbus_pin[i],
126 data->vbus_pin_active_low[i]);
127 }
128
129 /* Enable overcurrent notification */
130 for (i = 0; i < data->ports; i++) {
131 if (data->overcurrent_pin[i])
132 at91_set_gpio_input(data->overcurrent_pin[i], 1);
133 }
134
135 usbh_ohci_data = *data;
136 platform_device_register(&at91_usbh_ohci_device);
137 }
138 #else
139 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
140 #endif
141
142
143 /* --------------------------------------------------------------------
144 * USB Host HS (EHCI)
145 * Needs an OHCI host for low and full speed management
146 * -------------------------------------------------------------------- */
147
148 #if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
149 static u64 ehci_dmamask = DMA_BIT_MASK(32);
150 static struct at91_usbh_data usbh_ehci_data;
151
152 static struct resource usbh_ehci_resources[] = {
153 [0] = {
154 .start = AT91SAM9G45_EHCI_BASE,
155 .end = AT91SAM9G45_EHCI_BASE + SZ_1M - 1,
156 .flags = IORESOURCE_MEM,
157 },
158 [1] = {
159 .start = AT91SAM9G45_ID_UHPHS,
160 .end = AT91SAM9G45_ID_UHPHS,
161 .flags = IORESOURCE_IRQ,
162 },
163 };
164
165 static struct platform_device at91_usbh_ehci_device = {
166 .name = "atmel-ehci",
167 .id = -1,
168 .dev = {
169 .dma_mask = &ehci_dmamask,
170 .coherent_dma_mask = DMA_BIT_MASK(32),
171 .platform_data = &usbh_ehci_data,
172 },
173 .resource = usbh_ehci_resources,
174 .num_resources = ARRAY_SIZE(usbh_ehci_resources),
175 };
176
177 void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data)
178 {
179 int i;
180
181 if (!data)
182 return;
183
184 /* Enable VBus control for UHP ports */
185 for (i = 0; i < data->ports; i++) {
186 if (gpio_is_valid(data->vbus_pin[i]))
187 at91_set_gpio_output(data->vbus_pin[i],
188 data->vbus_pin_active_low[i]);
189 }
190
191 usbh_ehci_data = *data;
192 platform_device_register(&at91_usbh_ehci_device);
193 }
194 #else
195 void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) {}
196 #endif
197
198
199 /* --------------------------------------------------------------------
200 * USB HS Device (Gadget)
201 * -------------------------------------------------------------------- */
202
203 #if defined(CONFIG_USB_ATMEL_USBA) || defined(CONFIG_USB_ATMEL_USBA_MODULE)
204 static struct resource usba_udc_resources[] = {
205 [0] = {
206 .start = AT91SAM9G45_UDPHS_FIFO,
207 .end = AT91SAM9G45_UDPHS_FIFO + SZ_512K - 1,
208 .flags = IORESOURCE_MEM,
209 },
210 [1] = {
211 .start = AT91SAM9G45_BASE_UDPHS,
212 .end = AT91SAM9G45_BASE_UDPHS + SZ_1K - 1,
213 .flags = IORESOURCE_MEM,
214 },
215 [2] = {
216 .start = AT91SAM9G45_ID_UDPHS,
217 .end = AT91SAM9G45_ID_UDPHS,
218 .flags = IORESOURCE_IRQ,
219 },
220 };
221
222 #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
223 [idx] = { \
224 .name = nam, \
225 .index = idx, \
226 .fifo_size = maxpkt, \
227 .nr_banks = maxbk, \
228 .can_dma = dma, \
229 .can_isoc = isoc, \
230 }
231
232 static struct usba_ep_data usba_udc_ep[] __initdata = {
233 EP("ep0", 0, 64, 1, 0, 0),
234 EP("ep1", 1, 1024, 2, 1, 1),
235 EP("ep2", 2, 1024, 2, 1, 1),
236 EP("ep3", 3, 1024, 3, 1, 0),
237 EP("ep4", 4, 1024, 3, 1, 0),
238 EP("ep5", 5, 1024, 3, 1, 1),
239 EP("ep6", 6, 1024, 3, 1, 1),
240 };
241
242 #undef EP
243
244 /*
245 * pdata doesn't have room for any endpoints, so we need to
246 * append room for the ones we need right after it.
247 */
248 static struct {
249 struct usba_platform_data pdata;
250 struct usba_ep_data ep[7];
251 } usba_udc_data;
252
253 static struct platform_device at91_usba_udc_device = {
254 .name = "atmel_usba_udc",
255 .id = -1,
256 .dev = {
257 .platform_data = &usba_udc_data.pdata,
258 },
259 .resource = usba_udc_resources,
260 .num_resources = ARRAY_SIZE(usba_udc_resources),
261 };
262
263 void __init at91_add_device_usba(struct usba_platform_data *data)
264 {
265 usba_udc_data.pdata.vbus_pin = -EINVAL;
266 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
267 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
268
269 if (data && gpio_is_valid(data->vbus_pin)) {
270 at91_set_gpio_input(data->vbus_pin, 0);
271 at91_set_deglitch(data->vbus_pin, 1);
272 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
273 }
274
275 /* Pullup pin is handled internally by USB device peripheral */
276
277 platform_device_register(&at91_usba_udc_device);
278 }
279 #else
280 void __init at91_add_device_usba(struct usba_platform_data *data) {}
281 #endif
282
283
284 /* --------------------------------------------------------------------
285 * Ethernet
286 * -------------------------------------------------------------------- */
287
288 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
289 static u64 eth_dmamask = DMA_BIT_MASK(32);
290 static struct macb_platform_data eth_data;
291
292 static struct resource eth_resources[] = {
293 [0] = {
294 .start = AT91SAM9G45_BASE_EMAC,
295 .end = AT91SAM9G45_BASE_EMAC + SZ_16K - 1,
296 .flags = IORESOURCE_MEM,
297 },
298 [1] = {
299 .start = AT91SAM9G45_ID_EMAC,
300 .end = AT91SAM9G45_ID_EMAC,
301 .flags = IORESOURCE_IRQ,
302 },
303 };
304
305 static struct platform_device at91sam9g45_eth_device = {
306 .name = "macb",
307 .id = -1,
308 .dev = {
309 .dma_mask = &eth_dmamask,
310 .coherent_dma_mask = DMA_BIT_MASK(32),
311 .platform_data = &eth_data,
312 },
313 .resource = eth_resources,
314 .num_resources = ARRAY_SIZE(eth_resources),
315 };
316
317 void __init at91_add_device_eth(struct macb_platform_data *data)
318 {
319 if (!data)
320 return;
321
322 if (gpio_is_valid(data->phy_irq_pin)) {
323 at91_set_gpio_input(data->phy_irq_pin, 0);
324 at91_set_deglitch(data->phy_irq_pin, 1);
325 }
326
327 /* Pins used for MII and RMII */
328 at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */
329 at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */
330 at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
331 at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
332 at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */
333 at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */
334 at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */
335 at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */
336 at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */
337 at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */
338
339 if (!data->is_rmii) {
340 at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */
341 at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */
342 at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */
343 at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */
344 at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */
345 at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */
346 at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */
347 at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */
348 }
349
350 eth_data = *data;
351 platform_device_register(&at91sam9g45_eth_device);
352 }
353 #else
354 void __init at91_add_device_eth(struct macb_platform_data *data) {}
355 #endif
356
357
358 /* --------------------------------------------------------------------
359 * MMC / SD
360 * -------------------------------------------------------------------- */
361
362 #if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
363 static u64 mmc_dmamask = DMA_BIT_MASK(32);
364 static struct mci_platform_data mmc0_data, mmc1_data;
365
366 static struct resource mmc0_resources[] = {
367 [0] = {
368 .start = AT91SAM9G45_BASE_MCI0,
369 .end = AT91SAM9G45_BASE_MCI0 + SZ_16K - 1,
370 .flags = IORESOURCE_MEM,
371 },
372 [1] = {
373 .start = AT91SAM9G45_ID_MCI0,
374 .end = AT91SAM9G45_ID_MCI0,
375 .flags = IORESOURCE_IRQ,
376 },
377 };
378
379 static struct platform_device at91sam9g45_mmc0_device = {
380 .name = "atmel_mci",
381 .id = 0,
382 .dev = {
383 .dma_mask = &mmc_dmamask,
384 .coherent_dma_mask = DMA_BIT_MASK(32),
385 .platform_data = &mmc0_data,
386 },
387 .resource = mmc0_resources,
388 .num_resources = ARRAY_SIZE(mmc0_resources),
389 };
390
391 static struct resource mmc1_resources[] = {
392 [0] = {
393 .start = AT91SAM9G45_BASE_MCI1,
394 .end = AT91SAM9G45_BASE_MCI1 + SZ_16K - 1,
395 .flags = IORESOURCE_MEM,
396 },
397 [1] = {
398 .start = AT91SAM9G45_ID_MCI1,
399 .end = AT91SAM9G45_ID_MCI1,
400 .flags = IORESOURCE_IRQ,
401 },
402 };
403
404 static struct platform_device at91sam9g45_mmc1_device = {
405 .name = "atmel_mci",
406 .id = 1,
407 .dev = {
408 .dma_mask = &mmc_dmamask,
409 .coherent_dma_mask = DMA_BIT_MASK(32),
410 .platform_data = &mmc1_data,
411 },
412 .resource = mmc1_resources,
413 .num_resources = ARRAY_SIZE(mmc1_resources),
414 };
415
416 /* Consider only one slot : slot 0 */
417 void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
418 {
419
420 if (!data)
421 return;
422
423 /* Must have at least one usable slot */
424 if (!data->slot[0].bus_width)
425 return;
426
427 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
428 {
429 struct at_dma_slave *atslave;
430 struct mci_dma_data *alt_atslave;
431
432 alt_atslave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL);
433 atslave = &alt_atslave->sdata;
434
435 /* DMA slave channel configuration */
436 atslave->dma_dev = &at_hdmac_device.dev;
437 atslave->reg_width = AT_DMA_SLAVE_WIDTH_32BIT;
438 atslave->cfg = ATC_FIFOCFG_HALFFIFO
439 | ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW;
440 atslave->ctrla = ATC_SCSIZE_16 | ATC_DCSIZE_16;
441 if (mmc_id == 0) /* MCI0 */
442 atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI0)
443 | ATC_DST_PER(AT_DMA_ID_MCI0);
444
445 else /* MCI1 */
446 atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI1)
447 | ATC_DST_PER(AT_DMA_ID_MCI1);
448
449 data->dma_slave = alt_atslave;
450 }
451 #endif
452
453
454 /* input/irq */
455 if (gpio_is_valid(data->slot[0].detect_pin)) {
456 at91_set_gpio_input(data->slot[0].detect_pin, 1);
457 at91_set_deglitch(data->slot[0].detect_pin, 1);
458 }
459 if (gpio_is_valid(data->slot[0].wp_pin))
460 at91_set_gpio_input(data->slot[0].wp_pin, 1);
461
462 if (mmc_id == 0) { /* MCI0 */
463
464 /* CLK */
465 at91_set_A_periph(AT91_PIN_PA0, 0);
466
467 /* CMD */
468 at91_set_A_periph(AT91_PIN_PA1, 1);
469
470 /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
471 at91_set_A_periph(AT91_PIN_PA2, 1);
472 if (data->slot[0].bus_width == 4) {
473 at91_set_A_periph(AT91_PIN_PA3, 1);
474 at91_set_A_periph(AT91_PIN_PA4, 1);
475 at91_set_A_periph(AT91_PIN_PA5, 1);
476 if (data->slot[0].bus_width == 8) {
477 at91_set_A_periph(AT91_PIN_PA6, 1);
478 at91_set_A_periph(AT91_PIN_PA7, 1);
479 at91_set_A_periph(AT91_PIN_PA8, 1);
480 at91_set_A_periph(AT91_PIN_PA9, 1);
481 }
482 }
483
484 mmc0_data = *data;
485 platform_device_register(&at91sam9g45_mmc0_device);
486
487 } else { /* MCI1 */
488
489 /* CLK */
490 at91_set_A_periph(AT91_PIN_PA31, 0);
491
492 /* CMD */
493 at91_set_A_periph(AT91_PIN_PA22, 1);
494
495 /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
496 at91_set_A_periph(AT91_PIN_PA23, 1);
497 if (data->slot[0].bus_width == 4) {
498 at91_set_A_periph(AT91_PIN_PA24, 1);
499 at91_set_A_periph(AT91_PIN_PA25, 1);
500 at91_set_A_periph(AT91_PIN_PA26, 1);
501 if (data->slot[0].bus_width == 8) {
502 at91_set_A_periph(AT91_PIN_PA27, 1);
503 at91_set_A_periph(AT91_PIN_PA28, 1);
504 at91_set_A_periph(AT91_PIN_PA29, 1);
505 at91_set_A_periph(AT91_PIN_PA30, 1);
506 }
507 }
508
509 mmc1_data = *data;
510 platform_device_register(&at91sam9g45_mmc1_device);
511
512 }
513 }
514 #else
515 void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
516 #endif
517
518
519 /* --------------------------------------------------------------------
520 * NAND / SmartMedia
521 * -------------------------------------------------------------------- */
522
523 #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
524 static struct atmel_nand_data nand_data;
525
526 #define NAND_BASE AT91_CHIPSELECT_3
527
528 static struct resource nand_resources[] = {
529 [0] = {
530 .start = NAND_BASE,
531 .end = NAND_BASE + SZ_256M - 1,
532 .flags = IORESOURCE_MEM,
533 },
534 [1] = {
535 .start = AT91SAM9G45_BASE_ECC,
536 .end = AT91SAM9G45_BASE_ECC + SZ_512 - 1,
537 .flags = IORESOURCE_MEM,
538 }
539 };
540
541 static struct platform_device at91sam9g45_nand_device = {
542 .name = "atmel_nand",
543 .id = -1,
544 .dev = {
545 .platform_data = &nand_data,
546 },
547 .resource = nand_resources,
548 .num_resources = ARRAY_SIZE(nand_resources),
549 };
550
551 void __init at91_add_device_nand(struct atmel_nand_data *data)
552 {
553 unsigned long csa;
554
555 if (!data)
556 return;
557
558 csa = at91_sys_read(AT91_MATRIX_EBICSA);
559 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
560
561 /* enable pin */
562 if (gpio_is_valid(data->enable_pin))
563 at91_set_gpio_output(data->enable_pin, 1);
564
565 /* ready/busy pin */
566 if (gpio_is_valid(data->rdy_pin))
567 at91_set_gpio_input(data->rdy_pin, 1);
568
569 /* card detect pin */
570 if (gpio_is_valid(data->det_pin))
571 at91_set_gpio_input(data->det_pin, 1);
572
573 nand_data = *data;
574 platform_device_register(&at91sam9g45_nand_device);
575 }
576 #else
577 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
578 #endif
579
580
581 /* --------------------------------------------------------------------
582 * TWI (i2c)
583 * -------------------------------------------------------------------- */
584
585 /*
586 * Prefer the GPIO code since the TWI controller isn't robust
587 * (gets overruns and underruns under load) and can only issue
588 * repeated STARTs in one scenario (the driver doesn't yet handle them).
589 */
590 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
591 static struct i2c_gpio_platform_data pdata_i2c0 = {
592 .sda_pin = AT91_PIN_PA20,
593 .sda_is_open_drain = 1,
594 .scl_pin = AT91_PIN_PA21,
595 .scl_is_open_drain = 1,
596 .udelay = 5, /* ~100 kHz */
597 };
598
599 static struct platform_device at91sam9g45_twi0_device = {
600 .name = "i2c-gpio",
601 .id = 0,
602 .dev.platform_data = &pdata_i2c0,
603 };
604
605 static struct i2c_gpio_platform_data pdata_i2c1 = {
606 .sda_pin = AT91_PIN_PB10,
607 .sda_is_open_drain = 1,
608 .scl_pin = AT91_PIN_PB11,
609 .scl_is_open_drain = 1,
610 .udelay = 5, /* ~100 kHz */
611 };
612
613 static struct platform_device at91sam9g45_twi1_device = {
614 .name = "i2c-gpio",
615 .id = 1,
616 .dev.platform_data = &pdata_i2c1,
617 };
618
619 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
620 {
621 i2c_register_board_info(i2c_id, devices, nr_devices);
622
623 if (i2c_id == 0) {
624 at91_set_GPIO_periph(AT91_PIN_PA20, 1); /* TWD (SDA) */
625 at91_set_multi_drive(AT91_PIN_PA20, 1);
626
627 at91_set_GPIO_periph(AT91_PIN_PA21, 1); /* TWCK (SCL) */
628 at91_set_multi_drive(AT91_PIN_PA21, 1);
629
630 platform_device_register(&at91sam9g45_twi0_device);
631 } else {
632 at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* TWD (SDA) */
633 at91_set_multi_drive(AT91_PIN_PB10, 1);
634
635 at91_set_GPIO_periph(AT91_PIN_PB11, 1); /* TWCK (SCL) */
636 at91_set_multi_drive(AT91_PIN_PB11, 1);
637
638 platform_device_register(&at91sam9g45_twi1_device);
639 }
640 }
641
642 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
643 static struct resource twi0_resources[] = {
644 [0] = {
645 .start = AT91SAM9G45_BASE_TWI0,
646 .end = AT91SAM9G45_BASE_TWI0 + SZ_16K - 1,
647 .flags = IORESOURCE_MEM,
648 },
649 [1] = {
650 .start = AT91SAM9G45_ID_TWI0,
651 .end = AT91SAM9G45_ID_TWI0,
652 .flags = IORESOURCE_IRQ,
653 },
654 };
655
656 static struct platform_device at91sam9g45_twi0_device = {
657 .name = "at91_i2c",
658 .id = 0,
659 .resource = twi0_resources,
660 .num_resources = ARRAY_SIZE(twi0_resources),
661 };
662
663 static struct resource twi1_resources[] = {
664 [0] = {
665 .start = AT91SAM9G45_BASE_TWI1,
666 .end = AT91SAM9G45_BASE_TWI1 + SZ_16K - 1,
667 .flags = IORESOURCE_MEM,
668 },
669 [1] = {
670 .start = AT91SAM9G45_ID_TWI1,
671 .end = AT91SAM9G45_ID_TWI1,
672 .flags = IORESOURCE_IRQ,
673 },
674 };
675
676 static struct platform_device at91sam9g45_twi1_device = {
677 .name = "at91_i2c",
678 .id = 1,
679 .resource = twi1_resources,
680 .num_resources = ARRAY_SIZE(twi1_resources),
681 };
682
683 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
684 {
685 i2c_register_board_info(i2c_id, devices, nr_devices);
686
687 /* pins used for TWI interface */
688 if (i2c_id == 0) {
689 at91_set_A_periph(AT91_PIN_PA20, 0); /* TWD */
690 at91_set_multi_drive(AT91_PIN_PA20, 1);
691
692 at91_set_A_periph(AT91_PIN_PA21, 0); /* TWCK */
693 at91_set_multi_drive(AT91_PIN_PA21, 1);
694
695 platform_device_register(&at91sam9g45_twi0_device);
696 } else {
697 at91_set_A_periph(AT91_PIN_PB10, 0); /* TWD */
698 at91_set_multi_drive(AT91_PIN_PB10, 1);
699
700 at91_set_A_periph(AT91_PIN_PB11, 0); /* TWCK */
701 at91_set_multi_drive(AT91_PIN_PB11, 1);
702
703 platform_device_register(&at91sam9g45_twi1_device);
704 }
705 }
706 #else
707 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
708 #endif
709
710
711 /* --------------------------------------------------------------------
712 * SPI
713 * -------------------------------------------------------------------- */
714
715 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
716 static u64 spi_dmamask = DMA_BIT_MASK(32);
717
718 static struct resource spi0_resources[] = {
719 [0] = {
720 .start = AT91SAM9G45_BASE_SPI0,
721 .end = AT91SAM9G45_BASE_SPI0 + SZ_16K - 1,
722 .flags = IORESOURCE_MEM,
723 },
724 [1] = {
725 .start = AT91SAM9G45_ID_SPI0,
726 .end = AT91SAM9G45_ID_SPI0,
727 .flags = IORESOURCE_IRQ,
728 },
729 };
730
731 static struct platform_device at91sam9g45_spi0_device = {
732 .name = "atmel_spi",
733 .id = 0,
734 .dev = {
735 .dma_mask = &spi_dmamask,
736 .coherent_dma_mask = DMA_BIT_MASK(32),
737 },
738 .resource = spi0_resources,
739 .num_resources = ARRAY_SIZE(spi0_resources),
740 };
741
742 static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 };
743
744 static struct resource spi1_resources[] = {
745 [0] = {
746 .start = AT91SAM9G45_BASE_SPI1,
747 .end = AT91SAM9G45_BASE_SPI1 + SZ_16K - 1,
748 .flags = IORESOURCE_MEM,
749 },
750 [1] = {
751 .start = AT91SAM9G45_ID_SPI1,
752 .end = AT91SAM9G45_ID_SPI1,
753 .flags = IORESOURCE_IRQ,
754 },
755 };
756
757 static struct platform_device at91sam9g45_spi1_device = {
758 .name = "atmel_spi",
759 .id = 1,
760 .dev = {
761 .dma_mask = &spi_dmamask,
762 .coherent_dma_mask = DMA_BIT_MASK(32),
763 },
764 .resource = spi1_resources,
765 .num_resources = ARRAY_SIZE(spi1_resources),
766 };
767
768 static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 };
769
770 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
771 {
772 int i;
773 unsigned long cs_pin;
774 short enable_spi0 = 0;
775 short enable_spi1 = 0;
776
777 /* Choose SPI chip-selects */
778 for (i = 0; i < nr_devices; i++) {
779 if (devices[i].controller_data)
780 cs_pin = (unsigned long) devices[i].controller_data;
781 else if (devices[i].bus_num == 0)
782 cs_pin = spi0_standard_cs[devices[i].chip_select];
783 else
784 cs_pin = spi1_standard_cs[devices[i].chip_select];
785
786 if (devices[i].bus_num == 0)
787 enable_spi0 = 1;
788 else
789 enable_spi1 = 1;
790
791 /* enable chip-select pin */
792 at91_set_gpio_output(cs_pin, 1);
793
794 /* pass chip-select pin to driver */
795 devices[i].controller_data = (void *) cs_pin;
796 }
797
798 spi_register_board_info(devices, nr_devices);
799
800 /* Configure SPI bus(es) */
801 if (enable_spi0) {
802 at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI0_MISO */
803 at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI0_MOSI */
804 at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI0_SPCK */
805
806 platform_device_register(&at91sam9g45_spi0_device);
807 }
808 if (enable_spi1) {
809 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_MISO */
810 at91_set_A_periph(AT91_PIN_PB15, 0); /* SPI1_MOSI */
811 at91_set_A_periph(AT91_PIN_PB16, 0); /* SPI1_SPCK */
812
813 platform_device_register(&at91sam9g45_spi1_device);
814 }
815 }
816 #else
817 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
818 #endif
819
820
821 /* --------------------------------------------------------------------
822 * AC97
823 * -------------------------------------------------------------------- */
824
825 #if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
826 static u64 ac97_dmamask = DMA_BIT_MASK(32);
827 static struct ac97c_platform_data ac97_data;
828
829 static struct resource ac97_resources[] = {
830 [0] = {
831 .start = AT91SAM9G45_BASE_AC97C,
832 .end = AT91SAM9G45_BASE_AC97C + SZ_16K - 1,
833 .flags = IORESOURCE_MEM,
834 },
835 [1] = {
836 .start = AT91SAM9G45_ID_AC97C,
837 .end = AT91SAM9G45_ID_AC97C,
838 .flags = IORESOURCE_IRQ,
839 },
840 };
841
842 static struct platform_device at91sam9g45_ac97_device = {
843 .name = "atmel_ac97c",
844 .id = 0,
845 .dev = {
846 .dma_mask = &ac97_dmamask,
847 .coherent_dma_mask = DMA_BIT_MASK(32),
848 .platform_data = &ac97_data,
849 },
850 .resource = ac97_resources,
851 .num_resources = ARRAY_SIZE(ac97_resources),
852 };
853
854 void __init at91_add_device_ac97(struct ac97c_platform_data *data)
855 {
856 if (!data)
857 return;
858
859 at91_set_A_periph(AT91_PIN_PD8, 0); /* AC97FS */
860 at91_set_A_periph(AT91_PIN_PD9, 0); /* AC97CK */
861 at91_set_A_periph(AT91_PIN_PD7, 0); /* AC97TX */
862 at91_set_A_periph(AT91_PIN_PD6, 0); /* AC97RX */
863
864 /* reset */
865 if (gpio_is_valid(data->reset_pin))
866 at91_set_gpio_output(data->reset_pin, 0);
867
868 ac97_data = *data;
869 platform_device_register(&at91sam9g45_ac97_device);
870 }
871 #else
872 void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
873 #endif
874
875
876 /* --------------------------------------------------------------------
877 * LCD Controller
878 * -------------------------------------------------------------------- */
879
880 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
881 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
882 static struct atmel_lcdfb_info lcdc_data;
883
884 static struct resource lcdc_resources[] = {
885 [0] = {
886 .start = AT91SAM9G45_LCDC_BASE,
887 .end = AT91SAM9G45_LCDC_BASE + SZ_4K - 1,
888 .flags = IORESOURCE_MEM,
889 },
890 [1] = {
891 .start = AT91SAM9G45_ID_LCDC,
892 .end = AT91SAM9G45_ID_LCDC,
893 .flags = IORESOURCE_IRQ,
894 },
895 };
896
897 static struct platform_device at91_lcdc_device = {
898 .name = "atmel_lcdfb",
899 .id = 0,
900 .dev = {
901 .dma_mask = &lcdc_dmamask,
902 .coherent_dma_mask = DMA_BIT_MASK(32),
903 .platform_data = &lcdc_data,
904 },
905 .resource = lcdc_resources,
906 .num_resources = ARRAY_SIZE(lcdc_resources),
907 };
908
909 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
910 {
911 if (!data)
912 return;
913
914 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
915
916 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
917 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
918 at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
919 at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
920 at91_set_A_periph(AT91_PIN_PE6, 0); /* LCDDEN */
921 at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
922 at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
923 at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
924 at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
925 at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
926 at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
927 at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
928 at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
929 at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
930 at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
931 at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
932 at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
933 at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
934 at91_set_A_periph(AT91_PIN_PE20, 0); /* LCDD13 */
935 at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
936 at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
937 at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
938 at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
939 at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
940 at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
941 at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
942 at91_set_A_periph(AT91_PIN_PE28, 0); /* LCDD21 */
943 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
944 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
945
946 lcdc_data = *data;
947 platform_device_register(&at91_lcdc_device);
948 }
949 #else
950 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
951 #endif
952
953
954 /* --------------------------------------------------------------------
955 * Timer/Counter block
956 * -------------------------------------------------------------------- */
957
958 #ifdef CONFIG_ATMEL_TCLIB
959 static struct resource tcb0_resources[] = {
960 [0] = {
961 .start = AT91SAM9G45_BASE_TCB0,
962 .end = AT91SAM9G45_BASE_TCB0 + SZ_16K - 1,
963 .flags = IORESOURCE_MEM,
964 },
965 [1] = {
966 .start = AT91SAM9G45_ID_TCB,
967 .end = AT91SAM9G45_ID_TCB,
968 .flags = IORESOURCE_IRQ,
969 },
970 };
971
972 static struct platform_device at91sam9g45_tcb0_device = {
973 .name = "atmel_tcb",
974 .id = 0,
975 .resource = tcb0_resources,
976 .num_resources = ARRAY_SIZE(tcb0_resources),
977 };
978
979 /* TCB1 begins with TC3 */
980 static struct resource tcb1_resources[] = {
981 [0] = {
982 .start = AT91SAM9G45_BASE_TCB1,
983 .end = AT91SAM9G45_BASE_TCB1 + SZ_16K - 1,
984 .flags = IORESOURCE_MEM,
985 },
986 [1] = {
987 .start = AT91SAM9G45_ID_TCB,
988 .end = AT91SAM9G45_ID_TCB,
989 .flags = IORESOURCE_IRQ,
990 },
991 };
992
993 static struct platform_device at91sam9g45_tcb1_device = {
994 .name = "atmel_tcb",
995 .id = 1,
996 .resource = tcb1_resources,
997 .num_resources = ARRAY_SIZE(tcb1_resources),
998 };
999
1000 static void __init at91_add_device_tc(void)
1001 {
1002 platform_device_register(&at91sam9g45_tcb0_device);
1003 platform_device_register(&at91sam9g45_tcb1_device);
1004 }
1005 #else
1006 static void __init at91_add_device_tc(void) { }
1007 #endif
1008
1009
1010 /* --------------------------------------------------------------------
1011 * RTC
1012 * -------------------------------------------------------------------- */
1013
1014 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
1015 static struct resource rtc_resources[] = {
1016 [0] = {
1017 .start = AT91SAM9G45_BASE_RTC,
1018 .end = AT91SAM9G45_BASE_RTC + SZ_256 - 1,
1019 .flags = IORESOURCE_MEM,
1020 },
1021 [1] = {
1022 .start = AT91_ID_SYS,
1023 .end = AT91_ID_SYS,
1024 .flags = IORESOURCE_IRQ,
1025 },
1026 };
1027
1028 static struct platform_device at91sam9g45_rtc_device = {
1029 .name = "at91_rtc",
1030 .id = -1,
1031 .resource = rtc_resources,
1032 .num_resources = ARRAY_SIZE(rtc_resources),
1033 };
1034
1035 static void __init at91_add_device_rtc(void)
1036 {
1037 platform_device_register(&at91sam9g45_rtc_device);
1038 }
1039 #else
1040 static void __init at91_add_device_rtc(void) {}
1041 #endif
1042
1043
1044 /* --------------------------------------------------------------------
1045 * Touchscreen
1046 * -------------------------------------------------------------------- */
1047
1048 #if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE)
1049 static u64 tsadcc_dmamask = DMA_BIT_MASK(32);
1050 static struct at91_tsadcc_data tsadcc_data;
1051
1052 static struct resource tsadcc_resources[] = {
1053 [0] = {
1054 .start = AT91SAM9G45_BASE_TSC,
1055 .end = AT91SAM9G45_BASE_TSC + SZ_16K - 1,
1056 .flags = IORESOURCE_MEM,
1057 },
1058 [1] = {
1059 .start = AT91SAM9G45_ID_TSC,
1060 .end = AT91SAM9G45_ID_TSC,
1061 .flags = IORESOURCE_IRQ,
1062 }
1063 };
1064
1065 static struct platform_device at91sam9g45_tsadcc_device = {
1066 .name = "atmel_tsadcc",
1067 .id = -1,
1068 .dev = {
1069 .dma_mask = &tsadcc_dmamask,
1070 .coherent_dma_mask = DMA_BIT_MASK(32),
1071 .platform_data = &tsadcc_data,
1072 },
1073 .resource = tsadcc_resources,
1074 .num_resources = ARRAY_SIZE(tsadcc_resources),
1075 };
1076
1077 void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data)
1078 {
1079 if (!data)
1080 return;
1081
1082 at91_set_gpio_input(AT91_PIN_PD20, 0); /* AD0_XR */
1083 at91_set_gpio_input(AT91_PIN_PD21, 0); /* AD1_XL */
1084 at91_set_gpio_input(AT91_PIN_PD22, 0); /* AD2_YT */
1085 at91_set_gpio_input(AT91_PIN_PD23, 0); /* AD3_TB */
1086
1087 tsadcc_data = *data;
1088 platform_device_register(&at91sam9g45_tsadcc_device);
1089 }
1090 #else
1091 void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) {}
1092 #endif
1093
1094
1095 /* --------------------------------------------------------------------
1096 * RTT
1097 * -------------------------------------------------------------------- */
1098
1099 static struct resource rtt_resources[] = {
1100 {
1101 .start = AT91SAM9G45_BASE_RTT,
1102 .end = AT91SAM9G45_BASE_RTT + SZ_16 - 1,
1103 .flags = IORESOURCE_MEM,
1104 }
1105 };
1106
1107 static struct platform_device at91sam9g45_rtt_device = {
1108 .name = "at91_rtt",
1109 .id = 0,
1110 .resource = rtt_resources,
1111 .num_resources = ARRAY_SIZE(rtt_resources),
1112 };
1113
1114 static void __init at91_add_device_rtt(void)
1115 {
1116 platform_device_register(&at91sam9g45_rtt_device);
1117 }
1118
1119
1120 /* --------------------------------------------------------------------
1121 * TRNG
1122 * -------------------------------------------------------------------- */
1123
1124 #if defined(CONFIG_HW_RANDOM_ATMEL) || defined(CONFIG_HW_RANDOM_ATMEL_MODULE)
1125 static struct resource trng_resources[] = {
1126 {
1127 .start = AT91SAM9G45_BASE_TRNG,
1128 .end = AT91SAM9G45_BASE_TRNG + SZ_16K - 1,
1129 .flags = IORESOURCE_MEM,
1130 },
1131 };
1132
1133 static struct platform_device at91sam9g45_trng_device = {
1134 .name = "atmel-trng",
1135 .id = -1,
1136 .resource = trng_resources,
1137 .num_resources = ARRAY_SIZE(trng_resources),
1138 };
1139
1140 static void __init at91_add_device_trng(void)
1141 {
1142 platform_device_register(&at91sam9g45_trng_device);
1143 }
1144 #else
1145 static void __init at91_add_device_trng(void) {}
1146 #endif
1147
1148 /* --------------------------------------------------------------------
1149 * Watchdog
1150 * -------------------------------------------------------------------- */
1151
1152 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
1153 static struct resource wdt_resources[] = {
1154 {
1155 .start = AT91SAM9G45_BASE_WDT,
1156 .end = AT91SAM9G45_BASE_WDT + SZ_16 - 1,
1157 .flags = IORESOURCE_MEM,
1158 }
1159 };
1160
1161 static struct platform_device at91sam9g45_wdt_device = {
1162 .name = "at91_wdt",
1163 .id = -1,
1164 .resource = wdt_resources,
1165 .num_resources = ARRAY_SIZE(wdt_resources),
1166 };
1167
1168 static void __init at91_add_device_watchdog(void)
1169 {
1170 platform_device_register(&at91sam9g45_wdt_device);
1171 }
1172 #else
1173 static void __init at91_add_device_watchdog(void) {}
1174 #endif
1175
1176
1177 /* --------------------------------------------------------------------
1178 * PWM
1179 * --------------------------------------------------------------------*/
1180
1181 #if defined(CONFIG_ATMEL_PWM) || defined(CONFIG_ATMEL_PWM_MODULE)
1182 static u32 pwm_mask;
1183
1184 static struct resource pwm_resources[] = {
1185 [0] = {
1186 .start = AT91SAM9G45_BASE_PWMC,
1187 .end = AT91SAM9G45_BASE_PWMC + SZ_16K - 1,
1188 .flags = IORESOURCE_MEM,
1189 },
1190 [1] = {
1191 .start = AT91SAM9G45_ID_PWMC,
1192 .end = AT91SAM9G45_ID_PWMC,
1193 .flags = IORESOURCE_IRQ,
1194 },
1195 };
1196
1197 static struct platform_device at91sam9g45_pwm0_device = {
1198 .name = "atmel_pwm",
1199 .id = -1,
1200 .dev = {
1201 .platform_data = &pwm_mask,
1202 },
1203 .resource = pwm_resources,
1204 .num_resources = ARRAY_SIZE(pwm_resources),
1205 };
1206
1207 void __init at91_add_device_pwm(u32 mask)
1208 {
1209 if (mask & (1 << AT91_PWM0))
1210 at91_set_B_periph(AT91_PIN_PD24, 1); /* enable PWM0 */
1211
1212 if (mask & (1 << AT91_PWM1))
1213 at91_set_B_periph(AT91_PIN_PD31, 1); /* enable PWM1 */
1214
1215 if (mask & (1 << AT91_PWM2))
1216 at91_set_B_periph(AT91_PIN_PD26, 1); /* enable PWM2 */
1217
1218 if (mask & (1 << AT91_PWM3))
1219 at91_set_B_periph(AT91_PIN_PD0, 1); /* enable PWM3 */
1220
1221 pwm_mask = mask;
1222
1223 platform_device_register(&at91sam9g45_pwm0_device);
1224 }
1225 #else
1226 void __init at91_add_device_pwm(u32 mask) {}
1227 #endif
1228
1229
1230 /* --------------------------------------------------------------------
1231 * SSC -- Synchronous Serial Controller
1232 * -------------------------------------------------------------------- */
1233
1234 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
1235 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
1236
1237 static struct resource ssc0_resources[] = {
1238 [0] = {
1239 .start = AT91SAM9G45_BASE_SSC0,
1240 .end = AT91SAM9G45_BASE_SSC0 + SZ_16K - 1,
1241 .flags = IORESOURCE_MEM,
1242 },
1243 [1] = {
1244 .start = AT91SAM9G45_ID_SSC0,
1245 .end = AT91SAM9G45_ID_SSC0,
1246 .flags = IORESOURCE_IRQ,
1247 },
1248 };
1249
1250 static struct platform_device at91sam9g45_ssc0_device = {
1251 .name = "ssc",
1252 .id = 0,
1253 .dev = {
1254 .dma_mask = &ssc0_dmamask,
1255 .coherent_dma_mask = DMA_BIT_MASK(32),
1256 },
1257 .resource = ssc0_resources,
1258 .num_resources = ARRAY_SIZE(ssc0_resources),
1259 };
1260
1261 static inline void configure_ssc0_pins(unsigned pins)
1262 {
1263 if (pins & ATMEL_SSC_TF)
1264 at91_set_A_periph(AT91_PIN_PD1, 1);
1265 if (pins & ATMEL_SSC_TK)
1266 at91_set_A_periph(AT91_PIN_PD0, 1);
1267 if (pins & ATMEL_SSC_TD)
1268 at91_set_A_periph(AT91_PIN_PD2, 1);
1269 if (pins & ATMEL_SSC_RD)
1270 at91_set_A_periph(AT91_PIN_PD3, 1);
1271 if (pins & ATMEL_SSC_RK)
1272 at91_set_A_periph(AT91_PIN_PD4, 1);
1273 if (pins & ATMEL_SSC_RF)
1274 at91_set_A_periph(AT91_PIN_PD5, 1);
1275 }
1276
1277 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
1278
1279 static struct resource ssc1_resources[] = {
1280 [0] = {
1281 .start = AT91SAM9G45_BASE_SSC1,
1282 .end = AT91SAM9G45_BASE_SSC1 + SZ_16K - 1,
1283 .flags = IORESOURCE_MEM,
1284 },
1285 [1] = {
1286 .start = AT91SAM9G45_ID_SSC1,
1287 .end = AT91SAM9G45_ID_SSC1,
1288 .flags = IORESOURCE_IRQ,
1289 },
1290 };
1291
1292 static struct platform_device at91sam9g45_ssc1_device = {
1293 .name = "ssc",
1294 .id = 1,
1295 .dev = {
1296 .dma_mask = &ssc1_dmamask,
1297 .coherent_dma_mask = DMA_BIT_MASK(32),
1298 },
1299 .resource = ssc1_resources,
1300 .num_resources = ARRAY_SIZE(ssc1_resources),
1301 };
1302
1303 static inline void configure_ssc1_pins(unsigned pins)
1304 {
1305 if (pins & ATMEL_SSC_TF)
1306 at91_set_A_periph(AT91_PIN_PD14, 1);
1307 if (pins & ATMEL_SSC_TK)
1308 at91_set_A_periph(AT91_PIN_PD12, 1);
1309 if (pins & ATMEL_SSC_TD)
1310 at91_set_A_periph(AT91_PIN_PD10, 1);
1311 if (pins & ATMEL_SSC_RD)
1312 at91_set_A_periph(AT91_PIN_PD11, 1);
1313 if (pins & ATMEL_SSC_RK)
1314 at91_set_A_periph(AT91_PIN_PD13, 1);
1315 if (pins & ATMEL_SSC_RF)
1316 at91_set_A_periph(AT91_PIN_PD15, 1);
1317 }
1318
1319 /*
1320 * SSC controllers are accessed through library code, instead of any
1321 * kind of all-singing/all-dancing driver. For example one could be
1322 * used by a particular I2S audio codec's driver, while another one
1323 * on the same system might be used by a custom data capture driver.
1324 */
1325 void __init at91_add_device_ssc(unsigned id, unsigned pins)
1326 {
1327 struct platform_device *pdev;
1328
1329 /*
1330 * NOTE: caller is responsible for passing information matching
1331 * "pins" to whatever will be using each particular controller.
1332 */
1333 switch (id) {
1334 case AT91SAM9G45_ID_SSC0:
1335 pdev = &at91sam9g45_ssc0_device;
1336 configure_ssc0_pins(pins);
1337 break;
1338 case AT91SAM9G45_ID_SSC1:
1339 pdev = &at91sam9g45_ssc1_device;
1340 configure_ssc1_pins(pins);
1341 break;
1342 default:
1343 return;
1344 }
1345
1346 platform_device_register(pdev);
1347 }
1348
1349 #else
1350 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1351 #endif
1352
1353
1354 /* --------------------------------------------------------------------
1355 * UART
1356 * -------------------------------------------------------------------- */
1357
1358 #if defined(CONFIG_SERIAL_ATMEL)
1359 static struct resource dbgu_resources[] = {
1360 [0] = {
1361 .start = AT91SAM9G45_BASE_DBGU,
1362 .end = AT91SAM9G45_BASE_DBGU + SZ_512 - 1,
1363 .flags = IORESOURCE_MEM,
1364 },
1365 [1] = {
1366 .start = AT91_ID_SYS,
1367 .end = AT91_ID_SYS,
1368 .flags = IORESOURCE_IRQ,
1369 },
1370 };
1371
1372 static struct atmel_uart_data dbgu_data = {
1373 .use_dma_tx = 0,
1374 .use_dma_rx = 0,
1375 };
1376
1377 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1378
1379 static struct platform_device at91sam9g45_dbgu_device = {
1380 .name = "atmel_usart",
1381 .id = 0,
1382 .dev = {
1383 .dma_mask = &dbgu_dmamask,
1384 .coherent_dma_mask = DMA_BIT_MASK(32),
1385 .platform_data = &dbgu_data,
1386 },
1387 .resource = dbgu_resources,
1388 .num_resources = ARRAY_SIZE(dbgu_resources),
1389 };
1390
1391 static inline void configure_dbgu_pins(void)
1392 {
1393 at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */
1394 at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */
1395 }
1396
1397 static struct resource uart0_resources[] = {
1398 [0] = {
1399 .start = AT91SAM9G45_BASE_US0,
1400 .end = AT91SAM9G45_BASE_US0 + SZ_16K - 1,
1401 .flags = IORESOURCE_MEM,
1402 },
1403 [1] = {
1404 .start = AT91SAM9G45_ID_US0,
1405 .end = AT91SAM9G45_ID_US0,
1406 .flags = IORESOURCE_IRQ,
1407 },
1408 };
1409
1410 static struct atmel_uart_data uart0_data = {
1411 .use_dma_tx = 1,
1412 .use_dma_rx = 1,
1413 };
1414
1415 static u64 uart0_dmamask = DMA_BIT_MASK(32);
1416
1417 static struct platform_device at91sam9g45_uart0_device = {
1418 .name = "atmel_usart",
1419 .id = 1,
1420 .dev = {
1421 .dma_mask = &uart0_dmamask,
1422 .coherent_dma_mask = DMA_BIT_MASK(32),
1423 .platform_data = &uart0_data,
1424 },
1425 .resource = uart0_resources,
1426 .num_resources = ARRAY_SIZE(uart0_resources),
1427 };
1428
1429 static inline void configure_usart0_pins(unsigned pins)
1430 {
1431 at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */
1432 at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */
1433
1434 if (pins & ATMEL_UART_RTS)
1435 at91_set_B_periph(AT91_PIN_PB17, 0); /* RTS0 */
1436 if (pins & ATMEL_UART_CTS)
1437 at91_set_B_periph(AT91_PIN_PB15, 0); /* CTS0 */
1438 }
1439
1440 static struct resource uart1_resources[] = {
1441 [0] = {
1442 .start = AT91SAM9G45_BASE_US1,
1443 .end = AT91SAM9G45_BASE_US1 + SZ_16K - 1,
1444 .flags = IORESOURCE_MEM,
1445 },
1446 [1] = {
1447 .start = AT91SAM9G45_ID_US1,
1448 .end = AT91SAM9G45_ID_US1,
1449 .flags = IORESOURCE_IRQ,
1450 },
1451 };
1452
1453 static struct atmel_uart_data uart1_data = {
1454 .use_dma_tx = 1,
1455 .use_dma_rx = 1,
1456 };
1457
1458 static u64 uart1_dmamask = DMA_BIT_MASK(32);
1459
1460 static struct platform_device at91sam9g45_uart1_device = {
1461 .name = "atmel_usart",
1462 .id = 2,
1463 .dev = {
1464 .dma_mask = &uart1_dmamask,
1465 .coherent_dma_mask = DMA_BIT_MASK(32),
1466 .platform_data = &uart1_data,
1467 },
1468 .resource = uart1_resources,
1469 .num_resources = ARRAY_SIZE(uart1_resources),
1470 };
1471
1472 static inline void configure_usart1_pins(unsigned pins)
1473 {
1474 at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */
1475 at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */
1476
1477 if (pins & ATMEL_UART_RTS)
1478 at91_set_A_periph(AT91_PIN_PD16, 0); /* RTS1 */
1479 if (pins & ATMEL_UART_CTS)
1480 at91_set_A_periph(AT91_PIN_PD17, 0); /* CTS1 */
1481 }
1482
1483 static struct resource uart2_resources[] = {
1484 [0] = {
1485 .start = AT91SAM9G45_BASE_US2,
1486 .end = AT91SAM9G45_BASE_US2 + SZ_16K - 1,
1487 .flags = IORESOURCE_MEM,
1488 },
1489 [1] = {
1490 .start = AT91SAM9G45_ID_US2,
1491 .end = AT91SAM9G45_ID_US2,
1492 .flags = IORESOURCE_IRQ,
1493 },
1494 };
1495
1496 static struct atmel_uart_data uart2_data = {
1497 .use_dma_tx = 1,
1498 .use_dma_rx = 1,
1499 };
1500
1501 static u64 uart2_dmamask = DMA_BIT_MASK(32);
1502
1503 static struct platform_device at91sam9g45_uart2_device = {
1504 .name = "atmel_usart",
1505 .id = 3,
1506 .dev = {
1507 .dma_mask = &uart2_dmamask,
1508 .coherent_dma_mask = DMA_BIT_MASK(32),
1509 .platform_data = &uart2_data,
1510 },
1511 .resource = uart2_resources,
1512 .num_resources = ARRAY_SIZE(uart2_resources),
1513 };
1514
1515 static inline void configure_usart2_pins(unsigned pins)
1516 {
1517 at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD2 */
1518 at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD2 */
1519
1520 if (pins & ATMEL_UART_RTS)
1521 at91_set_B_periph(AT91_PIN_PC9, 0); /* RTS2 */
1522 if (pins & ATMEL_UART_CTS)
1523 at91_set_B_periph(AT91_PIN_PC11, 0); /* CTS2 */
1524 }
1525
1526 static struct resource uart3_resources[] = {
1527 [0] = {
1528 .start = AT91SAM9G45_BASE_US3,
1529 .end = AT91SAM9G45_BASE_US3 + SZ_16K - 1,
1530 .flags = IORESOURCE_MEM,
1531 },
1532 [1] = {
1533 .start = AT91SAM9G45_ID_US3,
1534 .end = AT91SAM9G45_ID_US3,
1535 .flags = IORESOURCE_IRQ,
1536 },
1537 };
1538
1539 static struct atmel_uart_data uart3_data = {
1540 .use_dma_tx = 1,
1541 .use_dma_rx = 1,
1542 };
1543
1544 static u64 uart3_dmamask = DMA_BIT_MASK(32);
1545
1546 static struct platform_device at91sam9g45_uart3_device = {
1547 .name = "atmel_usart",
1548 .id = 4,
1549 .dev = {
1550 .dma_mask = &uart3_dmamask,
1551 .coherent_dma_mask = DMA_BIT_MASK(32),
1552 .platform_data = &uart3_data,
1553 },
1554 .resource = uart3_resources,
1555 .num_resources = ARRAY_SIZE(uart3_resources),
1556 };
1557
1558 static inline void configure_usart3_pins(unsigned pins)
1559 {
1560 at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD3 */
1561 at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD3 */
1562
1563 if (pins & ATMEL_UART_RTS)
1564 at91_set_B_periph(AT91_PIN_PA23, 0); /* RTS3 */
1565 if (pins & ATMEL_UART_CTS)
1566 at91_set_B_periph(AT91_PIN_PA24, 0); /* CTS3 */
1567 }
1568
1569 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1570 struct platform_device *atmel_default_console_device; /* the serial console device */
1571
1572 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1573 {
1574 struct platform_device *pdev;
1575 struct atmel_uart_data *pdata;
1576
1577 switch (id) {
1578 case 0: /* DBGU */
1579 pdev = &at91sam9g45_dbgu_device;
1580 configure_dbgu_pins();
1581 break;
1582 case AT91SAM9G45_ID_US0:
1583 pdev = &at91sam9g45_uart0_device;
1584 configure_usart0_pins(pins);
1585 break;
1586 case AT91SAM9G45_ID_US1:
1587 pdev = &at91sam9g45_uart1_device;
1588 configure_usart1_pins(pins);
1589 break;
1590 case AT91SAM9G45_ID_US2:
1591 pdev = &at91sam9g45_uart2_device;
1592 configure_usart2_pins(pins);
1593 break;
1594 case AT91SAM9G45_ID_US3:
1595 pdev = &at91sam9g45_uart3_device;
1596 configure_usart3_pins(pins);
1597 break;
1598 default:
1599 return;
1600 }
1601 pdata = pdev->dev.platform_data;
1602 pdata->num = portnr; /* update to mapped ID */
1603
1604 if (portnr < ATMEL_MAX_UART)
1605 at91_uarts[portnr] = pdev;
1606 }
1607
1608 void __init at91_set_serial_console(unsigned portnr)
1609 {
1610 if (portnr < ATMEL_MAX_UART) {
1611 atmel_default_console_device = at91_uarts[portnr];
1612 at91sam9g45_set_console_clock(at91_uarts[portnr]->id);
1613 }
1614 }
1615
1616 void __init at91_add_device_serial(void)
1617 {
1618 int i;
1619
1620 for (i = 0; i < ATMEL_MAX_UART; i++) {
1621 if (at91_uarts[i])
1622 platform_device_register(at91_uarts[i]);
1623 }
1624
1625 if (!atmel_default_console_device)
1626 printk(KERN_INFO "AT91: No default serial console defined.\n");
1627 }
1628 #else
1629 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1630 void __init at91_set_serial_console(unsigned portnr) {}
1631 void __init at91_add_device_serial(void) {}
1632 #endif
1633
1634
1635 /* -------------------------------------------------------------------- */
1636 /*
1637 * These devices are always present and don't need any board-specific
1638 * setup.
1639 */
1640 static int __init at91_add_standard_devices(void)
1641 {
1642 at91_add_device_hdmac();
1643 at91_add_device_rtc();
1644 at91_add_device_rtt();
1645 at91_add_device_trng();
1646 at91_add_device_watchdog();
1647 at91_add_device_tc();
1648 return 0;
1649 }
1650
1651 arch_initcall(at91_add_standard_devices);