arch/arm/mach-at91/at91sam9g45_reset.S

   1 /*
   2  * reset AT91SAM9G45 as per errata
   3  *
   4  * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com>
   5  *
   6  * unless the SDRAM is cleanly shutdown before we hit the
   7  * reset register it can be left driving the data bus and
   8  * killing the chance of a subsequent boot from NAND
   9  *
  10  * GPLv2 Only
  11  */
  12
  13 #include <linux/linkage.h>
  14 #include <mach/hardware.h>
  15 #include <mach/at91sam9_ddrsdr.h>
  16 #include <mach/at91_rstc.h>
  17
  18                         .arm
  19
  20                         .globl  at91sam9g45_restart
  21
  22 at91sam9g45_restart:
  23                         ldr     r0, .at91_va_base_sdramc0       @ preload constants
  24                         ldr     r1, =at91_rstc_base
  25                         ldr     r1, [r1]
  26
  27                         mov     r2, #1
  28                         mov     r3, #AT91_DDRSDRC_LPCB_POWER_DOWN
  29                         ldr     r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST
  30
  31                         .balign 32                              @ align to cache line
  32
  33                         str     r2, [r0, #AT91_DDRSDRC_RTR]     @ disable DDR0 access
  34                         str     r3, [r0, #AT91_DDRSDRC_LPR]     @ power down DDR0
  35                         str     r4, [r1, #AT91_RSTC_CR]         @ reset processor
  36
  37                         b       .
  38
  39 .at91_va_base_sdramc0:
  40         .word AT91_VA_BASE_SYS + AT91_DDRSDRC0