arch/arm/mach-at91/include/mach/at91_rstc.h

   1 /*
   2  * arch/arm/mach-at91/include/mach/at91_rstc.h
   3  *
   4  * Copyright (C) 2007 Andrew Victor
   5  * Copyright (C) 2007 Atmel Corporation.
   6  *
   7  * Reset Controller (RSTC) - System peripherals regsters.
   8  * Based on AT91SAM9261 datasheet revision D.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  */
  15
  16 #ifndef AT91_RSTC_H
  17 #define AT91_RSTC_H
  18
  19 #ifndef __ASSEMBLY__
  20 extern void __iomem *at91_rstc_base;
  21
  22 #define at91_rstc_read(field) \
  23         __raw_readl(at91_rstc_base + field)
  24
  25 #define at91_rstc_write(field, value) \
  26         __raw_writel(value, at91_rstc_base + field);
  27 #else
  28 .extern at91_rstc_base
  29 #endif
  30
  31 #define AT91_RSTC_CR            0x00                    /* Reset Controller Control Register */
  32 #define         AT91_RSTC_PROCRST       (1 << 0)                /* Processor Reset */
  33 #define         AT91_RSTC_PERRST        (1 << 2)                /* Peripheral Reset */
  34 #define         AT91_RSTC_EXTRST        (1 << 3)                /* External Reset */
  35 #define         AT91_RSTC_KEY           (0xa5 << 24)            /* KEY Password */
  36
  37 #define AT91_RSTC_SR            0x04                    /* Reset Controller Status Register */
  38 #define         AT91_RSTC_URSTS         (1 << 0)                /* User Reset Status */
  39 #define         AT91_RSTC_RSTTYP        (7 << 8)                /* Reset Type */
  40 #define                 AT91_RSTC_RSTTYP_GENERAL        (0 << 8)
  41 #define                 AT91_RSTC_RSTTYP_WAKEUP         (1 << 8)
  42 #define                 AT91_RSTC_RSTTYP_WATCHDOG       (2 << 8)
  43 #define                 AT91_RSTC_RSTTYP_SOFTWARE       (3 << 8)
  44 #define                 AT91_RSTC_RSTTYP_USER   (4 << 8)
  45 #define         AT91_RSTC_NRSTL         (1 << 16)               /* NRST Pin Level */
  46 #define         AT91_RSTC_SRCMP         (1 << 17)               /* Software Reset Command in Progress */
  47
  48 #define AT91_RSTC_MR            0x08                    /* Reset Controller Mode Register */
  49 #define         AT91_RSTC_URSTEN        (1 << 0)                /* User Reset Enable */
  50 #define         AT91_RSTC_URSTIEN       (1 << 4)                /* User Reset Interrupt Enable */
  51 #define         AT91_RSTC_ERSTL         (0xf << 8)              /* External Reset Length */
  52
  53 #endif