arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h

   1 /*
   2  * Header file for the Atmel DDR/SDR SDRAM Controller
   3  *
   4  * Copyright (C) 2010 Atmel Corporation
   5  *      Nicolas Ferre <nicolas.ferre@atmel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  */
  12 #ifndef AT91SAM9_DDRSDR_H
  13 #define AT91SAM9_DDRSDR_H
  14
  15 #define AT91_DDRSDRC_MR         0x00    /* Mode Register */
  16 #define         AT91_DDRSDRC_MODE       (0x7 << 0)              /* Command Mode */
  17 #define                 AT91_DDRSDRC_MODE_NORMAL        0
  18 #define                 AT91_DDRSDRC_MODE_NOP           1
  19 #define                 AT91_DDRSDRC_MODE_PRECHARGE     2
  20 #define                 AT91_DDRSDRC_MODE_LMR           3
  21 #define                 AT91_DDRSDRC_MODE_REFRESH       4
  22 #define                 AT91_DDRSDRC_MODE_EXT_LMR       5
  23 #define                 AT91_DDRSDRC_MODE_DEEP          6
  24
  25 #define AT91_DDRSDRC_RTR        0x04    /* Refresh Timer Register */
  26 #define         AT91_DDRSDRC_COUNT      (0xfff << 0)            /* Refresh Timer Counter */
  27
  28 #define AT91_DDRSDRC_CR         0x08    /* Configuration Register */
  29 #define         AT91_DDRSDRC_NC         (3 << 0)                /* Number of Column Bits */
  30 #define                 AT91_DDRSDRC_NC_SDR8    (0 << 0)
  31 #define                 AT91_DDRSDRC_NC_SDR9    (1 << 0)
  32 #define                 AT91_DDRSDRC_NC_SDR10   (2 << 0)
  33 #define                 AT91_DDRSDRC_NC_SDR11   (3 << 0)
  34 #define                 AT91_DDRSDRC_NC_DDR9    (0 << 0)
  35 #define                 AT91_DDRSDRC_NC_DDR10   (1 << 0)
  36 #define                 AT91_DDRSDRC_NC_DDR11   (2 << 0)
  37 #define                 AT91_DDRSDRC_NC_DDR12   (3 << 0)
  38 #define         AT91_DDRSDRC_NR         (3 << 2)                /* Number of Row Bits */
  39 #define                 AT91_DDRSDRC_NR_11      (0 << 2)
  40 #define                 AT91_DDRSDRC_NR_12      (1 << 2)
  41 #define                 AT91_DDRSDRC_NR_13      (2 << 2)
  42 #define                 AT91_DDRSDRC_NR_14      (3 << 2)
  43 #define         AT91_DDRSDRC_CAS        (7 << 4)                /* CAS Latency */
  44 #define                 AT91_DDRSDRC_CAS_2      (2 << 4)
  45 #define                 AT91_DDRSDRC_CAS_3      (3 << 4)
  46 #define                 AT91_DDRSDRC_CAS_25     (6 << 4)
  47 #define         AT91_DDRSDRC_RST_DLL    (1 << 7)                /* Reset DLL */
  48 #define         AT91_DDRSDRC_DICDS      (1 << 8)                /* Output impedance control */
  49 #define         AT91_DDRSDRC_DIS_DLL    (1 << 9)                /* Disable DLL [SAM9 Only] */
  50 #define         AT91_DDRSDRC_OCD        (1 << 12)               /* Off-Chip Driver [SAM9 Only] */
  51 #define         AT91_DDRSDRC_DQMS       (1 << 16)               /* Mask Data is Shared [SAM9 Only] */
  52 #define         AT91_DDRSDRC_ACTBST     (1 << 18)               /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Only] */
  53
  54 #define AT91_DDRSDRC_T0PR       0x0C    /* Timing 0 Register */
  55 #define         AT91_DDRSDRC_TRAS       (0xf <<  0)             /* Active to Precharge delay */
  56 #define         AT91_DDRSDRC_TRCD       (0xf <<  4)             /* Row to Column delay */
  57 #define         AT91_DDRSDRC_TWR        (0xf <<  8)             /* Write recovery delay */
  58 #define         AT91_DDRSDRC_TRC        (0xf << 12)             /* Row cycle delay */
  59 #define         AT91_DDRSDRC_TRP        (0xf << 16)             /* Row precharge delay */
  60 #define         AT91_DDRSDRC_TRRD       (0xf << 20)             /* Active BankA to BankB */
  61 #define         AT91_DDRSDRC_TWTR       (0x7 << 24)             /* Internal Write to Read delay */
  62 #define         AT91CAP9_DDRSDRC_TWTR   (1   << 24)             /* Internal Write to Read delay */
  63 #define         AT91_DDRSDRC_RED_WRRD   (0x1 << 27)             /* Reduce Write to Read Delay [SAM9 Only] */
  64 #define         AT91_DDRSDRC_TMRD       (0xf << 28)             /* Load mode to active/refresh delay */
  65
  66 #define AT91_DDRSDRC_T1PR       0x10    /* Timing 1 Register */
  67 #define         AT91_DDRSDRC_TRFC       (0x1f << 0)             /* Row Cycle Delay */
  68 #define         AT91_DDRSDRC_TXSNR      (0xff << 8)             /* Exit self-refresh to non-read */
  69 #define         AT91_DDRSDRC_TXSRD      (0xff << 16)            /* Exit self-refresh to read */
  70 #define         AT91_DDRSDRC_TXP        (0xf  << 24)            /* Exit power-down delay */
  71
  72 #define AT91_DDRSDRC_T2PR       0x14    /* Timing 2 Register [SAM9 Only] */
  73 #define         AT91_DDRSDRC_TXARD      (0xf  << 0)             /* Exit active power down delay to read command in mode "Fast Exit" */
  74 #define         AT91_DDRSDRC_TXARDS     (0xf  << 4)             /* Exit active power down delay to read command in mode "Slow Exit" */
  75 #define         AT91_DDRSDRC_TRPA       (0xf  << 8)             /* Row Precharge All delay */
  76 #define         AT91_DDRSDRC_TRTP       (0x7  << 12)            /* Read to Precharge delay */
  77
  78 #define AT91_DDRSDRC_LPR        0x1C    /* Low Power Register */
  79 #define AT91CAP9_DDRSDRC_LPR    0x18    /* Low Power Register */
  80 #define         AT91_DDRSDRC_LPCB       (3 << 0)                /* Low-power Configurations */
  81 #define                 AT91_DDRSDRC_LPCB_DISABLE               0
  82 #define                 AT91_DDRSDRC_LPCB_SELF_REFRESH          1
  83 #define                 AT91_DDRSDRC_LPCB_POWER_DOWN            2
  84 #define                 AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN       3
  85 #define         AT91_DDRSDRC_CLKFR      (1 << 2)        /* Clock Frozen */
  86 #define         AT91_DDRSDRC_PASR       (7 << 4)        /* Partial Array Self Refresh */
  87 #define         AT91_DDRSDRC_TCSR       (3 << 8)        /* Temperature Compensated Self Refresh */
  88 #define         AT91_DDRSDRC_DS         (3 << 10)       /* Drive Strength */
  89 #define         AT91_DDRSDRC_TIMEOUT    (3 << 12)       /* Time to define when Low Power Mode is enabled */
  90 #define                 AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES       (0 << 12)
  91 #define                 AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES      (1 << 12)
  92 #define                 AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES     (2 << 12)
  93 #define         AT91_DDRSDRC_APDE       (1 << 16)        /* Active power down exit time */
  94 #define         AT91_DDRSDRC_UPD_MR     (3 << 20)        /* Update load mode register and extended mode register */
  95
  96 #define AT91_DDRSDRC_MDR        0x20    /* Memory Device Register */
  97 #define AT91CAP9_DDRSDRC_MDR    0x1C    /* Memory Device Register */
  98 #define         AT91_DDRSDRC_MD         (3 << 0)                /* Memory Device Type */
  99 #define                 AT91_DDRSDRC_MD_SDR             0
 100 #define                 AT91_DDRSDRC_MD_LOW_POWER_SDR   1
 101 #define                 AT91CAP9_DDRSDRC_MD_DDR         2
 102 #define                 AT91_DDRSDRC_MD_LOW_POWER_DDR   3
 103 #define                 AT91_DDRSDRC_MD_DDR2            6       /* [SAM9 Only] */
 104 #define         AT91_DDRSDRC_DBW        (1 << 4)                /* Data Bus Width */
 105 #define                 AT91_DDRSDRC_DBW_32BITS         (0 <<  4)
 106 #define                 AT91_DDRSDRC_DBW_16BITS         (1 <<  4)
 107
 108 #define AT91_DDRSDRC_DLL        0x24    /* DLL Information Register */
 109 #define AT91CAP9_DDRSDRC_DLL    0x20    /* DLL Information Register */
 110 #define         AT91_DDRSDRC_MDINC      (1 << 0)                /* Master Delay increment */
 111 #define         AT91_DDRSDRC_MDDEC      (1 << 1)                /* Master Delay decrement */
 112 #define         AT91_DDRSDRC_MDOVF      (1 << 2)                /* Master Delay Overflow */
 113 #define         AT91CAP9_DDRSDRC_SDCOVF (1 << 3)                /* Slave Delay Correction Overflow */
 114 #define         AT91CAP9_DDRSDRC_SDCUDF (1 << 4)                /* Slave Delay Correction Underflow */
 115 #define         AT91CAP9_DDRSDRC_SDERF  (1 << 5)                /* Slave Delay Correction error */
 116 #define         AT91_DDRSDRC_MDVAL      (0xff <<  8)            /* Master Delay value */
 117 #define         AT91CAP9_DDRSDRC_SDVAL  (0xff << 16)            /* Slave Delay value */
 118 #define         AT91CAP9_DDRSDRC_SDCVAL (0xff << 24)            /* Slave Delay Correction value */
 119
 120 #define AT91_DDRSDRC_HS         0x2C    /* High Speed Register [SAM9 Only] */
 121 #define         AT91_DDRSDRC_DIS_ATCP_RD        (1 << 2)        /* Anticip read access is disabled */
 122
 123 #define AT91_DDRSDRC_DELAY(n)   (0x30 + (0x4 * (n)))    /* Delay I/O Register n */
 124
 125 #define AT91_DDRSDRC_WPMR       0xE4    /* Write Protect Mode Register [SAM9 Only] */
 126 #define         AT91_DDRSDRC_WP         (1 << 0)                /* Write protect enable */
 127 #define         AT91_DDRSDRC_WPKEY      (0xffffff << 8)         /* Write protect key */
 128 #define         AT91_DDRSDRC_KEY        (0x444452 << 8)         /* Write protect key = "DDR" */
 129
 130 #define AT91_DDRSDRC_WPSR       0xE8    /* Write Protect Status Register [SAM9 Only] */
 131 #define         AT91_DDRSDRC_WPVS       (1 << 0)                /* Write protect violation status */
 132 #define         AT91_DDRSDRC_WPVSRC     (0xffff << 8)           /* Write protect violation source */
 133
 134 /* Register access macros */
 135 #define at91_ramc_read(num, reg) \
 136         at91_sys_read(AT91_DDRSDRC##num + reg)
 137 #define at91_ramc_write(num, reg, value) \
 138         at91_sys_write(AT91_DDRSDRC##num + reg, value)
 139
 140 #endif