spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / mach-at91 / include / mach / entry-macro.S
blob423eea0ed74c31921551c5e53a6b2f1f0332ec3a
1 /*
2  * arch/arm/mach-at91/include/mach/entry-macro.S
3  *
4  *  Copyright (C) 2003-2005 SAN People
5  *
6  * Low-level IRQ helper macros for AT91RM9200 platforms
7  *
8  * This file is licensed under the terms of the GNU General Public
9  * License version 2. This program is licensed "as is" without any
10  * warranty of any kind, whether express or implied.
11  */
13 #include <mach/hardware.h>
14 #include <mach/at91_aic.h>
16         .macro  disable_fiq
17         .endm
19         .macro  get_irqnr_preamble, base, tmp
20         ldr     \base, =at91_aic_base           @ base virtual address of AIC peripheral
21         ldr     \base, [\base]
22         .endm
24         .macro  arch_ret_to_user, tmp1, tmp2
25         .endm
27         .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
28         ldr     \irqnr, [\base, #AT91_AIC_IVR]          @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
29         ldr     \irqstat, [\base, #AT91_AIC_ISR]        @ read interrupt source number
30         teq     \irqstat, #0                            @ ISR is 0 when no current interrupt, or spurious interrupt
31         streq   \tmp, [\base, #AT91_AIC_EOICR]          @ not going to be handled further, then ACK it now.
32         .endm