spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / mach-at91 / include / mach / gsia18s.h
blob307c194926f9b2a7615d416c7d563388ed861232
1 /* Buttons */
2 #define GPIO_TRIG_NET_IN AT91_PIN_PB21
3 #define GPIO_CARD_UNMOUNT_0 AT91_PIN_PB13
4 #define GPIO_CARD_UNMOUNT_1 AT91_PIN_PB12
5 #define GPIO_KEY_POWER AT91_PIN_PA25
7 /* PCF8574 0x20 GPIO - U1 on the GS_IA18-CB_V3 board */
8 #define GS_IA18_S_PCF_GPIO_BASE0 NR_BUILTIN_GPIO
9 #define PCF_GPIO_HDC_POWER (GS_IA18_S_PCF_GPIO_BASE0 + 0)
10 #define PCF_GPIO_WIFI_SETUP (GS_IA18_S_PCF_GPIO_BASE0 + 1)
11 #define PCF_GPIO_WIFI_ENABLE (GS_IA18_S_PCF_GPIO_BASE0 + 2)
12 #define PCF_GPIO_WIFI_RESET (GS_IA18_S_PCF_GPIO_BASE0 + 3)
13 #define PCF_GPIO_ETH_DETECT 4 /* this is a GPI */
14 #define PCF_GPIO_GPS_SETUP (GS_IA18_S_PCF_GPIO_BASE0 + 5)
15 #define PCF_GPIO_GPS_STANDBY (GS_IA18_S_PCF_GPIO_BASE0 + 6)
16 #define PCF_GPIO_GPS_POWER (GS_IA18_S_PCF_GPIO_BASE0 + 7)
18 /* PCF8574 0x22 GPIO - U1 on the GS_2G_OPT1-A_V0 board (Alarm) */
19 #define GS_IA18_S_PCF_GPIO_BASE1 (GS_IA18_S_PCF_GPIO_BASE0 + 8)
20 #define PCF_GPIO_ALARM1 (GS_IA18_S_PCF_GPIO_BASE1 + 0)
21 #define PCF_GPIO_ALARM2 (GS_IA18_S_PCF_GPIO_BASE1 + 1)
22 #define PCF_GPIO_ALARM3 (GS_IA18_S_PCF_GPIO_BASE1 + 2)
23 #define PCF_GPIO_ALARM4 (GS_IA18_S_PCF_GPIO_BASE1 + 3)
24 /* bits 4, 5, 6 not used */
25 #define PCF_GPIO_ALARM_V_RELAY_ON (GS_IA18_S_PCF_GPIO_BASE1 + 7)
27 /* PCF8574 0x24 GPIO U1 on the GS_2G-OPT23-A_V0 board (Modem) */
28 #define GS_IA18_S_PCF_GPIO_BASE2 (GS_IA18_S_PCF_GPIO_BASE1 + 8)
29 #define PCF_GPIO_MODEM_POWER (GS_IA18_S_PCF_GPIO_BASE2 + 0)
30 #define PCF_GPIO_MODEM_RESET (GS_IA18_S_PCF_GPIO_BASE2 + 3)
31 /* bits 1, 2, 4, 5 not used */
32 #define PCF_GPIO_TRX_RESET (GS_IA18_S_PCF_GPIO_BASE2 + 6)
33 /* bit 7 not used */