spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / mach-at91 / include / mach / hardware.h
blob2d0e4e99856624415d72e1ddcae38bb1f6dadb32
1 /*
2 * arch/arm/mach-at91/include/mach/hardware.h
4 * Copyright (C) 2003 SAN People
5 * Copyright (C) 2003 ATMEL
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
14 #ifndef __ASM_ARCH_HARDWARE_H
15 #define __ASM_ARCH_HARDWARE_H
17 #include <asm/sizes.h>
19 /* DBGU base */
20 /* rm9200, 9260/9g20, 9261/9g10, 9rl */
21 #define AT91_BASE_DBGU0 0xfffff200
22 /* 9263, 9g45, cap9 */
23 #define AT91_BASE_DBGU1 0xffffee00
25 #if defined(CONFIG_ARCH_AT91RM9200)
26 #include <mach/at91rm9200.h>
27 #elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)
28 #include <mach/at91sam9260.h>
29 #elif defined(CONFIG_ARCH_AT91SAM9261) || defined(CONFIG_ARCH_AT91SAM9G10)
30 #include <mach/at91sam9261.h>
31 #elif defined(CONFIG_ARCH_AT91SAM9263)
32 #include <mach/at91sam9263.h>
33 #elif defined(CONFIG_ARCH_AT91SAM9RL)
34 #include <mach/at91sam9rl.h>
35 #elif defined(CONFIG_ARCH_AT91SAM9G45)
36 #include <mach/at91sam9g45.h>
37 #elif defined(CONFIG_ARCH_AT91CAP9)
38 #include <mach/at91cap9.h>
39 #elif defined(CONFIG_ARCH_AT91X40)
40 #include <mach/at91x40.h>
41 #else
42 #error "Unsupported AT91 processor"
43 #endif
45 #if !defined(CONFIG_ARCH_AT91X40)
47 * On all at91 except rm9200 and x40 have the System Controller starts
48 * at address 0xffffc000 and has a size of 16KiB.
50 * On rm9200 it's start at 0xfffe4000 of 111KiB with non reserved data starting
51 * at 0xfffff000
53 * Removes the individual definitions of AT91_BASE_SYS and
54 * replaces them with a common version at base 0xfffffc000 and size 16KiB
55 * and map the same memory space
57 #define AT91_BASE_SYS 0xffffc000
58 #endif
61 * On all at91 have the Advanced Interrupt Controller starts at address
62 * 0xfffff000
64 #define AT91_AIC 0xfffff000
67 * Peripheral identifiers/interrupts.
69 #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
70 #define AT91_ID_SYS 1 /* System Peripherals */
72 #ifdef CONFIG_MMU
74 * Remap the peripherals from address 0xFFF78000 .. 0xFFFFFFFF
75 * to 0xFEF78000 .. 0xFF000000. (544Kb)
77 #define AT91_IO_PHYS_BASE 0xFFF78000
78 #define AT91_IO_VIRT_BASE (0xFF000000 - AT91_IO_SIZE)
79 #else
81 * Identity mapping for the non MMU case.
83 #define AT91_IO_PHYS_BASE AT91_BASE_SYS
84 #define AT91_IO_VIRT_BASE AT91_IO_PHYS_BASE
85 #endif
87 #define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1)
89 /* Convert a physical IO address to virtual IO address */
90 #define AT91_IO_P2V(x) ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE)
93 * Virtual to Physical Address mapping for IO devices.
95 #define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS)
96 #define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91RM9200_BASE_EMAC)
98 /* Internal SRAM is mapped below the IO devices */
99 #define AT91_SRAM_MAX SZ_1M
100 #define AT91_VIRT_BASE (AT91_IO_VIRT_BASE - AT91_SRAM_MAX)
102 /* Serial ports */
103 #define ATMEL_MAX_UART 7 /* 6 USART3's and one DBGU port (SAM9260) */
105 /* External Memory Map */
106 #define AT91_CHIPSELECT_0 0x10000000
107 #define AT91_CHIPSELECT_1 0x20000000
108 #define AT91_CHIPSELECT_2 0x30000000
109 #define AT91_CHIPSELECT_3 0x40000000
110 #define AT91_CHIPSELECT_4 0x50000000
111 #define AT91_CHIPSELECT_5 0x60000000
112 #define AT91_CHIPSELECT_6 0x70000000
113 #define AT91_CHIPSELECT_7 0x80000000
115 /* Clocks */
116 #define AT91_SLOW_CLOCK 32768 /* slow clock */
119 #endif