arch/arm/mach-exynos/clock-exynos4210.c

   1 /*
   2  * linux/arch/arm/mach-exynos4/clock-exynos4210.c
   3  *
   4  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * EXYNOS4210 - Clock support
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12 */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/err.h>
  16 #include <linux/clk.h>
  17 #include <linux/io.h>
  18 #include <linux/syscore_ops.h>
  19
  20 #include <plat/cpu-freq.h>
  21 #include <plat/clock.h>
  22 #include <plat/cpu.h>
  23 #include <plat/pll.h>
  24 #include <plat/s5p-clock.h>
  25 #include <plat/clock-clksrc.h>
  26 #include <plat/pm.h>
  27
  28 #include <mach/hardware.h>
  29 #include <mach/map.h>
  30 #include <mach/regs-clock.h>
  31 #include <mach/exynos4-clock.h>
  32
  33 #include "common.h"
  34
  35 #ifdef CONFIG_PM_SLEEP
  36 static struct sleep_save exynos4210_clock_save[] = {
  37         SAVE_ITEM(S5P_CLKSRC_IMAGE),
  38         SAVE_ITEM(S5P_CLKSRC_LCD1),
  39         SAVE_ITEM(S5P_CLKDIV_IMAGE),
  40         SAVE_ITEM(S5P_CLKDIV_LCD1),
  41         SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
  42         SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),
  43         SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
  44         SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
  45 };
  46 #endif
  47
  48 static struct clksrc_clk *sysclks[] = {
  49         /* nothing here yet */
  50 };
  51
  52 static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
  53 {
  54         return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
  55 }
  56
  57 static struct clksrc_clk clksrcs[] = {
  58         {
  59                 .clk            = {
  60                         .name           = "sclk_sata",
  61                         .id             = -1,
  62                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
  63                         .ctrlbit        = (1 << 24),
  64                 },
  65                 .sources = &clkset_mout_corebus,
  66                 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
  67                 .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
  68         }, {
  69                 .clk            = {
  70                         .name           = "sclk_fimd",
  71                         .devname        = "exynos4-fb.1",
  72                         .enable         = exynos4_clksrc_mask_lcd1_ctrl,
  73                         .ctrlbit        = (1 << 0),
  74                 },
  75                 .sources = &clkset_group,
  76                 .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
  77                 .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
  78         },
  79 };
  80
  81 static struct clk init_clocks_off[] = {
  82         {
  83                 .name           = "sataphy",
  84                 .id             = -1,
  85                 .parent         = &clk_aclk_133.clk,
  86                 .enable         = exynos4_clk_ip_fsys_ctrl,
  87                 .ctrlbit        = (1 << 3),
  88         }, {
  89                 .name           = "sata",
  90                 .id             = -1,
  91                 .parent         = &clk_aclk_133.clk,
  92                 .enable         = exynos4_clk_ip_fsys_ctrl,
  93                 .ctrlbit        = (1 << 10),
  94         }, {
  95                 .name           = "fimd",
  96                 .devname        = "exynos4-fb.1",
  97                 .enable         = exynos4_clk_ip_lcd1_ctrl,
  98                 .ctrlbit        = (1 << 0),
  99         },
 100 };
 101
 102 #ifdef CONFIG_PM_SLEEP
 103 static int exynos4210_clock_suspend(void)
 104 {
 105         s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
 106
 107         return 0;
 108 }
 109
 110 static void exynos4210_clock_resume(void)
 111 {
 112         s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
 113 }
 114
 115 #else
 116 #define exynos4210_clock_suspend NULL
 117 #define exynos4210_clock_resume NULL
 118 #endif
 119
 120 struct syscore_ops exynos4210_clock_syscore_ops = {
 121         .suspend        = exynos4210_clock_suspend,
 122         .resume         = exynos4210_clock_resume,
 123 };
 124
 125 void __init exynos4210_register_clocks(void)
 126 {
 127         int ptr;
 128
 129         clk_mout_mpll.reg_src.reg = S5P_CLKSRC_CPU;
 130         clk_mout_mpll.reg_src.shift = 8;
 131         clk_mout_mpll.reg_src.size = 1;
 132
 133         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
 134                 s3c_register_clksrc(sysclks[ptr], 1);
 135
 136         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
 137
 138         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 139         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 140
 141         register_syscore_ops(&exynos4210_clock_syscore_ops);
 142 }