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spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / mach-exynos / clock.c
blob187287aa57ab9154fbe7808bbd26ec895348ddd8
1 /* linux/arch/arm/mach-exynos4/clock.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - Clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/err.h>
15 #include <linux/io.h>
16 #include <linux/syscore_ops.h>
17
18 #include <plat/cpu-freq.h>
19 #include <plat/clock.h>
20 #include <plat/cpu.h>
21 #include <plat/pll.h>
22 #include <plat/s5p-clock.h>
23 #include <plat/clock-clksrc.h>
24 #include <plat/pm.h>
25
26 #include <mach/map.h>
27 #include <mach/regs-clock.h>
28 #include <mach/sysmmu.h>
29 #include <mach/exynos4-clock.h>
30
31 #include "common.h"
32
33 #ifdef CONFIG_PM_SLEEP
34 static struct sleep_save exynos4_clock_save[] = {
35 SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
36 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
37 SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
38 SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
39 SAVE_ITEM(S5P_CLKSRC_TOP0),
40 SAVE_ITEM(S5P_CLKSRC_TOP1),
41 SAVE_ITEM(S5P_CLKSRC_CAM),
42 SAVE_ITEM(S5P_CLKSRC_TV),
43 SAVE_ITEM(S5P_CLKSRC_MFC),
44 SAVE_ITEM(S5P_CLKSRC_G3D),
45 SAVE_ITEM(S5P_CLKSRC_LCD0),
46 SAVE_ITEM(S5P_CLKSRC_MAUDIO),
47 SAVE_ITEM(S5P_CLKSRC_FSYS),
48 SAVE_ITEM(S5P_CLKSRC_PERIL0),
49 SAVE_ITEM(S5P_CLKSRC_PERIL1),
50 SAVE_ITEM(S5P_CLKDIV_CAM),
51 SAVE_ITEM(S5P_CLKDIV_TV),
52 SAVE_ITEM(S5P_CLKDIV_MFC),
53 SAVE_ITEM(S5P_CLKDIV_G3D),
54 SAVE_ITEM(S5P_CLKDIV_LCD0),
55 SAVE_ITEM(S5P_CLKDIV_MAUDIO),
56 SAVE_ITEM(S5P_CLKDIV_FSYS0),
57 SAVE_ITEM(S5P_CLKDIV_FSYS1),
58 SAVE_ITEM(S5P_CLKDIV_FSYS2),
59 SAVE_ITEM(S5P_CLKDIV_FSYS3),
60 SAVE_ITEM(S5P_CLKDIV_PERIL0),
61 SAVE_ITEM(S5P_CLKDIV_PERIL1),
62 SAVE_ITEM(S5P_CLKDIV_PERIL2),
63 SAVE_ITEM(S5P_CLKDIV_PERIL3),
64 SAVE_ITEM(S5P_CLKDIV_PERIL4),
65 SAVE_ITEM(S5P_CLKDIV_PERIL5),
66 SAVE_ITEM(S5P_CLKDIV_TOP),
67 SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
68 SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
69 SAVE_ITEM(S5P_CLKSRC_MASK_TV),
70 SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
71 SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
72 SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
73 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
74 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
75 SAVE_ITEM(S5P_CLKDIV2_RATIO),
76 SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
77 SAVE_ITEM(S5P_CLKGATE_IP_CAM),
78 SAVE_ITEM(S5P_CLKGATE_IP_TV),
79 SAVE_ITEM(S5P_CLKGATE_IP_MFC),
80 SAVE_ITEM(S5P_CLKGATE_IP_G3D),
81 SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
82 SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
83 SAVE_ITEM(S5P_CLKGATE_IP_GPS),
84 SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
85 SAVE_ITEM(S5P_CLKGATE_BLOCK),
86 SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
87 SAVE_ITEM(S5P_CLKSRC_DMC),
88 SAVE_ITEM(S5P_CLKDIV_DMC0),
89 SAVE_ITEM(S5P_CLKDIV_DMC1),
90 SAVE_ITEM(S5P_CLKGATE_IP_DMC),
91 SAVE_ITEM(S5P_CLKSRC_CPU),
92 SAVE_ITEM(S5P_CLKDIV_CPU),
93 SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
94 SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
95 SAVE_ITEM(S5P_CLKGATE_IP_CPU),
96 };
97 #endif
98
99 struct clk clk_sclk_hdmi27m = {
100 .name = "sclk_hdmi27m",
101 .rate = 27000000,
102 };
103
104 struct clk clk_sclk_hdmiphy = {
105 .name = "sclk_hdmiphy",
106 };
107
108 struct clk clk_sclk_usbphy0 = {
109 .name = "sclk_usbphy0",
110 .rate = 27000000,
111 };
112
113 struct clk clk_sclk_usbphy1 = {
114 .name = "sclk_usbphy1",
115 };
116
117 static struct clk dummy_apb_pclk = {
118 .name = "apb_pclk",
119 .id = -1,
120 };
121
122 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
123 {
124 return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
125 }
126
127 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
128 {
129 return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
130 }
131
132 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
133 {
134 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
135 }
136
137 int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
138 {
139 return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
140 }
141
142 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
143 {
144 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
145 }
146
147 static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
148 {
149 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
150 }
151
152 static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
153 {
154 return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
155 }
156
157 static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
158 {
159 return s5p_gatectrl(S5P_CLKSRC_MASK_TV, clk, enable);
160 }
161
162 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
163 {
164 return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
165 }
166
167 static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
168 {
169 return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
170 }
171
172 static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
173 {
174 return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
175 }
176
177 static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
178 {
179 return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
180 }
181
182 int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
183 {
184 return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
185 }
186
187 int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
188 {
189 return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
190 }
191
192 static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
193 {
194 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
195 }
196
197 static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
198 {
199 return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
200 }
201
202 static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
203 {
204 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
205 }
206
207 static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
208 {
209 return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
210 }
211
212 /* Core list of CMU_CPU side */
213
214 static struct clksrc_clk clk_mout_apll = {
215 .clk = {
216 .name = "mout_apll",
217 },
218 .sources = &clk_src_apll,
219 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
220 };
221
222 struct clksrc_clk clk_sclk_apll = {
223 .clk = {
224 .name = "sclk_apll",
225 .parent = &clk_mout_apll.clk,
226 },
227 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
228 };
229
230 struct clksrc_clk clk_mout_epll = {
231 .clk = {
232 .name = "mout_epll",
233 },
234 .sources = &clk_src_epll,
235 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
236 };
237
238 struct clksrc_clk clk_mout_mpll = {
239 .clk = {
240 .name = "mout_mpll",
241 },
242 .sources = &clk_src_mpll,
243
244 /* reg_src will be added in each SoCs' clock */
245 };
246
247 static struct clk *clkset_moutcore_list[] = {
248 [0] = &clk_mout_apll.clk,
249 [1] = &clk_mout_mpll.clk,
250 };
251
252 static struct clksrc_sources clkset_moutcore = {
253 .sources = clkset_moutcore_list,
254 .nr_sources = ARRAY_SIZE(clkset_moutcore_list),
255 };
256
257 static struct clksrc_clk clk_moutcore = {
258 .clk = {
259 .name = "moutcore",
260 },
261 .sources = &clkset_moutcore,
262 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
263 };
264
265 static struct clksrc_clk clk_coreclk = {
266 .clk = {
267 .name = "core_clk",
268 .parent = &clk_moutcore.clk,
269 },
270 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
271 };
272
273 static struct clksrc_clk clk_armclk = {
274 .clk = {
275 .name = "armclk",
276 .parent = &clk_coreclk.clk,
277 },
278 };
279
280 static struct clksrc_clk clk_aclk_corem0 = {
281 .clk = {
282 .name = "aclk_corem0",
283 .parent = &clk_coreclk.clk,
284 },
285 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
286 };
287
288 static struct clksrc_clk clk_aclk_cores = {
289 .clk = {
290 .name = "aclk_cores",
291 .parent = &clk_coreclk.clk,
292 },
293 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
294 };
295
296 static struct clksrc_clk clk_aclk_corem1 = {
297 .clk = {
298 .name = "aclk_corem1",
299 .parent = &clk_coreclk.clk,
300 },
301 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
302 };
303
304 static struct clksrc_clk clk_periphclk = {
305 .clk = {
306 .name = "periphclk",
307 .parent = &clk_coreclk.clk,
308 },
309 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
310 };
311
312 /* Core list of CMU_CORE side */
313
314 struct clk *clkset_corebus_list[] = {
315 [0] = &clk_mout_mpll.clk,
316 [1] = &clk_sclk_apll.clk,
317 };
318
319 struct clksrc_sources clkset_mout_corebus = {
320 .sources = clkset_corebus_list,
321 .nr_sources = ARRAY_SIZE(clkset_corebus_list),
322 };
323
324 static struct clksrc_clk clk_mout_corebus = {
325 .clk = {
326 .name = "mout_corebus",
327 },
328 .sources = &clkset_mout_corebus,
329 .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
330 };
331
332 static struct clksrc_clk clk_sclk_dmc = {
333 .clk = {
334 .name = "sclk_dmc",
335 .parent = &clk_mout_corebus.clk,
336 },
337 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
338 };
339
340 static struct clksrc_clk clk_aclk_cored = {
341 .clk = {
342 .name = "aclk_cored",
343 .parent = &clk_sclk_dmc.clk,
344 },
345 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
346 };
347
348 static struct clksrc_clk clk_aclk_corep = {
349 .clk = {
350 .name = "aclk_corep",
351 .parent = &clk_aclk_cored.clk,
352 },
353 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
354 };
355
356 static struct clksrc_clk clk_aclk_acp = {
357 .clk = {
358 .name = "aclk_acp",
359 .parent = &clk_mout_corebus.clk,
360 },
361 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
362 };
363
364 static struct clksrc_clk clk_pclk_acp = {
365 .clk = {
366 .name = "pclk_acp",
367 .parent = &clk_aclk_acp.clk,
368 },
369 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
370 };
371
372 /* Core list of CMU_TOP side */
373
374 struct clk *clkset_aclk_top_list[] = {
375 [0] = &clk_mout_mpll.clk,
376 [1] = &clk_sclk_apll.clk,
377 };
378
379 struct clksrc_sources clkset_aclk = {
380 .sources = clkset_aclk_top_list,
381 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
382 };
383
384 static struct clksrc_clk clk_aclk_200 = {
385 .clk = {
386 .name = "aclk_200",
387 },
388 .sources = &clkset_aclk,
389 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
390 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
391 };
392
393 static struct clksrc_clk clk_aclk_100 = {
394 .clk = {
395 .name = "aclk_100",
396 },
397 .sources = &clkset_aclk,
398 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
399 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
400 };
401
402 static struct clksrc_clk clk_aclk_160 = {
403 .clk = {
404 .name = "aclk_160",
405 },
406 .sources = &clkset_aclk,
407 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
408 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
409 };
410
411 struct clksrc_clk clk_aclk_133 = {
412 .clk = {
413 .name = "aclk_133",
414 },
415 .sources = &clkset_aclk,
416 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
417 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
418 };
419
420 static struct clk *clkset_vpllsrc_list[] = {
421 [0] = &clk_fin_vpll,
422 [1] = &clk_sclk_hdmi27m,
423 };
424
425 static struct clksrc_sources clkset_vpllsrc = {
426 .sources = clkset_vpllsrc_list,
427 .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
428 };
429
430 static struct clksrc_clk clk_vpllsrc = {
431 .clk = {
432 .name = "vpll_src",
433 .enable = exynos4_clksrc_mask_top_ctrl,
434 .ctrlbit = (1 << 0),
435 },
436 .sources = &clkset_vpllsrc,
437 .reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
438 };
439
440 static struct clk *clkset_sclk_vpll_list[] = {
441 [0] = &clk_vpllsrc.clk,
442 [1] = &clk_fout_vpll,
443 };
444
445 static struct clksrc_sources clkset_sclk_vpll = {
446 .sources = clkset_sclk_vpll_list,
447 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
448 };
449
450 struct clksrc_clk clk_sclk_vpll = {
451 .clk = {
452 .name = "sclk_vpll",
453 },
454 .sources = &clkset_sclk_vpll,
455 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
456 };
457
458 static struct clk init_clocks_off[] = {
459 {
460 .name = "timers",
461 .parent = &clk_aclk_100.clk,
462 .enable = exynos4_clk_ip_peril_ctrl,
463 .ctrlbit = (1<<24),
464 }, {
465 .name = "csis",
466 .devname = "s5p-mipi-csis.0",
467 .enable = exynos4_clk_ip_cam_ctrl,
468 .ctrlbit = (1 << 4),
469 }, {
470 .name = "csis",
471 .devname = "s5p-mipi-csis.1",
472 .enable = exynos4_clk_ip_cam_ctrl,
473 .ctrlbit = (1 << 5),
474 }, {
475 .name = "fimc",
476 .devname = "exynos4-fimc.0",
477 .enable = exynos4_clk_ip_cam_ctrl,
478 .ctrlbit = (1 << 0),
479 }, {
480 .name = "fimc",
481 .devname = "exynos4-fimc.1",
482 .enable = exynos4_clk_ip_cam_ctrl,
483 .ctrlbit = (1 << 1),
484 }, {
485 .name = "fimc",
486 .devname = "exynos4-fimc.2",
487 .enable = exynos4_clk_ip_cam_ctrl,
488 .ctrlbit = (1 << 2),
489 }, {
490 .name = "fimc",
491 .devname = "exynos4-fimc.3",
492 .enable = exynos4_clk_ip_cam_ctrl,
493 .ctrlbit = (1 << 3),
494 }, {
495 .name = "fimd",
496 .devname = "exynos4-fb.0",
497 .enable = exynos4_clk_ip_lcd0_ctrl,
498 .ctrlbit = (1 << 0),
499 }, {
500 .name = "hsmmc",
501 .devname = "s3c-sdhci.0",
502 .parent = &clk_aclk_133.clk,
503 .enable = exynos4_clk_ip_fsys_ctrl,
504 .ctrlbit = (1 << 5),
505 }, {
506 .name = "hsmmc",
507 .devname = "s3c-sdhci.1",
508 .parent = &clk_aclk_133.clk,
509 .enable = exynos4_clk_ip_fsys_ctrl,
510 .ctrlbit = (1 << 6),
511 }, {
512 .name = "hsmmc",
513 .devname = "s3c-sdhci.2",
514 .parent = &clk_aclk_133.clk,
515 .enable = exynos4_clk_ip_fsys_ctrl,
516 .ctrlbit = (1 << 7),
517 }, {
518 .name = "hsmmc",
519 .devname = "s3c-sdhci.3",
520 .parent = &clk_aclk_133.clk,
521 .enable = exynos4_clk_ip_fsys_ctrl,
522 .ctrlbit = (1 << 8),
523 }, {
524 .name = "dwmmc",
525 .parent = &clk_aclk_133.clk,
526 .enable = exynos4_clk_ip_fsys_ctrl,
527 .ctrlbit = (1 << 9),
528 }, {
529 .name = "dac",
530 .devname = "s5p-sdo",
531 .enable = exynos4_clk_ip_tv_ctrl,
532 .ctrlbit = (1 << 2),
533 }, {
534 .name = "mixer",
535 .devname = "s5p-mixer",
536 .enable = exynos4_clk_ip_tv_ctrl,
537 .ctrlbit = (1 << 1),
538 }, {
539 .name = "vp",
540 .devname = "s5p-mixer",
541 .enable = exynos4_clk_ip_tv_ctrl,
542 .ctrlbit = (1 << 0),
543 }, {
544 .name = "hdmi",
545 .devname = "exynos4-hdmi",
546 .enable = exynos4_clk_ip_tv_ctrl,
547 .ctrlbit = (1 << 3),
548 }, {
549 .name = "hdmiphy",
550 .devname = "exynos4-hdmi",
551 .enable = exynos4_clk_hdmiphy_ctrl,
552 .ctrlbit = (1 << 0),
553 }, {
554 .name = "dacphy",
555 .devname = "s5p-sdo",
556 .enable = exynos4_clk_dac_ctrl,
557 .ctrlbit = (1 << 0),
558 }, {
559 .name = "adc",
560 .enable = exynos4_clk_ip_peril_ctrl,
561 .ctrlbit = (1 << 15),
562 }, {
563 .name = "keypad",
564 .enable = exynos4_clk_ip_perir_ctrl,
565 .ctrlbit = (1 << 16),
566 }, {
567 .name = "rtc",
568 .enable = exynos4_clk_ip_perir_ctrl,
569 .ctrlbit = (1 << 15),
570 }, {
571 .name = "watchdog",
572 .parent = &clk_aclk_100.clk,
573 .enable = exynos4_clk_ip_perir_ctrl,
574 .ctrlbit = (1 << 14),
575 }, {
576 .name = "usbhost",
577 .enable = exynos4_clk_ip_fsys_ctrl ,
578 .ctrlbit = (1 << 12),
579 }, {
580 .name = "otg",
581 .enable = exynos4_clk_ip_fsys_ctrl,
582 .ctrlbit = (1 << 13),
583 }, {
584 .name = "spi",
585 .devname = "s3c64xx-spi.0",
586 .enable = exynos4_clk_ip_peril_ctrl,
587 .ctrlbit = (1 << 16),
588 }, {
589 .name = "spi",
590 .devname = "s3c64xx-spi.1",
591 .enable = exynos4_clk_ip_peril_ctrl,
592 .ctrlbit = (1 << 17),
593 }, {
594 .name = "spi",
595 .devname = "s3c64xx-spi.2",
596 .enable = exynos4_clk_ip_peril_ctrl,
597 .ctrlbit = (1 << 18),
598 }, {
599 .name = "iis",
600 .devname = "samsung-i2s.0",
601 .enable = exynos4_clk_ip_peril_ctrl,
602 .ctrlbit = (1 << 19),
603 }, {
604 .name = "iis",
605 .devname = "samsung-i2s.1",
606 .enable = exynos4_clk_ip_peril_ctrl,
607 .ctrlbit = (1 << 20),
608 }, {
609 .name = "iis",
610 .devname = "samsung-i2s.2",
611 .enable = exynos4_clk_ip_peril_ctrl,
612 .ctrlbit = (1 << 21),
613 }, {
614 .name = "ac97",
615 .devname = "samsung-ac97",
616 .enable = exynos4_clk_ip_peril_ctrl,
617 .ctrlbit = (1 << 27),
618 }, {
619 .name = "fimg2d",
620 .enable = exynos4_clk_ip_image_ctrl,
621 .ctrlbit = (1 << 0),
622 }, {
623 .name = "mfc",
624 .devname = "s5p-mfc",
625 .enable = exynos4_clk_ip_mfc_ctrl,
626 .ctrlbit = (1 << 0),
627 }, {
628 .name = "i2c",
629 .devname = "s3c2440-i2c.0",
630 .parent = &clk_aclk_100.clk,
631 .enable = exynos4_clk_ip_peril_ctrl,
632 .ctrlbit = (1 << 6),
633 }, {
634 .name = "i2c",
635 .devname = "s3c2440-i2c.1",
636 .parent = &clk_aclk_100.clk,
637 .enable = exynos4_clk_ip_peril_ctrl,
638 .ctrlbit = (1 << 7),
639 }, {
640 .name = "i2c",
641 .devname = "s3c2440-i2c.2",
642 .parent = &clk_aclk_100.clk,
643 .enable = exynos4_clk_ip_peril_ctrl,
644 .ctrlbit = (1 << 8),
645 }, {
646 .name = "i2c",
647 .devname = "s3c2440-i2c.3",
648 .parent = &clk_aclk_100.clk,
649 .enable = exynos4_clk_ip_peril_ctrl,
650 .ctrlbit = (1 << 9),
651 }, {
652 .name = "i2c",
653 .devname = "s3c2440-i2c.4",
654 .parent = &clk_aclk_100.clk,
655 .enable = exynos4_clk_ip_peril_ctrl,
656 .ctrlbit = (1 << 10),
657 }, {
658 .name = "i2c",
659 .devname = "s3c2440-i2c.5",
660 .parent = &clk_aclk_100.clk,
661 .enable = exynos4_clk_ip_peril_ctrl,
662 .ctrlbit = (1 << 11),
663 }, {
664 .name = "i2c",
665 .devname = "s3c2440-i2c.6",
666 .parent = &clk_aclk_100.clk,
667 .enable = exynos4_clk_ip_peril_ctrl,
668 .ctrlbit = (1 << 12),
669 }, {
670 .name = "i2c",
671 .devname = "s3c2440-i2c.7",
672 .parent = &clk_aclk_100.clk,
673 .enable = exynos4_clk_ip_peril_ctrl,
674 .ctrlbit = (1 << 13),
675 }, {
676 .name = "i2c",
677 .devname = "s3c2440-hdmiphy-i2c",
678 .parent = &clk_aclk_100.clk,
679 .enable = exynos4_clk_ip_peril_ctrl,
680 .ctrlbit = (1 << 14),
681 }, {
682 .name = "SYSMMU_MDMA",
683 .enable = exynos4_clk_ip_image_ctrl,
684 .ctrlbit = (1 << 5),
685 }, {
686 .name = "SYSMMU_FIMC0",
687 .enable = exynos4_clk_ip_cam_ctrl,
688 .ctrlbit = (1 << 7),
689 }, {
690 .name = "SYSMMU_FIMC1",
691 .enable = exynos4_clk_ip_cam_ctrl,
692 .ctrlbit = (1 << 8),
693 }, {
694 .name = "SYSMMU_FIMC2",
695 .enable = exynos4_clk_ip_cam_ctrl,
696 .ctrlbit = (1 << 9),
697 }, {
698 .name = "SYSMMU_FIMC3",
699 .enable = exynos4_clk_ip_cam_ctrl,
700 .ctrlbit = (1 << 10),
701 }, {
702 .name = "SYSMMU_JPEG",
703 .enable = exynos4_clk_ip_cam_ctrl,
704 .ctrlbit = (1 << 11),
705 }, {
706 .name = "SYSMMU_FIMD0",
707 .enable = exynos4_clk_ip_lcd0_ctrl,
708 .ctrlbit = (1 << 4),
709 }, {
710 .name = "SYSMMU_FIMD1",
711 .enable = exynos4_clk_ip_lcd1_ctrl,
712 .ctrlbit = (1 << 4),
713 }, {
714 .name = "SYSMMU_PCIe",
715 .enable = exynos4_clk_ip_fsys_ctrl,
716 .ctrlbit = (1 << 18),
717 }, {
718 .name = "SYSMMU_G2D",
719 .enable = exynos4_clk_ip_image_ctrl,
720 .ctrlbit = (1 << 3),
721 }, {
722 .name = "SYSMMU_ROTATOR",
723 .enable = exynos4_clk_ip_image_ctrl,
724 .ctrlbit = (1 << 4),
725 }, {
726 .name = "SYSMMU_TV",
727 .enable = exynos4_clk_ip_tv_ctrl,
728 .ctrlbit = (1 << 4),
729 }, {
730 .name = "SYSMMU_MFC_L",
731 .enable = exynos4_clk_ip_mfc_ctrl,
732 .ctrlbit = (1 << 1),
733 }, {
734 .name = "SYSMMU_MFC_R",
735 .enable = exynos4_clk_ip_mfc_ctrl,
736 .ctrlbit = (1 << 2),
737 }
738 };
739
740 static struct clk init_clocks[] = {
741 {
742 .name = "uart",
743 .devname = "s5pv210-uart.0",
744 .enable = exynos4_clk_ip_peril_ctrl,
745 .ctrlbit = (1 << 0),
746 }, {
747 .name = "uart",
748 .devname = "s5pv210-uart.1",
749 .enable = exynos4_clk_ip_peril_ctrl,
750 .ctrlbit = (1 << 1),
751 }, {
752 .name = "uart",
753 .devname = "s5pv210-uart.2",
754 .enable = exynos4_clk_ip_peril_ctrl,
755 .ctrlbit = (1 << 2),
756 }, {
757 .name = "uart",
758 .devname = "s5pv210-uart.3",
759 .enable = exynos4_clk_ip_peril_ctrl,
760 .ctrlbit = (1 << 3),
761 }, {
762 .name = "uart",
763 .devname = "s5pv210-uart.4",
764 .enable = exynos4_clk_ip_peril_ctrl,
765 .ctrlbit = (1 << 4),
766 }, {
767 .name = "uart",
768 .devname = "s5pv210-uart.5",
769 .enable = exynos4_clk_ip_peril_ctrl,
770 .ctrlbit = (1 << 5),
771 }
772 };
773
774 static struct clk clk_pdma0 = {
775 .name = "dma",
776 .devname = "dma-pl330.0",
777 .enable = exynos4_clk_ip_fsys_ctrl,
778 .ctrlbit = (1 << 0),
779 };
780
781 static struct clk clk_pdma1 = {
782 .name = "dma",
783 .devname = "dma-pl330.1",
784 .enable = exynos4_clk_ip_fsys_ctrl,
785 .ctrlbit = (1 << 1),
786 };
787
788 struct clk *clkset_group_list[] = {
789 [0] = &clk_ext_xtal_mux,
790 [1] = &clk_xusbxti,
791 [2] = &clk_sclk_hdmi27m,
792 [3] = &clk_sclk_usbphy0,
793 [4] = &clk_sclk_usbphy1,
794 [5] = &clk_sclk_hdmiphy,
795 [6] = &clk_mout_mpll.clk,
796 [7] = &clk_mout_epll.clk,
797 [8] = &clk_sclk_vpll.clk,
798 };
799
800 struct clksrc_sources clkset_group = {
801 .sources = clkset_group_list,
802 .nr_sources = ARRAY_SIZE(clkset_group_list),
803 };
804
805 static struct clk *clkset_mout_g2d0_list[] = {
806 [0] = &clk_mout_mpll.clk,
807 [1] = &clk_sclk_apll.clk,
808 };
809
810 static struct clksrc_sources clkset_mout_g2d0 = {
811 .sources = clkset_mout_g2d0_list,
812 .nr_sources = ARRAY_SIZE(clkset_mout_g2d0_list),
813 };
814
815 static struct clksrc_clk clk_mout_g2d0 = {
816 .clk = {
817 .name = "mout_g2d0",
818 },
819 .sources = &clkset_mout_g2d0,
820 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
821 };
822
823 static struct clk *clkset_mout_g2d1_list[] = {
824 [0] = &clk_mout_epll.clk,
825 [1] = &clk_sclk_vpll.clk,
826 };
827
828 static struct clksrc_sources clkset_mout_g2d1 = {
829 .sources = clkset_mout_g2d1_list,
830 .nr_sources = ARRAY_SIZE(clkset_mout_g2d1_list),
831 };
832
833 static struct clksrc_clk clk_mout_g2d1 = {
834 .clk = {
835 .name = "mout_g2d1",
836 },
837 .sources = &clkset_mout_g2d1,
838 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
839 };
840
841 static struct clk *clkset_mout_g2d_list[] = {
842 [0] = &clk_mout_g2d0.clk,
843 [1] = &clk_mout_g2d1.clk,
844 };
845
846 static struct clksrc_sources clkset_mout_g2d = {
847 .sources = clkset_mout_g2d_list,
848 .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list),
849 };
850
851 static struct clk *clkset_mout_mfc0_list[] = {
852 [0] = &clk_mout_mpll.clk,
853 [1] = &clk_sclk_apll.clk,
854 };
855
856 static struct clksrc_sources clkset_mout_mfc0 = {
857 .sources = clkset_mout_mfc0_list,
858 .nr_sources = ARRAY_SIZE(clkset_mout_mfc0_list),
859 };
860
861 static struct clksrc_clk clk_mout_mfc0 = {
862 .clk = {
863 .name = "mout_mfc0",
864 },
865 .sources = &clkset_mout_mfc0,
866 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
867 };
868
869 static struct clk *clkset_mout_mfc1_list[] = {
870 [0] = &clk_mout_epll.clk,
871 [1] = &clk_sclk_vpll.clk,
872 };
873
874 static struct clksrc_sources clkset_mout_mfc1 = {
875 .sources = clkset_mout_mfc1_list,
876 .nr_sources = ARRAY_SIZE(clkset_mout_mfc1_list),
877 };
878
879 static struct clksrc_clk clk_mout_mfc1 = {
880 .clk = {
881 .name = "mout_mfc1",
882 },
883 .sources = &clkset_mout_mfc1,
884 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
885 };
886
887 static struct clk *clkset_mout_mfc_list[] = {
888 [0] = &clk_mout_mfc0.clk,
889 [1] = &clk_mout_mfc1.clk,
890 };
891
892 static struct clksrc_sources clkset_mout_mfc = {
893 .sources = clkset_mout_mfc_list,
894 .nr_sources = ARRAY_SIZE(clkset_mout_mfc_list),
895 };
896
897 static struct clk *clkset_sclk_dac_list[] = {
898 [0] = &clk_sclk_vpll.clk,
899 [1] = &clk_sclk_hdmiphy,
900 };
901
902 static struct clksrc_sources clkset_sclk_dac = {
903 .sources = clkset_sclk_dac_list,
904 .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list),
905 };
906
907 static struct clksrc_clk clk_sclk_dac = {
908 .clk = {
909 .name = "sclk_dac",
910 .enable = exynos4_clksrc_mask_tv_ctrl,
911 .ctrlbit = (1 << 8),
912 },
913 .sources = &clkset_sclk_dac,
914 .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 8, .size = 1 },
915 };
916
917 static struct clksrc_clk clk_sclk_pixel = {
918 .clk = {
919 .name = "sclk_pixel",
920 .parent = &clk_sclk_vpll.clk,
921 },
922 .reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 },
923 };
924
925 static struct clk *clkset_sclk_hdmi_list[] = {
926 [0] = &clk_sclk_pixel.clk,
927 [1] = &clk_sclk_hdmiphy,
928 };
929
930 static struct clksrc_sources clkset_sclk_hdmi = {
931 .sources = clkset_sclk_hdmi_list,
932 .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list),
933 };
934
935 static struct clksrc_clk clk_sclk_hdmi = {
936 .clk = {
937 .name = "sclk_hdmi",
938 .enable = exynos4_clksrc_mask_tv_ctrl,
939 .ctrlbit = (1 << 0),
940 },
941 .sources = &clkset_sclk_hdmi,
942 .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 0, .size = 1 },
943 };
944
945 static struct clk *clkset_sclk_mixer_list[] = {
946 [0] = &clk_sclk_dac.clk,
947 [1] = &clk_sclk_hdmi.clk,
948 };
949
950 static struct clksrc_sources clkset_sclk_mixer = {
951 .sources = clkset_sclk_mixer_list,
952 .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list),
953 };
954
955 static struct clksrc_clk clk_sclk_mixer = {
956 .clk = {
957 .name = "sclk_mixer",
958 .enable = exynos4_clksrc_mask_tv_ctrl,
959 .ctrlbit = (1 << 4),
960 },
961 .sources = &clkset_sclk_mixer,
962 .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 4, .size = 1 },
963 };
964
965 static struct clksrc_clk *sclk_tv[] = {
966 &clk_sclk_dac,
967 &clk_sclk_pixel,
968 &clk_sclk_hdmi,
969 &clk_sclk_mixer,
970 };
971
972 static struct clksrc_clk clk_dout_mmc0 = {
973 .clk = {
974 .name = "dout_mmc0",
975 },
976 .sources = &clkset_group,
977 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
978 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
979 };
980
981 static struct clksrc_clk clk_dout_mmc1 = {
982 .clk = {
983 .name = "dout_mmc1",
984 },
985 .sources = &clkset_group,
986 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
987 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
988 };
989
990 static struct clksrc_clk clk_dout_mmc2 = {
991 .clk = {
992 .name = "dout_mmc2",
993 },
994 .sources = &clkset_group,
995 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
996 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
997 };
998
999 static struct clksrc_clk clk_dout_mmc3 = {
1000 .clk = {
1001 .name = "dout_mmc3",
1002 },
1003 .sources = &clkset_group,
1004 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
1005 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1006 };
1007
1008 static struct clksrc_clk clk_dout_mmc4 = {
1009 .clk = {
1010 .name = "dout_mmc4",
1011 },
1012 .sources = &clkset_group,
1013 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
1014 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1015 };
1016
1017 static struct clksrc_clk clksrcs[] = {
1018 {
1019 .clk = {
1020 .name = "sclk_pwm",
1021 .enable = exynos4_clksrc_mask_peril0_ctrl,
1022 .ctrlbit = (1 << 24),
1023 },
1024 .sources = &clkset_group,
1025 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
1026 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
1027 }, {
1028 .clk = {
1029 .name = "sclk_csis",
1030 .devname = "s5p-mipi-csis.0",
1031 .enable = exynos4_clksrc_mask_cam_ctrl,
1032 .ctrlbit = (1 << 24),
1033 },
1034 .sources = &clkset_group,
1035 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
1036 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
1037 }, {
1038 .clk = {
1039 .name = "sclk_csis",
1040 .devname = "s5p-mipi-csis.1",
1041 .enable = exynos4_clksrc_mask_cam_ctrl,
1042 .ctrlbit = (1 << 28),
1043 },
1044 .sources = &clkset_group,
1045 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
1046 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
1047 }, {
1048 .clk = {
1049 .name = "sclk_cam0",
1050 .enable = exynos4_clksrc_mask_cam_ctrl,
1051 .ctrlbit = (1 << 16),
1052 },
1053 .sources = &clkset_group,
1054 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
1055 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
1056 }, {
1057 .clk = {
1058 .name = "sclk_cam1",
1059 .enable = exynos4_clksrc_mask_cam_ctrl,
1060 .ctrlbit = (1 << 20),
1061 },
1062 .sources = &clkset_group,
1063 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
1064 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
1065 }, {
1066 .clk = {
1067 .name = "sclk_fimc",
1068 .devname = "exynos4-fimc.0",
1069 .enable = exynos4_clksrc_mask_cam_ctrl,
1070 .ctrlbit = (1 << 0),
1071 },
1072 .sources = &clkset_group,
1073 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
1074 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
1075 }, {
1076 .clk = {
1077 .name = "sclk_fimc",
1078 .devname = "exynos4-fimc.1",
1079 .enable = exynos4_clksrc_mask_cam_ctrl,
1080 .ctrlbit = (1 << 4),
1081 },
1082 .sources = &clkset_group,
1083 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
1084 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
1085 }, {
1086 .clk = {
1087 .name = "sclk_fimc",
1088 .devname = "exynos4-fimc.2",
1089 .enable = exynos4_clksrc_mask_cam_ctrl,
1090 .ctrlbit = (1 << 8),
1091 },
1092 .sources = &clkset_group,
1093 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
1094 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
1095 }, {
1096 .clk = {
1097 .name = "sclk_fimc",
1098 .devname = "exynos4-fimc.3",
1099 .enable = exynos4_clksrc_mask_cam_ctrl,
1100 .ctrlbit = (1 << 12),
1101 },
1102 .sources = &clkset_group,
1103 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
1104 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
1105 }, {
1106 .clk = {
1107 .name = "sclk_fimd",
1108 .devname = "exynos4-fb.0",
1109 .enable = exynos4_clksrc_mask_lcd0_ctrl,
1110 .ctrlbit = (1 << 0),
1111 },
1112 .sources = &clkset_group,
1113 .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
1114 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
1115 }, {
1116 .clk = {
1117 .name = "sclk_fimg2d",
1118 },
1119 .sources = &clkset_mout_g2d,
1120 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
1121 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
1122 }, {
1123 .clk = {
1124 .name = "sclk_mfc",
1125 .devname = "s5p-mfc",
1126 },
1127 .sources = &clkset_mout_mfc,
1128 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
1129 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
1130 }, {
1131 .clk = {
1132 .name = "sclk_dwmmc",
1133 .parent = &clk_dout_mmc4.clk,
1134 .enable = exynos4_clksrc_mask_fsys_ctrl,
1135 .ctrlbit = (1 << 16),
1136 },
1137 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1138 }
1139 };
1140
1141 static struct clksrc_clk clk_sclk_uart0 = {
1142 .clk = {
1143 .name = "uclk1",
1144 .devname = "exynos4210-uart.0",
1145 .enable = exynos4_clksrc_mask_peril0_ctrl,
1146 .ctrlbit = (1 << 0),
1147 },
1148 .sources = &clkset_group,
1149 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1150 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1151 };
1152
1153 static struct clksrc_clk clk_sclk_uart1 = {
1154 .clk = {
1155 .name = "uclk1",
1156 .devname = "exynos4210-uart.1",
1157 .enable = exynos4_clksrc_mask_peril0_ctrl,
1158 .ctrlbit = (1 << 4),
1159 },
1160 .sources = &clkset_group,
1161 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1162 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1163 };
1164
1165 static struct clksrc_clk clk_sclk_uart2 = {
1166 .clk = {
1167 .name = "uclk1",
1168 .devname = "exynos4210-uart.2",
1169 .enable = exynos4_clksrc_mask_peril0_ctrl,
1170 .ctrlbit = (1 << 8),
1171 },
1172 .sources = &clkset_group,
1173 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1174 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1175 };
1176
1177 static struct clksrc_clk clk_sclk_uart3 = {
1178 .clk = {
1179 .name = "uclk1",
1180 .devname = "exynos4210-uart.3",
1181 .enable = exynos4_clksrc_mask_peril0_ctrl,
1182 .ctrlbit = (1 << 12),
1183 },
1184 .sources = &clkset_group,
1185 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1186 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1187 };
1188
1189 static struct clksrc_clk clk_sclk_mmc0 = {
1190 .clk = {
1191 .name = "sclk_mmc",
1192 .devname = "s3c-sdhci.0",
1193 .parent = &clk_dout_mmc0.clk,
1194 .enable = exynos4_clksrc_mask_fsys_ctrl,
1195 .ctrlbit = (1 << 0),
1196 },
1197 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1198 };
1199
1200 static struct clksrc_clk clk_sclk_mmc1 = {
1201 .clk = {
1202 .name = "sclk_mmc",
1203 .devname = "s3c-sdhci.1",
1204 .parent = &clk_dout_mmc1.clk,
1205 .enable = exynos4_clksrc_mask_fsys_ctrl,
1206 .ctrlbit = (1 << 4),
1207 },
1208 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1209 };
1210
1211 static struct clksrc_clk clk_sclk_mmc2 = {
1212 .clk = {
1213 .name = "sclk_mmc",
1214 .devname = "s3c-sdhci.2",
1215 .parent = &clk_dout_mmc2.clk,
1216 .enable = exynos4_clksrc_mask_fsys_ctrl,
1217 .ctrlbit = (1 << 8),
1218 },
1219 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1220 };
1221
1222 static struct clksrc_clk clk_sclk_mmc3 = {
1223 .clk = {
1224 .name = "sclk_mmc",
1225 .devname = "s3c-sdhci.3",
1226 .parent = &clk_dout_mmc3.clk,
1227 .enable = exynos4_clksrc_mask_fsys_ctrl,
1228 .ctrlbit = (1 << 12),
1229 },
1230 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1231 };
1232
1233 static struct clksrc_clk clk_sclk_spi0 = {
1234 .clk = {
1235 .name = "sclk_spi",
1236 .devname = "s3c64xx-spi.0",
1237 .enable = exynos4_clksrc_mask_peril1_ctrl,
1238 .ctrlbit = (1 << 16),
1239 },
1240 .sources = &clkset_group,
1241 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1242 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1243 };
1244
1245 static struct clksrc_clk clk_sclk_spi1 = {
1246 .clk = {
1247 .name = "sclk_spi",
1248 .devname = "s3c64xx-spi.1",
1249 .enable = exynos4_clksrc_mask_peril1_ctrl,
1250 .ctrlbit = (1 << 20),
1251 },
1252 .sources = &clkset_group,
1253 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1254 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1255 };
1256
1257 static struct clksrc_clk clk_sclk_spi2 = {
1258 .clk = {
1259 .name = "sclk_spi",
1260 .devname = "s3c64xx-spi.2",
1261 .enable = exynos4_clksrc_mask_peril1_ctrl,
1262 .ctrlbit = (1 << 24),
1263 },
1264 .sources = &clkset_group,
1265 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1266 .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1267 };
1268
1269 /* Clock initialization code */
1270 static struct clksrc_clk *sysclks[] = {
1271 &clk_mout_apll,
1272 &clk_sclk_apll,
1273 &clk_mout_epll,
1274 &clk_mout_mpll,
1275 &clk_moutcore,
1276 &clk_coreclk,
1277 &clk_armclk,
1278 &clk_aclk_corem0,
1279 &clk_aclk_cores,
1280 &clk_aclk_corem1,
1281 &clk_periphclk,
1282 &clk_mout_corebus,
1283 &clk_sclk_dmc,
1284 &clk_aclk_cored,
1285 &clk_aclk_corep,
1286 &clk_aclk_acp,
1287 &clk_pclk_acp,
1288 &clk_vpllsrc,
1289 &clk_sclk_vpll,
1290 &clk_aclk_200,
1291 &clk_aclk_100,
1292 &clk_aclk_160,
1293 &clk_aclk_133,
1294 &clk_dout_mmc0,
1295 &clk_dout_mmc1,
1296 &clk_dout_mmc2,
1297 &clk_dout_mmc3,
1298 &clk_dout_mmc4,
1299 &clk_mout_mfc0,
1300 &clk_mout_mfc1,
1301 };
1302
1303 static struct clk *clk_cdev[] = {
1304 &clk_pdma0,
1305 &clk_pdma1,
1306 };
1307
1308 static struct clksrc_clk *clksrc_cdev[] = {
1309 &clk_sclk_uart0,
1310 &clk_sclk_uart1,
1311 &clk_sclk_uart2,
1312 &clk_sclk_uart3,
1313 &clk_sclk_mmc0,
1314 &clk_sclk_mmc1,
1315 &clk_sclk_mmc2,
1316 &clk_sclk_mmc3,
1317 &clk_sclk_spi0,
1318 &clk_sclk_spi1,
1319 &clk_sclk_spi2,
1320
1321 };
1322
1323 static struct clk_lookup exynos4_clk_lookup[] = {
1324 CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &clk_sclk_uart0.clk),
1325 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk),
1326 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk),
1327 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk),
1328 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1329 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1330 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1331 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
1332 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),
1333 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),
1334 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &clk_sclk_spi0.clk),
1335 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &clk_sclk_spi1.clk),
1336 CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &clk_sclk_spi2.clk),
1337 };
1338
1339 static int xtal_rate;
1340
1341 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1342 {
1343 if (soc_is_exynos4210())
1344 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
1345 pll_4508);
1346 else if (soc_is_exynos4212() || soc_is_exynos4412())
1347 return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
1348 else
1349 return 0;
1350 }
1351
1352 static struct clk_ops exynos4_fout_apll_ops = {
1353 .get_rate = exynos4_fout_apll_get_rate,
1354 };
1355
1356 static u32 vpll_div[][8] = {
1357 { 54000000, 3, 53, 3, 1024, 0, 17, 0 },
1358 { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
1359 };
1360
1361 static unsigned long exynos4_vpll_get_rate(struct clk *clk)
1362 {
1363 return clk->rate;
1364 }
1365
1366 static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
1367 {
1368 unsigned int vpll_con0, vpll_con1 = 0;
1369 unsigned int i;
1370
1371 /* Return if nothing changed */
1372 if (clk->rate == rate)
1373 return 0;
1374
1375 vpll_con0 = __raw_readl(S5P_VPLL_CON0);
1376 vpll_con0 &= ~(0x1 << 27 | \
1377 PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
1378 PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1379 PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1380
1381 vpll_con1 = __raw_readl(S5P_VPLL_CON1);
1382 vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \
1383 PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
1384 PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
1385
1386 for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
1387 if (vpll_div[i][0] == rate) {
1388 vpll_con0 |= vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
1389 vpll_con0 |= vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
1390 vpll_con0 |= vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
1391 vpll_con1 |= vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
1392 vpll_con1 |= vpll_div[i][5] << PLL46XX_MFR_SHIFT;
1393 vpll_con1 |= vpll_div[i][6] << PLL46XX_MRR_SHIFT;
1394 vpll_con0 |= vpll_div[i][7] << 27;
1395 break;
1396 }
1397 }
1398
1399 if (i == ARRAY_SIZE(vpll_div)) {
1400 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1401 __func__);
1402 return -EINVAL;
1403 }
1404
1405 __raw_writel(vpll_con0, S5P_VPLL_CON0);
1406 __raw_writel(vpll_con1, S5P_VPLL_CON1);
1407
1408 /* Wait for VPLL lock */
1409 while (!(__raw_readl(S5P_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
1410 continue;
1411
1412 clk->rate = rate;
1413 return 0;
1414 }
1415
1416 static struct clk_ops exynos4_vpll_ops = {
1417 .get_rate = exynos4_vpll_get_rate,
1418 .set_rate = exynos4_vpll_set_rate,
1419 };
1420
1421 void __init_or_cpufreq exynos4_setup_clocks(void)
1422 {
1423 struct clk *xtal_clk;
1424 unsigned long apll = 0;
1425 unsigned long mpll = 0;
1426 unsigned long epll = 0;
1427 unsigned long vpll = 0;
1428 unsigned long vpllsrc;
1429 unsigned long xtal;
1430 unsigned long armclk;
1431 unsigned long sclk_dmc;
1432 unsigned long aclk_200;
1433 unsigned long aclk_100;
1434 unsigned long aclk_160;
1435 unsigned long aclk_133;
1436 unsigned int ptr;
1437
1438 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1439
1440 xtal_clk = clk_get(NULL, "xtal");
1441 BUG_ON(IS_ERR(xtal_clk));
1442
1443 xtal = clk_get_rate(xtal_clk);
1444
1445 xtal_rate = xtal;
1446
1447 clk_put(xtal_clk);
1448
1449 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1450
1451 if (soc_is_exynos4210()) {
1452 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0),
1453 pll_4508);
1454 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0),
1455 pll_4508);
1456 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
1457 __raw_readl(S5P_EPLL_CON1), pll_4600);
1458
1459 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1460 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1461 __raw_readl(S5P_VPLL_CON1), pll_4650c);
1462 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1463 apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
1464 mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
1465 epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),
1466 __raw_readl(S5P_EPLL_CON1));
1467
1468 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1469 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1470 __raw_readl(S5P_VPLL_CON1));
1471 } else {
1472 /* nothing */
1473 }
1474
1475 clk_fout_apll.ops = &exynos4_fout_apll_ops;
1476 clk_fout_mpll.rate = mpll;
1477 clk_fout_epll.rate = epll;
1478 clk_fout_vpll.ops = &exynos4_vpll_ops;
1479 clk_fout_vpll.rate = vpll;
1480
1481 printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1482 apll, mpll, epll, vpll);
1483
1484 armclk = clk_get_rate(&clk_armclk.clk);
1485 sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
1486
1487 aclk_200 = clk_get_rate(&clk_aclk_200.clk);
1488 aclk_100 = clk_get_rate(&clk_aclk_100.clk);
1489 aclk_160 = clk_get_rate(&clk_aclk_160.clk);
1490 aclk_133 = clk_get_rate(&clk_aclk_133.clk);
1491
1492 printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1493 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1494 armclk, sclk_dmc, aclk_200,
1495 aclk_100, aclk_160, aclk_133);
1496
1497 clk_f.rate = armclk;
1498 clk_h.rate = sclk_dmc;
1499 clk_p.rate = aclk_100;
1500
1501 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1502 s3c_set_clksrc(&clksrcs[ptr], true);
1503 }
1504
1505 static struct clk *clks[] __initdata = {
1506 &clk_sclk_hdmi27m,
1507 &clk_sclk_hdmiphy,
1508 &clk_sclk_usbphy0,
1509 &clk_sclk_usbphy1,
1510 };
1511
1512 #ifdef CONFIG_PM_SLEEP
1513 static int exynos4_clock_suspend(void)
1514 {
1515 s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1516 return 0;
1517 }
1518
1519 static void exynos4_clock_resume(void)
1520 {
1521 s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1522 }
1523
1524 #else
1525 #define exynos4_clock_suspend NULL
1526 #define exynos4_clock_resume NULL
1527 #endif
1528
1529 struct syscore_ops exynos4_clock_syscore_ops = {
1530 .suspend = exynos4_clock_suspend,
1531 .resume = exynos4_clock_resume,
1532 };
1533
1534 void __init exynos4_register_clocks(void)
1535 {
1536 int ptr;
1537
1538 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1539
1540 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1541 s3c_register_clksrc(sysclks[ptr], 1);
1542
1543 for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
1544 s3c_register_clksrc(sclk_tv[ptr], 1);
1545
1546 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
1547 s3c_register_clksrc(clksrc_cdev[ptr], 1);
1548
1549 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1550 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1551
1552 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
1553 for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1554 s3c_disable_clocks(clk_cdev[ptr], 1);
1555
1556 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1557 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1558 clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
1559
1560 register_syscore_ops(&exynos4_clock_syscore_ops);
1561 s3c24xx_register_clock(&dummy_apb_pclk);
1562
1563 s3c_pwmclk_init();
1564 }