spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / mach-exynos / headsmp.S
blob5364d4bfa8bc79efe6d51b27ff361811d98b8227
1 /*
2  *  linux/arch/arm/mach-exynos4/headsmp.S
3  *
4  *  Cloned from linux/arch/arm/mach-realview/headsmp.S
5  *
6  *  Copyright (c) 2003 ARM Limited
7  *  All Rights Reserved
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  */
13 #include <linux/linkage.h>
14 #include <linux/init.h>
16         __CPUINIT
19  * exynos4 specific entry point for secondary CPUs.  This provides
20  * a "holding pen" into which all secondary cores are held until we're
21  * ready for them to initialise.
22  */
23 ENTRY(exynos4_secondary_startup)
24         mrc     p15, 0, r0, c0, c0, 5
25         and     r0, r0, #15
26         adr     r4, 1f
27         ldmia   r4, {r5, r6}
28         sub     r4, r4, r5
29         add     r6, r6, r4
30 pen:    ldr     r7, [r6]
31         cmp     r7, r0
32         bne     pen
34         /*
35          * we've been released from the holding pen: secondary_stack
36          * should now contain the SVC stack for this core
37          */
38         b       secondary_startup
39 ENDPROC(exynos4_secondary_startup)
41         .align 2
42 1:      .long   .
43         .long   pen_release